JP6162800B2 - 素子収納用パッケージおよび実装構造体 - Google Patents
素子収納用パッケージおよび実装構造体 Download PDFInfo
- Publication number
- JP6162800B2 JP6162800B2 JP2015519843A JP2015519843A JP6162800B2 JP 6162800 B2 JP6162800 B2 JP 6162800B2 JP 2015519843 A JP2015519843 A JP 2015519843A JP 2015519843 A JP2015519843 A JP 2015519843A JP 6162800 B2 JP6162800 B2 JP 6162800B2
- Authority
- JP
- Japan
- Prior art keywords
- frame
- input
- output terminal
- recess
- ground
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
- H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6683—High-frequency adaptations for monolithic microwave integrated circuit [MMIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1301—Thyristor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/141—Analog devices
- H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/163—Connection portion, e.g. seal
- H01L2924/164—Material
- H01L2924/165—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/163—Connection portion, e.g. seal
- H01L2924/164—Material
- H01L2924/1659—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
Description
られた、枠体の内側と枠体の外側とを電気的に接続する誘電体層からなる入出力端子とを備えている。入出力端子は、枠体の内側から枠体の外側まで形成された、複数の配線導体と、枠体の外側に突出するように積層される誘電体層の端部の角部に形成されるとともに、内面に接地金属層が設けられた窪みを有するグランド層と、枠体外の複数の配線導体のそれぞれに接続されたリード端子と、グランド層に接続されたグランド端子とを有している。入出力端子は、前記リード端子と前記グランド端子との間および前記リード端子同士の間に凹部が形成されている。
実装構造体1は、図1に示すように、素子収納用パッケージ2と、素子収納用パッケージ2の実装領域Rに設けられた素子3とを備えている。素子収納用パッケージ2は、例えば、半導体素子、トランジスタ、レーザーダイオード、フォトダイオードまたはサイリスタ等の能動素子あるいは抵抗器、コンデンサ、太陽電池、圧電素子、水晶振動子またはセラミック発振子等の受動素子からなる単数または複数の素子3を実装するのに用いるものである。
たグラフである。本実施形態の周波数特性のうち反射損失を実線で、比較例の周波数特性のうち反射損失を点線で示している。さらに、本実施形態の周波数特性のうち挿入損失を長破線で、比較例の周波数特性のうち挿入損失を破線で示している。なお、本実施形態は、凹部Cを有した構造であって、比較例は、凹部Cがない構造である。反射損失は、周波数が0GHzから高くなるにつれて、反射損失が0dBに近づく。また、挿入損失は、周波数が0GHzで0dBであるが、高くなるにつれて、徐々に0dBからのずれが大きくなる。そして、挿入損失が急に0dBから大きくずれ始める周波数が、いわゆる共振周波数である。
ここで、図1または図2に示す実装構造体1の製造方法を説明する。まず、素子収納用パッケージ2と素子3とを準備する。素子収納用パッケージ2の基板4および枠体5は、溶融した金属材料を型枠に鋳込んで固化させたインゴットに対して、従来周知の圧延加工または打抜き加工等の金属加工法を用いることで、所定形状に製作される。また、上述した製造方法によって入出力端子6を作製する。
Claims (4)
- 上面に素子を実装するための実装領域を有する基板と、
前記基板上に前記実装領域を取り囲むように設けられた枠体と、
前記枠体に設けられた、前記枠体の内側と前記枠体の外側とを電気的に接続する誘電体層からなる入出力端子とを備え、
前記入出力端子は、前記枠体の内側から前記枠体の外側まで形成された、複数の配線導体と、前記枠体の外側に突出するように積層される誘電体層の端部の角部に形成されるとともに、内面に接地金属層が設けられた窪みを有するグランド層と、
前記枠体外の前記複数の配線導体のそれぞれに接続されたリード端子と、前記グランド層に接続されたグランド端子とを有しており、
前記入出力端子は、前記リード端子と前記グランド端子との間および前記リード端子同士の間に凹部が形成されていることを特徴とする素子収納用パッケージ。 - 請求項1に記載の素子収納用パッケージであって、
前記凹部は、前記入出力端子の下面から前記入出力端子の側面にかけて形成されていることを特徴とする素子収納用パッケージ。 - 請求項1または請求項2に記載の素子収納用パッケージであって、
前記凹部は、前記入出力端子を下面視して、基板側の端部が前記複数の配線導体の端部よりも前記入出力端子の端部側に位置するように設けられていることを特徴とする素子収納用パッケージ。 - 請求項1ないし請求項3のいずれか1つに記載の素子収納用パッケージと、
前記素子収納用パッケージの前記実装領域に実装された素子とを備えたことを特徴とする実装構造体。
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013112989 | 2013-05-29 | ||
JP2013112989 | 2013-05-29 | ||
JP2014012353 | 2014-01-27 | ||
JP2014012353 | 2014-01-27 | ||
JP2014064303 | 2014-03-26 | ||
JP2014064303 | 2014-03-26 | ||
PCT/JP2014/063819 WO2014192687A1 (ja) | 2013-05-29 | 2014-05-26 | 素子収納用パッケージおよび実装構造体 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2014192687A1 JPWO2014192687A1 (ja) | 2017-02-23 |
JP6162800B2 true JP6162800B2 (ja) | 2017-07-12 |
Family
ID=51988718
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015519843A Active JP6162800B2 (ja) | 2013-05-29 | 2014-05-26 | 素子収納用パッケージおよび実装構造体 |
Country Status (2)
Country | Link |
---|---|
JP (1) | JP6162800B2 (ja) |
WO (1) | WO2014192687A1 (ja) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2016146439A (ja) * | 2015-02-09 | 2016-08-12 | Ngkエレクトロデバイス株式会社 | 高周波用半導体素子収納用パッケージ |
CN107534023B (zh) * | 2015-05-20 | 2020-11-06 | 京瓷株式会社 | 半导体元件封装件、半导体装置以及安装构造体 |
WO2017131092A1 (ja) | 2016-01-27 | 2017-08-03 | 京セラ株式会社 | 配線基板、光半導体素子パッケージおよび光半導体装置 |
JP6744103B2 (ja) * | 2016-01-29 | 2020-08-19 | 京セラ株式会社 | 半導体素子収納用パッケージおよび半導体装置 |
CN109417054B (zh) * | 2016-06-27 | 2022-11-15 | Ngk电子器件株式会社 | 高频用陶瓷基板及高频用半导体元件收纳封装体 |
CN111034372B (zh) * | 2017-09-11 | 2023-03-14 | Ngk电子器件株式会社 | 布线基板与柔性基板的连接构造及电子器件收纳用封装体 |
JP6923431B2 (ja) * | 2017-12-25 | 2021-08-18 | 京セラ株式会社 | 高周波基体、高周波パッケージおよび高周波モジュール |
JP7036687B2 (ja) * | 2018-07-25 | 2022-03-15 | 京セラ株式会社 | 配線基板、電子部品用パッケージおよび電子装置 |
EP3937223A4 (en) * | 2019-03-07 | 2023-02-01 | Kyocera Corporation | WIRING BOARD, ELECTRONIC COMPONENT BOX AND ELECTRONIC DEVICE |
JP7172793B2 (ja) * | 2019-03-27 | 2022-11-16 | 住友大阪セメント株式会社 | 光変調器及びそれを用いた光送信装置 |
US11889618B2 (en) * | 2019-04-25 | 2024-01-30 | Kyocera Corporation | Wiring board, electronic component package, and electronic apparatus |
WO2021049111A1 (ja) * | 2019-09-11 | 2021-03-18 | Ngkエレクトロデバイス株式会社 | 端子構造、パッケージ、および、端子構造の製造方法 |
US20230054870A1 (en) | 2020-01-24 | 2023-02-23 | Kyocera Corporation | Wiring base and electronic device |
CN114450787A (zh) * | 2020-07-20 | 2022-05-06 | 日本电信电话株式会社 | 高频封装 |
US20220375766A1 (en) * | 2020-07-30 | 2022-11-24 | Nippon Telegraph And Telephone Corporation | Manufacturing Method for High-Frequency Package |
US20240063108A1 (en) * | 2020-12-28 | 2024-02-22 | Kyocera Corporation | Semiconductor package and semiconductor electronic device |
WO2024075816A1 (ja) * | 2022-10-07 | 2024-04-11 | 京セラ株式会社 | 配線基板、配線基板を用いた電子部品実装用パッケージ、および電子モジュール |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3493301B2 (ja) * | 1998-01-26 | 2004-02-03 | 京セラ株式会社 | 高周波用入出力端子ならびに高周波用半導体素子収納用パッケージ |
JPH11330298A (ja) * | 1998-05-12 | 1999-11-30 | Murata Mfg Co Ltd | 信号端子付パッケージおよびそれを用いた電子装置 |
JP3667274B2 (ja) * | 2001-11-12 | 2005-07-06 | 京セラ株式会社 | 高周波用パッケージ |
JP5127475B2 (ja) * | 2008-01-28 | 2013-01-23 | 京セラ株式会社 | 接続基板および電子装置 |
JP5636834B2 (ja) * | 2010-09-10 | 2014-12-10 | 富士通株式会社 | 高周波回路用パッケージ及び高周波回路装置 |
JP5769474B2 (ja) * | 2011-04-06 | 2015-08-26 | 京セラ株式会社 | 端子構造体、電子部品収納用パッケージおよび電子装置 |
WO2013042627A1 (ja) * | 2011-09-22 | 2013-03-28 | 京セラ株式会社 | 電子部品載置用基板、電子部品収納用パッケージおよび電子装置 |
-
2014
- 2014-05-26 JP JP2015519843A patent/JP6162800B2/ja active Active
- 2014-05-26 WO PCT/JP2014/063819 patent/WO2014192687A1/ja active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO2014192687A1 (ja) | 2014-12-04 |
JPWO2014192687A1 (ja) | 2017-02-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6162800B2 (ja) | 素子収納用パッケージおよび実装構造体 | |
JP6093020B2 (ja) | 素子収納用パッケージおよび実装構造体 | |
JP5902825B2 (ja) | 素子収納用パッケージおよび実装構造体 | |
JP5518086B2 (ja) | 素子収納用パッケージおよび実装構造体 | |
JP6243510B2 (ja) | 電子部品収納用パッケージおよび電子装置 | |
JP6633656B2 (ja) | 配線基板、光半導体素子パッケージおよび光半導体装置 | |
JP6181777B2 (ja) | 素子収納用パッケージおよび実装構造体 | |
JP5926290B2 (ja) | 入出力部材ならびに電子部品収納用パッケージおよび電子装置 | |
JP6082114B2 (ja) | 素子収納用パッケージおよび実装構造体 | |
WO2015088028A1 (ja) | 素子収納用パッケージおよび実装構造体 | |
JP2015103619A (ja) | 素子収納用パッケージおよび実装構造体 | |
JP6030371B2 (ja) | 素子収納用パッケージおよび実装構造体 | |
WO2015029880A1 (ja) | 素子収納用パッケージおよび実装構造体 | |
JP2021064812A (ja) | 絶縁基体、半導体パッケージおよび半導体装置 | |
JP6075597B2 (ja) | 素子収納用パッケージおよび実装構造体 | |
JP5905728B2 (ja) | 素子収納用パッケージ、および実装構造体 | |
JP6208618B2 (ja) | 素子実装基板および実装構造体 | |
JP2012033543A (ja) | 素子収納用パッケージおよびこれを備えた半導体装置 | |
JP2015002206A (ja) | 素子収納用パッケージおよび実装構造体 | |
JP2011044483A (ja) | 素子収納用パッケージ、並びに実装構造体 | |
JP2014165208A (ja) | 素子収納用パッケージ、並びに実装構造体 | |
JP2004253714A (ja) | リードフレーム付き配線基板 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20161111 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170110 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170301 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20170516 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20170615 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6162800 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |