JP6157100B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP6157100B2
JP6157100B2 JP2012272137A JP2012272137A JP6157100B2 JP 6157100 B2 JP6157100 B2 JP 6157100B2 JP 2012272137 A JP2012272137 A JP 2012272137A JP 2012272137 A JP2012272137 A JP 2012272137A JP 6157100 B2 JP6157100 B2 JP 6157100B2
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Japan
Prior art keywords
semiconductor device
seal ring
tsv
dielectric constant
constant film
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JP2012272137A
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English (en)
Japanese (ja)
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JP2014120504A5 (enExample
JP2014120504A (ja
Inventor
落合　俊彦
俊彦 落合
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Renesas Electronics Corp
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Renesas Electronics Corp
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Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Priority to JP2012272137A priority Critical patent/JP6157100B2/ja
Priority to US14/077,503 priority patent/US9673153B2/en
Priority to CN201310685194.9A priority patent/CN103872047B/zh
Publication of JP2014120504A publication Critical patent/JP2014120504A/ja
Publication of JP2014120504A5 publication Critical patent/JP2014120504A5/ja
Priority to US15/585,468 priority patent/US10062655B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/213—Cross-sectional shapes or dispositions
    • H10W20/2134—TSVs extending from the semiconductor wafer into back-end-of-line layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/44—Conductive materials thereof
    • H10W20/4403—Conductive materials thereof based on metals, e.g. alloys, metal silicides
    • H10W20/4421—Conductive materials thereof based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/792—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between multiple chips

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
JP2012272137A 2012-12-13 2012-12-13 半導体装置 Active JP6157100B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2012272137A JP6157100B2 (ja) 2012-12-13 2012-12-13 半導体装置
US14/077,503 US9673153B2 (en) 2012-12-13 2013-11-12 Semiconductor device
CN201310685194.9A CN103872047B (zh) 2012-12-13 2013-12-13 半导体器件
US15/585,468 US10062655B2 (en) 2012-12-13 2017-05-03 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012272137A JP6157100B2 (ja) 2012-12-13 2012-12-13 半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2017111407A Division JP2017147475A (ja) 2017-06-06 2017-06-06 半導体装置

Publications (3)

Publication Number Publication Date
JP2014120504A JP2014120504A (ja) 2014-06-30
JP2014120504A5 JP2014120504A5 (enExample) 2015-10-08
JP6157100B2 true JP6157100B2 (ja) 2017-07-05

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JP2012272137A Active JP6157100B2 (ja) 2012-12-13 2012-12-13 半導体装置

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US (2) US9673153B2 (enExample)
JP (1) JP6157100B2 (enExample)
CN (1) CN103872047B (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105336710B (zh) * 2014-07-10 2018-03-23 中芯国际集成电路制造(上海)有限公司 一种芯片的密封环
JP6519785B2 (ja) * 2015-05-11 2019-05-29 国立研究開発法人産業技術総合研究所 貫通電極及びその製造方法、並びに半導体装置及びその製造方法
JP6713481B2 (ja) 2015-10-28 2020-06-24 オリンパス株式会社 半導体装置
CN108155155B (zh) * 2016-12-02 2020-03-10 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US11756977B2 (en) * 2018-06-21 2023-09-12 Semiconductor Components Industries, Llc Backside illumination image sensors
CN109830464A (zh) * 2019-02-15 2019-05-31 德淮半导体有限公司 半导体结构及其形成方法
US12014997B2 (en) 2021-07-01 2024-06-18 Taiwan Semiconductor Manufacturing Co., Ltd. Dummy stacked structures surrounding TSVs and method forming the same
US12211757B2 (en) * 2021-12-14 2025-01-28 Micron Technology, Inc. Semiconductor device and method of forming the same

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4502173B2 (ja) * 2003-02-03 2010-07-14 ルネサスエレクトロニクス株式会社 半導体装置及びその製造方法
JP2005142553A (ja) * 2003-10-15 2005-06-02 Toshiba Corp 半導体装置
US7049701B2 (en) * 2003-10-15 2006-05-23 Kabushiki Kaisha Toshiba Semiconductor device using insulating film of low dielectric constant as interlayer insulating film
JP4689244B2 (ja) * 2004-11-16 2011-05-25 ルネサスエレクトロニクス株式会社 半導体装置
US7224069B2 (en) * 2005-07-25 2007-05-29 Taiwan Semiconductor Manufacturing Company, Ltd. Dummy structures extending from seal ring into active circuit area of integrated circuit chip
JP5021992B2 (ja) * 2005-09-29 2012-09-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2007115988A (ja) * 2005-10-21 2007-05-10 Renesas Technology Corp 半導体装置
WO2007074530A1 (ja) 2005-12-27 2007-07-05 Fujitsu Limited 半導体装置
JP5329068B2 (ja) 2007-10-22 2013-10-30 ルネサスエレクトロニクス株式会社 半導体装置
JP2009123734A (ja) * 2007-11-12 2009-06-04 Renesas Technology Corp 半導体装置及びその製造方法
US8188578B2 (en) * 2008-05-29 2012-05-29 Mediatek Inc. Seal ring structure for integrated circuits
US8053902B2 (en) 2008-12-02 2011-11-08 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation structure for protecting dielectric layers from degradation
US8749027B2 (en) * 2009-01-07 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Robust TSV structure
US20100224878A1 (en) 2009-03-05 2010-09-09 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8299583B2 (en) * 2009-03-05 2012-10-30 International Business Machines Corporation Two-sided semiconductor structure
US8169055B2 (en) 2009-03-18 2012-05-01 International Business Machines Corporation Chip guard ring including a through-substrate via
JP2011129722A (ja) 2009-12-17 2011-06-30 Panasonic Corp 半導体装置
JP2011176047A (ja) * 2010-02-23 2011-09-08 On Semiconductor Trading Ltd 半導体装置及びその製造方法
JP2011216753A (ja) 2010-04-01 2011-10-27 Panasonic Corp 半導体装置及びその製造方法
JP5300814B2 (ja) 2010-10-14 2013-09-25 ルネサスエレクトロニクス株式会社 半導体装置
JP5685060B2 (ja) * 2010-11-18 2015-03-18 ルネサスエレクトロニクス株式会社 半導体装置
JP2012256787A (ja) * 2011-06-10 2012-12-27 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法

Also Published As

Publication number Publication date
US20140167286A1 (en) 2014-06-19
CN103872047B (zh) 2018-02-27
US10062655B2 (en) 2018-08-28
CN103872047A (zh) 2014-06-18
US20170236789A1 (en) 2017-08-17
US9673153B2 (en) 2017-06-06
JP2014120504A (ja) 2014-06-30

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