CN103872047A - 半导体器件 - Google Patents

半导体器件 Download PDF

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CN103872047A
CN103872047A CN201310685194.9A CN201310685194A CN103872047A CN 103872047 A CN103872047 A CN 103872047A CN 201310685194 A CN201310685194 A CN 201310685194A CN 103872047 A CN103872047 A CN 103872047A
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semiconductor device
sealing ring
low relative
dielectric constant
relative dielectric
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CN103872047B (zh
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落合俊彦
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Renesas Electronics Corp
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Renesas Electronics Corp
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Abstract

本发明涉及半导体器件。该半导体器件包括贯穿硅衬底的TSV。密封环被设置为从最对于硅衬底最近的第一低相对介电常数薄膜至对于硅衬底最远的第二低相对介电常数薄膜。密封环被形成为在从晶圆正面的硅衬底的鸟瞰图中围绕TSV。这就能实现包括了低相对介电常数薄膜和TSV的半导体器件中的低相对介电常数薄膜中的裂缝的产生或发展的抑制。

Description

半导体器件
技术领域
本发明涉及一种包括硅通孔的半导体器件。
背景技术
在半导体领域中，密封环用于各种用途。例如，日本未审专利申请公布No.2011-9795公开了一种半导体器件，其包括用于防止水从芯片外周上的侧面进入芯片的密封环。沿芯片的外周提供这种密封环。日本未审专利申请公布No.2011-9795也公开了一种用于例如通过设置双重密封环并设计密封环的形状而有效防止由于裂缝造成密封环毁坏的技术。
日本未审专利申请公布No.2010-161367公开了一种在制造三维集成电路时使用密封环防止离子扩散进裸片的衬底区并在裸片切割过程中防止裂缝产生的技术。
三维集成电路由一个半导体封装中的硅通孔层叠的多个半导体器件组成。以下将硅通孔称作TSV（Through-Silicon Via）。
日本未审专利申请公布No.2010-161367中公开的技术试图通过密封环包围多个TSV来实现上述目的。
发明内容
三维集成电路中的TSV连接在半导体器件之间并通常由具有低电阻的铜制成。另一方面，半导体器件中的半导体元件由硅制成。
作为TSV的材料的铜和作为半导体元件的材料的硅之间的热膨胀系数不同。因此，由于温度波动会产生热应力。特别地，对封装的半导体集成电路进行的热循环测试等会导致施加高温度载荷，由此产生相对大的热应力。
近年来，虽然推进了半导体器件的小型化，但是铜布线的寄生电容的大小变得与晶体管本身的输入/输出能力相当，且已经变得阻碍元件操作速度的提升。因此，为了减小布线间的寄生电容，具有比公知的氧化硅低的低相对介电常数的所谓的低相对介电常数薄膜通常用作绝缘膜。低相对介电常数薄膜例如是一种具有小于3.5的相对介电常数的绝缘膜，且具有低于二氧化硅的公知低相对介电常数薄膜的机械强度。
因此，存在的问题是包括TSV和低相对介电常数薄膜的半导体器件容易在低相对介电常数薄膜中形成裂缝，且所产生的裂缝会迅速发展。以下参考图12提供具体说明。
图12是示出包括用于连接至另一半导体器件的TSV并包括低相对介电常数薄膜的半导体器件的示例的截面图。如图12中所示，半导体器件10从晶圆背面至正面依次包括硅衬底20、扩散层LD、接触层LC、第一铜布线层LCU1、第一过孔层LV1、第二铜布线层LCU2、第二过孔层LV2、第三铜布线层LCU3、第三过孔层LV3、第四铜布线层LCU4、第四过孔层LV4、第五铜布线层LCU5以及铝电极30。作为半导体元件的示例，示出可为晶体管的半导体元件40。
第一铜布线层、第二铜布线层以及第三铜布线层具有比其上层布线层小的布线间距。为了减小布线间的寄生电容，低相对介电常数薄膜用作第一铜布线层LCU1和第二铜布线层LCU2之间的绝缘膜51、第二铜布线层LCU2和第三铜布线层LCU3之间的绝缘膜52以及第三铜布线层LCU3和第四铜布线层LCU4之间的绝缘膜53。注意到常用的氧化硅用作由阴影指示的绝缘膜54。
而且，提供从第一铜布线层LCU1贯穿硅衬底20的TSV60。TSV60包括TSV电极61和TSV电极焊盘62。TSV电极61连接至第一铜布线层LCU1，且TSV电极焊盘62提供至晶圆背面并连接至未示出的另一半导体器件的铝电极。
已经开发出半导体器件的若干结构，例如具有从半导体器件的背面贯穿至正面的结构以及具有从半导体器件的背面贯穿至第一布线层的底部的结构。在图12中所示的示例中的半导体器件10中，TSV60具有从晶圆背面贯穿至连接至第一铜布线层LCU1的部分的结构。而且，在图12中所示的示例中，TSV60的TSV电极61通过铜布线以及层的过孔连接至铝电极30，且半导体器件10没有其他分支的铜布线。
当施加例如热循环测试的高温载荷时，连接至TSV60的从第一铜布线层LCU1至铝电极30的部分会由于半导体器件10中的TSV60和半导体元件之间的热膨胀系数差异而向上突起或被向下拉。这会使热应力施加在这些部分附近的绝缘膜上，由此使其易于断裂。特别地，绝缘膜51至53是具有低机械强度的低相对介电常数薄膜，因此绝缘膜51至53比其他绝缘膜（未示出）更易于断裂。
说明书的描述和附图将使其他问题和新特征变得显而易见。
本发明的一个方面是一种包括硅衬底和贯穿硅衬底的TSV（硅通孔）的半导体器件。半导体器件包括从作为对于硅衬底最近的低相对介电常数薄膜的第一低相对介电常数薄膜提供至作为对于硅衬底最远的低相对介电常数薄膜的第二低相对介电常数薄膜的密封环。密封环被形成在TSV附近以在硅衬底的鸟瞰图中围绕TSV。
根据上述方面的半导体器件，能抑制低相对介电常数薄膜中裂缝的产生或发展。
附图说明
结合附图从某些实施例的以下说明将使上述和其他方面、优点和特征更加显而易见，其中：
图1是示出根据第一实施例的三维集成电路的示意图；
图2是示出图1中所示的三维集成电路中的半导体器件的截面图；
图3是示出图2中所示的半导体器件的硅衬底的鸟瞰图中的密封环和TSV之间的位置关系的示意图；
图4是示出图2中所示的半导体器件中的裂缝的位置和发展方向的示例的示意图；
图5是示出图2中所示的半导体器件的硅衬底的鸟瞰图中的裂缝的发展方向的示意图；
图6是根据第二实施例的三维集成电路中的半导体器件的截面图；
图7是根据第三实施例的三维集成电路中的半导体器件的截面图；
图8是示出图7中所示的半导体器件的硅衬底的鸟瞰图中的密封环和TSV之间的位置关系的示意图；
图9是示出根据第四实施例的半导体器件的截面图；
图10是根据第五实施例的半导体器件的截面图的一部分；
图11是根据第六实施例的半导体器件的截面图的一部分；以及
图12是示出包括TSV的公知半导体器件的示例的示意图。
具体实施方式
出于说明清楚的考虑，适当省略和简化以下说明和附图。而且，在附图中，相同部件由相同附图标记表示，且适当省略重复说明。
第一实施例
图1示出根据第一实施例的三维集成电路80。三维集成电路80由在封装基板90上层叠的四个半导体器件100组成。作为示例，封装基板90上层叠的半导体器件的数量在此是四个，但是该数量不限于此且可以是大于或等于二的任意值。
图2是三维集成电路80的半导体器件100的截面图。为了更容易进行对比，使半导体器件100中的TSV的结构与图12中所示的现有技术的半导体器件10中的TSV的结构相同。而且，为了方便说明，从硅衬底20延伸至铝电极30的方向，即从半导体器件100的底部向上延伸的方向被称为Y方向，且垂直于Y方向的方向被称为X方向。
在图2中，黑色填充的部分指示密封环110。如图2中所示，密封环110被设置为在Y方向上从最对于硅衬底20最近的低相对介电常数薄膜51（以下称为第一低相对介电常数薄膜）向上到达对于硅衬底20最远的低相对介电常数薄膜53（以下称为第二低相对介电常数薄膜）并穿过低相对介电常数薄膜53。
图3是示出密封环110的形状以及在从铝电极30到硅衬底20上的鸟瞰图中的密封环110和TSV60之间位置关系的示意图。
虽然不限于此，但在本实施例中，密封环110在硅衬底20的鸟瞰图中的形状是通过以45度切割矩形的四个角而获得的八边形。下文说明这种形状的意义。
如图3中所示，密封环110形成在TSV60附近以围绕TSV电极61并在硅衬底20的鸟瞰图中与TSV60（更具体来说是TSV电极61）的外周具有间隙。
图4示出可能产生在图2中所示的半导体器件100中的裂缝和裂缝的发展方向的示例。在半导体器件的层中，靠近连接至TSV的部分更容易断裂。在本示例中，裂缝产生在低相对介电常数薄膜52的圆周部分的区域中，并如图4中的箭头所示，裂缝的发展方向是朝半导体器件100的外周的方向。
图5示出硅衬底20的鸟瞰图中的裂缝的发展方向。图5的中心黑点指示TSV的中心，且箭头指示裂缝的发展方向。
裂缝从TSV的中心径向地向半导体器件的外周发展。在本实施例中，密封环110抑制裂缝的发展，由此抑制低相对介电常数薄膜的损坏。
密封环110还有效支撑薄膜，因此密封环110的存在还可抑制其本身裂缝的产生。
随后，说明密封环110的形状的意义。例如，假设裂缝的一个发展方向是方向1。为了防止裂缝朝方向1发展，具有基本上垂直于方向1的形状的阻挡物体似乎是有效的。
如图5中所示，裂缝径向发展。通过以45度切割矩形的四个角使作为阻挡物体的密封环110的形状形成为八边形，因此在裂缝的发展方向之中，存在更多的基本上垂直于密封环110的方向，因此能提高裂缝的阻挡效果。
第二实施例
第二实施例也涉及由多个层叠的半导体器件组成的三维集成电路。图6示出根据第二实施例的三维集成电路中的半导体器件200。
除了提供密封环210以替代密封环110之外，半导体器件200具有与半导体器件100相同的构造。注意到在图6中，密封环210也由黑色填充部分指示。
在半导体器件100中，密封环110被设置为从第一低相对介电常数薄膜51向上到达第二低相对介电常数薄膜53并贯穿第二低相对介电常数薄膜53。另一方面，如图6中所示，在半导体器件200中，密封环210向上延伸至最上层铜布线层（此处为第五铜布线层LCU5）且向下延伸至接触层LC。
通过将密封环从第一低相对介电常数薄膜51下的层向上提供至第二低相对介电常数薄膜53上的层并贯穿该层，能够进一步提高阻挡效果以避免不仅仅是在低相对介电常数薄膜中而且在另外的层中的裂缝的产生和发展。
显然，密封环的上限不限于顶层布线层，只要密封环的覆盖范围包括从第一低相对介电常数薄膜51至第二低相对介电常数薄膜53的层即可，且根据半导体器件200的布线情况可以是处于第二低相对介电常数薄膜53中或其上的任意层。类似地，对于下限来说，不限于接触层LC，而是根据半导体器件200的布线情况可以是处于第一低相对介电常数薄膜51中或其下的任意层。
第三实施例
第三实施例也涉及由多个层叠半导体器件组成的三维集成电路。图7示出根据第三实施例的三维集成电路中的半导体器件300。仅说明在图7中与半导体器件200的不同之处。
半导体器件300包括多个TSV（所示示例中为两个TSV）。如图7中所示，除TSV60之外还提供TSV360。TSV360包括TSV电极361和TSV电极焊盘362。从TSV电极361至铝电极330的连接类似于从TSV电极61至铝电极30的TSV60的连接。
而且，在半导体器件300中，提供密封环310以替代半导体器件200中的密封环210。还注意到在图7中，密封环310由黑色填充部分指示。
在从接触层LC向上至第五铜布线层LCU5并贯穿第五铜布线层LCU5的Y方向上，以与类似于密封环210的方式提供密封环310。
图8是示出从晶圆正面的硅衬底20上鸟瞰图来看的TSV60、TSV360以及密封环310之间的位置关系的示意图。
如图8中所示，密封环310形成在TSV60（更具体来说是TSV电极61）以及TSV360（具体来说是TSV电极361）附近，以围绕TSV电极61和TSV电极361。密封环310的形状是以与密封环110和密封环210类似的方式形成的八边形。
如上所述，在硅衬底的鸟瞰图中，密封环被形成为围绕多个TSV，由此抑制绝缘膜中的裂缝的产生和发展，而且与为每一个TSV都提供密封环的情况相比，还能减少密封环的数量，这有利于半导体器件的布局。
注意到图7示出其中半导体器件中包括的TSV的数量是两个且一个密封环提供用于两个TSV的示例。例如，当TSV的数量是三个或三个以上时，这些TSV可根据TSV之间的空间和半导体器件的布线情况分成多个组，且密封环可提供用于每个组。
显然，密封环310也可提供在任意层中，只要在Y方向上，下限处于第一低相对介电常数薄膜51中或其下且上限处于第二低相对介电常数薄膜53中或其上即可。
第四实施例
根据上述实施例的半导体器件是其中TSV连接至铝电极的示例。这种技术可应用于其中TSV不连接至铝电极的半导体器件。第四实施例涉及这种半导体器件。
图9示出根据第四实施例的三维集成电路中的半导体器件400。这种半导体器件400例如是三维集成电路的最顶层的半导体器件。
如图9中所示，在半导体器件400中，TSV60连通至第五铜布线层LCU5。而且，第五铜布线层LCU5通过第四过孔层LV4、第三铜布线层LCU3、第三过孔层LV3、第二铜布线层LCU2、第二过孔层LV2、第一铜布线层LCU1以及接触层LC连接至半导体元件40。
由黑色填充部分指示的密封环410被设置为从接触层LC向上至作为第五铜布线层LCU5之下的一层的铜布线层（第四铜布线层LCU4）并贯穿该层。
通过这样设置，密封环410将不会干扰从第五铜布线层LCU5至半导体元件40的布线，并且可防止低相对介电常数薄膜中的裂缝的产生和/或发展。
注意到在半导体器件400中，密封环410在向下的方向上被设置为向下到达并贯穿接触层LC，但是密封环410也可以不提供在接触层LC中而是被设置为向上到达并贯穿第一低相对介电常数薄膜51。显然，在向上的方向上，密封环410可以不被设置为向上到达并贯穿第四铜布线层LCU4，而是可以被设置为向下到达并贯穿第二低相对介电常数薄膜53。
第五实施例
如上所述，密封环被设置为从对于硅衬底最近的低相对介电常数薄膜（第一低相对介电常数薄膜）向上到达至并贯穿对于硅衬底最远的低相对介电常数薄膜（第二低相对介电常数薄膜），由此抑制低相对介电常数薄膜中的裂缝的产生和/或发展。密封环被设置为向下到达并贯穿第一低相对介电常数薄膜之下的接触层，即向下至扩散层的正面，并连接至扩散层，使得密封环可具有与衬底相同的电势。因此，密封环可用作附近半导体元件的电源。参考图9说明一个示例。
图10是根据第五实施例的三维集成电路中的半导体器件500的截面图。在图10中，仅示出向上至第二铜布线层LCU2且未示出第二铜布线层LCU2之上的层。
在半导体器件500中，由黑色填充部分指示的密封环510被设置为向下至到达并贯穿扩散层LD。
半导体元件40例如是N型晶体管，且扩散层LD是P+扩散层。半导体元件40的漏电极和源电极（GND）提供在第一铜布线层LCU1中，且通过接触层LC分别为半导体元件40的漏极端子和源极端子供电。
在这种情况下，在第一铜布线层LCU1中，密封环510通过连接布线连接至半导体元件40的漏电极，以便能为半导体元件40的源极端子供电。
第六实施例
图11中所示的根据第六实施例的半导体器件600也是其中密封环被设置为向下到达并贯穿扩散层且将电力提供至半导体元件的示例。而且在半导体器件600中，作为示例，半导体元件40是N型晶体管，且扩散层LD是P+扩散层。
TSV60通过TSV电极焊盘62连接至未示出的外部GND。在这种情况下，如图11中所示，在第一铜布线层LCU1中，密封环610通过连接线连接至半导体元件40的漏电极以及TSV60的TSV电极61，以便能将电力提供至半导体元件40的源极端子。
虽然已经根据若干实施例说明了本发明，但是本领域技术人员将认识到本发明可在随附权利要求的精神和范围内以各种变型实现，且本发明不限于上述示例。
而且，上述实施例可由本领域技术人员根据需要进行组合，且权利要求的范围不由这些实施例限定。
而且，注意到，即使在后续审查中进行修改，申请人也试图将所有要求保护的元素的等同体涵盖在内。

Claims (9)

1.一种包括硅衬底和贯穿所述硅衬底的硅通孔TSV的半导体器件，所述半导体器件包含：
密封环，所述密封环被设置为从第一低相对介电常数薄膜向下到达并贯穿第二低相对介电常数薄膜，所述第一低相对介电常数薄膜是对于所述硅衬底最近的低相对介电常数薄膜，并且所述第二低相对介电常数薄膜是对于所述硅衬底最远的低相对介电常数薄膜，
其中，在所述硅衬底上从鸟瞰图来看，所述密封环被形成在所述硅通孔TSV的附近以围绕所述硅通孔TSV。
2.根据权利要求1所述的半导体器件，其中，
所述密封环被设置为向下到达并贯穿位于所述第一低相对介电常数薄膜之下的接触层，并且连接至扩散层。
3.根据权利要求1所述的半导体器件，其中，
所述密封环被设置为向上到达并贯穿所述第二低相对介电常数薄膜。
4.根据权利要求2所述的半导体器件，其中，
所述密封环被设置为向上到达并贯穿所述第二低相对介电常数薄膜。
5.根据权利要求1所述的半导体器件，还包括多个所述硅通孔TSV，
其中，在所述硅衬底上从鸟瞰图来看，所述密封环被形成为围绕所述多个硅通孔TSV。
6.根据权利要求2所述的半导体器件，还包括多个所述硅通孔TSV，
其中，在所述硅衬底上从鸟瞰图来看，所述密封环被形成为围绕所述多个硅通孔TSV。
7.根据权利要求3所述的半导体器件，还包括多个所述硅通孔TSV，
其中，在所述硅衬底上从鸟瞰图来看，所述密封环被形成为围绕所述多个硅通孔TSV。
8.根据权利要求4所述的半导体器件，还包括多个所述硅通孔TSV，
其中，在所述硅衬底上从鸟瞰图来看，所述密封环被形成为围绕所述多个硅通孔TSV。
9.根据权利要求1至8中的任一项所述的半导体器件，其中，
在所述硅衬底上从鸟瞰图来看，所述密封环具有通过以45度切割矩形的四个角而获得的八边形形状。
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