CN103367272A - 半导体模块 - Google Patents

半导体模块 Download PDF

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Publication number
CN103367272A
CN103367272A CN201310106918XA CN201310106918A CN103367272A CN 103367272 A CN103367272 A CN 103367272A CN 201310106918X A CN201310106918X A CN 201310106918XA CN 201310106918 A CN201310106918 A CN 201310106918A CN 103367272 A CN103367272 A CN 103367272A
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Prior art keywords
semiconductor
packaging
base plate
bare chip
described semiconductor
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CN201310106918XA
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梅木昭宏
蛭田阳一
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Amkor Technology Japan Inc
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J Devices Corp
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Publication of CN103367272A publication Critical patent/CN103367272A/zh
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Abstract

本发明涉及半导体模块。本发明的课题是，解决在由封装基板、第1半导体封装和半导体裸芯片构成的半导体模块中，由于第1半导体封装的翘曲而产生引线短路、树脂封止时的未填充等问题。半导体模块（10），具有：在第1封装基板搭载半导体裸芯片并进行树脂封止而成的半导体封装（6）、半导体裸芯片（2）和第2封装基板（12），其特征在于，在所述第2封装基板（12）上搭载所述半导体封装（6），在所述半导体封装（6）上搭载所述半导体裸芯片（2）。

Description

半导体模块
技术领域
本发明涉及将半导体裸芯片（bare chip）和半导体封装（package）层叠起来的半导体模块。
背景技术
伴随着近年来的电子设备的高功能化以及轻薄短小化的要求，电子部件的高密度集成化、进而高密度安装化不断进展，用于这些电子设备的半导体装置也与以往相比不断小型化。
作为使半导体装置小型化的方法，有如下SOC（SOC：System-on-a-chip）技术：通过对一个半导体裸芯片进行微细加工而将所需的所有功能都集成于一个芯片，从而谋求安装面积的缩小化、功耗的降低化。然而，该方法由于伴随着电路的微细化导致制造成本的上升，并且扩散工序变得非常复杂，所以制造工期变长，另外不能提高制造成品率。
作为代替于此的方法，SIP（System In Package）技术备受瞩目。根据SIP，分别以最合适的制造条件制造功能不同的多个半导体裸芯片，将其封装化，在封装上适当地布线，由此能够稳定生产具有更高度的功能的集成电路。
在如上所述那样将多个半导体裸芯片收纳于1个封装的SIP中，从成品率的观点出发，要求各半导体裸芯片是预先完成检查而确认是合格品的半导体裸芯片（KGD：Known Good Die）。
为了得到KGD，在半导体晶片的状态或者通过切割将半导体晶片分离为单个的半导体裸芯片的状态下，使探针与设置于这些半导体裸芯片的表面的电极接触而进行探针检查，基于该检查结果甄别半导体裸芯片，仅对甄别为合格品的半导体裸芯片进行老化检查（burn-in test）等筛选检查。
然而，如果对半导体裸芯片直接进行探针检查，则存在半导体裸芯片单片或半导体芯片破裂，或者在检查中使用的插口（socket）、探针、测试器（tester，电路检测器）等也不能简便地操作的问题。
因此，为了解决上述课题，提出了一种半导体装置，在将半导体裸芯片进行树脂封止而成的树脂封止封装的表面设置有连接于半导体裸芯片的电极的电极、和与试验用设备连接的试验用电极（专利文献1：日本特开2002-40095号公报）。该半导体装置在安装于安装基板之前被封装化，所以不会产生芯片破裂等问题，具有能够使用廉价的检查插口进行检查的优点。
而且，也提出了一种使用上述的封装化的半导体装置而SIP化的半导体模块（专利文献2）。
将该半导体模块表示于图12。
图12（a）示出如下得到的第1半导体封装6：对中介层（interposer）4安装半导体裸芯片1a，在其上层叠隔片15，进而在其上层叠半导体裸芯片1b，通过引线接合布线引线9，然后通过树脂5进行树脂封止。
图12（b）表示在封装基板12按顺序层叠半导体裸芯片2、隔片15以及所述第1半导体封装6、并进行树脂封止而SIP化的半导体模块10。
另外，在图示例中第1半导体封装6为与半导体裸芯片2大致相同大小，所以将隔片15插入第1半导体封装6与半导体裸芯片2之间以使得半导体裸芯片2的电极焊盘不被遮住。
另外，在专利文献3中，记载了：在封装基板搭载半导体裸芯片并进行树脂封止而做成第1半导体封装，然后搭载第2半导体封装而形成半导体模块。
然而，这样的半导体模块经过复杂的工序而导致成本上升以及成品率降低，并且不适于封装厚度的薄型化。另外，在由层叠于上述第1半导体封装上的测试完的半导体封装构成的半导体模块中，存在下述的技术问题：测试后的第1半导体封装由于组装热履历中的翘曲变动而与下层的封装的引线接触，会产生引线短路，或者由于下层封装比测试后的封装小而产生悬垂，产生树脂封止时的未填充等。
专利文献1：日本特开2002-40095号公报
专利文献2：日本专利第4303772号公报
专利文献3：美国专利第7057269号说明书
发明内容
本发明的目的在于，解决在由封装基板、第1半导体封装、半导体裸芯片构成的半导体模块中，由于第1半导体封装的翘曲而产生引线短路、树脂封止时的未填充等问题。
本发明者发现，在由封装基板、第1半导体封装、半导体裸芯片构成的半导体模块中，搭载在封装基板上搭载半导体裸芯片并进行树脂封止而成的第1半导体封装，在该第1半导体封装上搭载半导体裸芯片，将第1半导体封装和所述半导体裸芯片树脂封止，由此能够解决上述的问题，从而完成了本发明。即，本发明为如下所述的发明。
（1）一种半导体模块，具有：在第1封装基板上搭载半导体裸芯片并进行树脂封止而成的半导体封装、半导体裸芯片和第2封装基板，其特征在于：在所述第2封装基板搭载所述半导体封装，在所述半导体封装上搭载所述半导体裸芯片。
（2）如（1）所述的半导体模块，其特征在于：所述半导体封装在与树脂面相反一侧的面经由电极焊盘通过软钎料与第2封装基板电连接。
（3）如（1）所述的半导体模块，其特征在于：所述半导体封装在树脂面与第2封装基板接合，通过引线接合与第2封装基板电连接。
（4）如（1）～（3）的任意一项所述的半导体模块，其特征在于：搭载于所述半导体封装的半导体裸芯片通过引线接合与第2封装基板电连接。
（5）如（1）～（4）的任意一项所述的半导体模块，其特征在于：在所述半导体封装上层叠搭载2个以上所述半导体裸芯片，所述半导体裸芯片之间的电连接设为COC构造。
（6）如（1）～（5）的任意一项所述的半导体模块，其特征在于：在所述半导体封装上层叠搭载2个以上所述半导体裸芯片，所述半导体裸芯片之间通过引线接合电连接。
（7）如（1）～（6）的任意一项所述的半导体模块，其特征在于：所述半导体裸芯片隔着隔片搭载于所述半导体封装上。
（8）如（1）～（7）的任意一项所述的半导体模块，其特征在于：在所述半导体裸芯片上搭载有散热板。
（9）如（1）～（8）的任意一项所述的半导体模块，其特征在于：所述半导体封装在第1封装基板上搭载有多个半导体裸芯片。
根据本发明，将第1半导体封装搭载于封装基板，所以能够抑制由以后的组装工序中的热履历引起的第1半导体封装基板的翘曲变动。
因此，能够解决由于第1半导体封装的翘曲而产生引线短路、树脂封止时的未填充等问题。裂纹，能够设为无视第1半导体封装的翘曲变动的封装截面尺寸，也能够使封装的厚度变薄。
附图说明
图1是表示本发明的实施方式1的半导体模块的截面构造的图。
图2是表示作为构成本发明的半导体模块的部件的第1半导体封装的截面构造的图。
图3是示意性表示本发明中的第1半导体封装的第1封装基板的外观的图。
图4是表示本发明的实施方式2的半导体模块的截面构造的图。
图5是表示本发明的实施方式3的半导体模块的截面构造的图。
图6是表示本发明的实施方式4的半导体模块的截面构造的图。
图7是表示本发明的实施方式5的半导体模块的截面构造的图。
图8是表示本发明的实施方式6的半导体模块的截面构造的图。
图9是表示本发明的实施方式7的半导体模块的截面构造的图。
图10是表示本发明的实施方式8的半导体模块的截面构造的图。
图11是表示本发明的实施方式9的半导体模块的截面构造的图。
图12是表示以往的半导体模块的截面构造的图。
附图标记说明
1、1a、1b：半导体裸芯片
2：第1半导体裸芯片
3：第2半导体裸芯片
4：第1封装基板
5、5a：树脂
6：第1半导体封装
7：电极焊盘（安装用电极）
8：电极焊盘（试验用电极）
9、9a、9b、9c：引线
11：软钎料
12：第2封装基板
13：软钎料球
14：粘接剂
15：隔片
16：散热板
10、20、30、40、50、60、70、80：半导体模块
具体实施方式
以下，对于本发明的具体实施方式进行说明。另外，在以下的记载中基于附图对实施方式进行说明，但这些附图是为了图解而提供的，本发明并不限定于这些附图。
本发明所涉及的半导体模块是将封装基板、搭载于该封装基板的第1半导体封装、和层叠于该第1半导体封装的半导体裸芯片进行树脂封止（封止）而封装化的半导体模块。
以下基于图1、2对本发明的半导体模块的基本结构进行说明。
以下，有时将第1半导体封装的封装基板称为第1封装基板，将搭载该第1半导体封装的封装基板称为第2封装基板。另外，有时将具备第1半导体封装的本发明的半导体模块称为第2半导体封装。
（实施方式1）
图1是表示本发明的实施方式1的半导体模块10的图。
本发明所涉及的半导体模块10是通过树脂5将封装基板（以下，也称为第2封装基板）12、搭载于该第2封装基板12的第1半导体封装6和层叠于该第1半导体封装6的半导体裸芯片2树脂封止而成的。
基于图2对第1半导体封装6的详细进行说明。
第1半导体封装6是在第1封装基板4上搭载半导体裸芯片1、通过引线接合用引线（wire）9c将半导体裸芯片1与第1封装基板4电连接、然后通过树脂5a进行树脂封止而成的。
半导体裸芯片1使用用晶片级测试为合格品的芯片。另外，第1半导体封装6使用在封装的状态下测试为合格品的封装。另外，并不限定于一定进行测试。
图3是表示第1封装基板4的外观的图。第1封装基板4具备安装用电极7和试验用电极8。
在本实施方式中，如图1所示，首先，在第2封装基板12上搭载第1半导体封装6。该搭载通过将第1半导体封装6的第1封装基板4的电极焊盘（electrode pad）7、8用软钎料接合于封装基板12的电极而进行。接下来，在该第1半导体封装6的树脂面上通过粘接剂14接合半导体裸芯片2从而搭载，通过引线9将半导体裸芯片2与第2封装基板12电连接，然后通过树脂5将第1半导体封装6以及半导体裸芯片2封止，由此得到第2半导体封装（半导体模块）。
在图12（b）所示的以往例中，在半导体裸芯片2与第1半导体封装6的间隙配置有引线，所以存在引线由于第1半导体封装6的翘曲而变形而产生引线短路、或者所述间隙窄而树脂不能充分进入间隙的问题，但在本实施方式中，第1半导体封装6经由电极7、8通过软钎料接合于封装基板12，所以能够校正第1半导体封装6的翘曲、另外防止翘曲的产生。
另外，半导体裸芯片2位于最上层，所以引线接合作业容易，也没有引线短路和/或形成树脂未填充部分的问题。
另外，在以往例中，第1封装基板4的试验用电极8仅为了试验而使用，但如本实施方式中所示，将第1封装基板和第2封装基板在电极之间软钎料接合的情况下，通过适当涉及第2封装基板的布线，还能够有将试验用电极8作为安装用电极而利用的优点。
（实施方式2）
图4是表示本发明的实施方式2的半导体模块20的图。
在本实施方式中与实施方式1同样，通过软钎料将第1封装基板4的电极焊盘7、8接合于封装基板12的电极，由此在第2封装基板12搭载第1半导体封装6。在第1半导体封装6的树脂面上搭载第1半导体裸芯片2，进而在该第1半导体裸芯片2之上搭载第2半导体裸芯片3。第1半导体裸芯片2和第2半导体裸芯片3通过软钎料等金属接合而直接连接、成为所谓的利用了微细间距连接的COC（Chip On Chip）连接构造。
（实施方式3）
图5是表示本发明的实施方式3的半导体模块30的图。
在本实施方式中，与实施方式1同样，通过软钎料将第1半导体封装6的第1封装基板4的电极焊盘7、8接合于第2封装基板12的电极，由此在第2封装基板12搭载第1半导体封装6。另外，在第1半导体封装6的树脂面上通过粘接剂搭载第1半导体裸芯片2，进而在其上通过粘接剂搭载第2半导体裸芯片3。第1半导体裸芯片2和第2半导体裸芯片3通过引线9a电连接，第1半导体裸芯片2和第2封装基板12通过引线9电连接。另外，有时第2半导体裸芯片3直接通过引线9a与第2封装基板12电连接。
图6是表示本发明的实施方式4的半导体模块40的图。
在本实施方式中，使第1半导体封装6的树脂面侧成为第2封装基板侧，通过粘接剂将第1半导体封装6与第2封装基板12接合。这样，通过使第1半导体封装6的树脂面侧成为第2封装基板侧而将第1半导体封装6与第2封装基板12接合，也能够校正第1半导体封装6的翘曲、另外防止翘曲的产生。
在该第1半导体封装6的与树脂面相反一侧的面上，通过粘接剂14接合搭载有半导体裸芯片2。该第1半导体封装通过引线9b电连接于第2封装基板12，半导体裸芯片2通过9电连接于第2封装基板12。
图7是表示本发明的实施方式5的半导体模块50的图。
在本实施方式中，使第1半导体封装6的树脂面侧成为第2封装基板侧，通过粘接剂将第1半导体封装6与第2封装基板12接合。在第1半导体封装6的与树脂面相反一侧的面上搭载有第1半导体裸芯片2。进而，在该第1半导体裸芯片2上，搭载第2半导体裸芯片3。第1半导体裸芯片2与第2半导体裸芯片3通过软钎料11等金属接合而直接电连接。
另外，第1半导体封装6通过引线9b电连接于第2封装基板12，第1半导体裸芯片2通过引线9电连接于第2封装基板12。
图8是表示本发明的实施方式6的半导体模块60的图。
在本实施方式中，使第1半导体封装6的树脂面侧成为第2封装基板侧，通过粘接剂将第1半导体封装6与第2封装基板12接合。在第1半导体封装的与树脂面相反一侧的面上通过粘接剂接合搭载有第1半导体裸芯片2，在该第1半导体裸芯片2上通过粘接剂接合搭载有第2半导体裸芯片3。第1半导体裸芯片2与第2半导体裸芯片3通过引线9a电连接，第1半导体裸芯片2与第2封装基板12通过引线9电连接，第1半导体封装6与第2封装基板12通过引线9b电连接。另外，有时第2半导体裸芯片3与第2封装基板12直接通过引线9a电连接。
图9是表示本发明的实施方式7的半导体模块70的图。
在本实施方式中，在第1半导体封装6上搭载隔片（spacer）15，在其上搭载半导体裸芯片2。另外，在图9中没有图示第1半导体封装6与第2封装基板12的电连接构造以及半导体裸芯片2与第2封装基板12的电连接构造。第1半导体封装6与第2封装基板12可以在第1半导体封装6的电极侧接合，也可以在第1半导体封装6的树脂面侧接合。
通过设置隔片15，即使在半导体裸芯片2与第1半导体封装6的大小没有差异的情况下也能够进行第1半导体封装6与封装基板12的引线接合。
图10是表示本发明的实施方式8的半导体模块80的图。
在本实施方式中，在第1半导体封装6上搭载有半导体裸芯片2，在该半导体裸芯片2上搭载有硅板或者Cu板等散热板16。
在图示例中将散热板16搭载于半导体裸芯片上，但设置散热板16的位置并不限定于半导体裸芯片2上。
另外，在图10中没有图示第1半导体封装6与封装基板12的电连接构造以及半导体裸芯片2与封装基板12的电连接构造。
第1半导体封装6与第2封装基板12可以在第1半导体封装6的电极侧接合，也可以在第1半导体封装6的树脂面侧接合。
通过设置这样的散热板16，能够提高半导体模块的散热特性。
图11是表示本发明的实施方式9的半导体模块90的图。
在本实施方式中在第2封装基板12之中安装半导体裸芯片2，在该第2封装基板12接合第1半导体封装6，之后通过树脂5封止而做成半导体模块90。
根据该实施方式，能够在第2封装基板12中吸收半导体裸芯片2的厚度，所以能够使半导体模块90厚度变薄。

Claims (9)

1.一种半导体模块，具有：在第1封装基板搭载半导体裸芯片并树脂封止而成的半导体封装、半导体裸芯片和第2封装基板，其特征在于：在所述第2封装基板搭载所述半导体封装，在所述半导体封装上搭载所述半导体裸芯片。
2.如权利要求1所述的半导体模块，其特征在于：所述半导体封装在与树脂面相反一侧的面经由电极焊盘通过软钎料与第2封装基板电连接。
3.如权利要求1所述的半导体模块，其特征在于：所述半导体封装在树脂面与第2封装基板接合，通过引线接合与第2封装基板电连接。
4.如权利要求1～3的任意一项所述的半导体模块，其特征在于：搭载于所述半导体封装上的半导体裸芯片通过引线接合与第2封装基板电连接。
5.如权利要求1～4的任意一项所述的半导体模块，其特征在于：在所述半导体封装上层叠搭载2个以上所述半导体裸芯片，所述半导体裸芯片之间的电连接设为COC构造。
6.如权利要求1～4的任意一项所述的半导体模块，其特征在于：在所述半导体封装上层叠搭载2个以上所述半导体裸芯片，所述半导体裸芯片之间通过引线接合电连接。
7.如权利要求1～6的任意一项所述的半导体模块，其特征在于：所述半导体裸芯片隔着隔片搭载于所述半导体封装上。
8.如权利要求1～7的任意一项所述的半导体模块，其特征在于：在所述半导体裸芯片上搭载有散热板。
9.如权利要求1～8的任意一项所述的半导体模块，其特征在于：所述半导体封装在第1封装基板上搭载有多个半导体裸芯片。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107424980A (zh) * 2016-04-28 2017-12-01 株式会社吉帝伟士 半导体封装件及半导体封装件的制造方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10847488B2 (en) 2015-11-02 2020-11-24 Mediatek Inc. Semiconductor package having multi-tier bonding wires and components directly mounted on the multi-tier bonding wires
US10541153B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10804115B2 (en) * 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541209B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
EP3821466B1 (en) 2018-10-11 2023-12-13 Yangtze Memory Technologies Co., Ltd. Vertical memory devices
CN109564905A (zh) * 2018-10-30 2019-04-02 长江存储科技有限责任公司 Ic封装
EP3903346B1 (en) 2019-02-18 2024-04-03 Yangtze Memory Technologies Co., Ltd. Novel through silicon contact structure and method of forming the same
JP2021015922A (ja) * 2019-07-16 2021-02-12 キオクシア株式会社 半導体装置およびその製造方法
US11355450B2 (en) * 2019-08-01 2022-06-07 Mediatek Inc. Semiconductor package with EMI shielding structure
US11456231B2 (en) * 2021-01-18 2022-09-27 Fortinet, Inc. Heatsink arrangement for integrated circuit assembly and method for assembling thereof

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6946323B1 (en) * 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
US20060027841A1 (en) * 2004-08-04 2006-02-09 Sharp Kabushiki Kaisha Stack type semiconductor apparatus package and manufacturing method thereof
TW200616108A (en) * 2004-11-08 2006-05-16 Siliconware Precision Industries Co Ltd Semiconductor device having flip chip package
CN1819187A (zh) * 2005-02-07 2006-08-16 株式会社瑞萨科技 半导体装置及胶囊型半导体封装
US20060249851A1 (en) * 2005-05-05 2006-11-09 Stats Chippac Ltd. Multiple Chip Package Module Including Die Stacked Over Encapsulated Package
JP2008192714A (ja) * 2007-02-02 2008-08-21 Toshiba Corp 半導体パッケージ
US20120001315A1 (en) * 2010-06-30 2012-01-05 Hitachi, Ltd. Semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002040095A (ja) 2000-07-26 2002-02-06 Nec Corp 半導体装置及びその実装方法
US7061088B2 (en) 2002-10-08 2006-06-13 Chippac, Inc. Semiconductor stacked multi-package module having inverted second package
US7843058B2 (en) * 2007-10-30 2010-11-30 Taiwan Semiconductor Manufacturing Company, Ltd. Flip chip packages with spacers separating heat sinks and substrates
JP4303772B2 (ja) 2008-06-17 2009-07-29 株式会社Ｇｅｎｕｓｉｏｎ 半導体パッケージ

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6946323B1 (en) * 2001-11-02 2005-09-20 Amkor Technology, Inc. Semiconductor package having one or more die stacked on a prepackaged device and method therefor
US20060027841A1 (en) * 2004-08-04 2006-02-09 Sharp Kabushiki Kaisha Stack type semiconductor apparatus package and manufacturing method thereof
TW200616108A (en) * 2004-11-08 2006-05-16 Siliconware Precision Industries Co Ltd Semiconductor device having flip chip package
CN1819187A (zh) * 2005-02-07 2006-08-16 株式会社瑞萨科技 半导体装置及胶囊型半导体封装
US20060249851A1 (en) * 2005-05-05 2006-11-09 Stats Chippac Ltd. Multiple Chip Package Module Including Die Stacked Over Encapsulated Package
JP2008192714A (ja) * 2007-02-02 2008-08-21 Toshiba Corp 半導体パッケージ
US20120001315A1 (en) * 2010-06-30 2012-01-05 Hitachi, Ltd. Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107424980A (zh) * 2016-04-28 2017-12-01 株式会社吉帝伟士 半导体封装件及半导体封装件的制造方法

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