TW201349443A - 半導體模組 - Google Patents

半導體模組 Download PDF

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Publication number
TW201349443A
TW201349443A TW102110840A TW102110840A TW201349443A TW 201349443 A TW201349443 A TW 201349443A TW 102110840 A TW102110840 A TW 102110840A TW 102110840 A TW102110840 A TW 102110840A TW 201349443 A TW201349443 A TW 201349443A
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Taiwan
Prior art keywords
semiconductor
package
package substrate
bare chip
semiconductor bare
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Application number
TW102110840A
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English (en)
Inventor
Akihiro Umeki
Yoichi Hiruta
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J Devices Corp
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Application filed by J Devices Corp filed Critical J Devices Corp
Publication of TW201349443A publication Critical patent/TW201349443A/zh

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Abstract

本發明之目的在於解決在包含封裝基板、第一半導體封裝件、及半導體裸晶片的半導體模組中，由於第一半導體封裝件的翹曲所引起之銲線短路的發生、及樹脂封裝時的未充填等之問題。本發明之半導體模組10，係具有在第一封裝基板上搭載半導體裸晶片並加以樹脂封裝而成的半導體封裝件6、半導體裸晶片2、及第二封裝基板12的半導體模組10，其中前述半導體封裝件6搭載於前述第二封裝基板12上，且前述半導體裸晶片2搭載於前述半導體封裝件6上。

Description

半導體模組
本發明係關於堆疊有半導體裸晶片(bare chip)及半導體封裝件(package)之半導體模組。
伴隨著近年來之電子機器的高機能化及輕薄短小化之要求，電子零件也跟著往高密度積體化，進而往電子零件的高密度安裝化發展，使用於此等電子機器之半導體裝置比以往增加且往小型化發展。
使半導體裝置小型化之方法中，有一種係對於一個半導體裸晶片進行微細加工而將必需的所有機能集積在一個晶片中，藉此來謀求安裝面積的縮小化、及消耗電力的減低化之SOC(System-On-a-Chip：系統單晶片)技術。然而，此方法因為製造成本會隨著電路的微細化而上升，以及擴散製程非常複雜，所以製造工期會變長，且無法提高製造良率。
在取代SOC技術的方法方面，有一種SIP(System In Package：系統級封裝)技術受到矚目。根據SIP，分別以最佳化的製造條件來製造不同機能的複數個半導體裸晶片，並將其予以封裝件化，且在封裝件上適切地配線，藉此而可穩定地生產具有更高度機能的積體電路。
但是，在如上述之將複數個半導體裸晶片封裝在一個封裝件內之SIP中，基於良率的觀點，而有各半導體裸晶片要是預先檢查完畢且確認為良品的半導體裸晶片(良品晶粒)(KGD：Known Good Die)之要求。就獲得KGD而言，係在半導體晶圓的狀態下、或是藉由切晶(dicing)而將半導體晶圓切為個體化分離的半導體裸晶片的狀態下，以探針(probe)抵觸設在該等半導體裸晶片的表面之電極而進行探針檢查，然後根據檢查結果來挑選半導體裸晶片，再針對經挑選為良品之半導體裸晶片進行預燒(burn in)檢查等之篩選(screening)檢查而獲得。
然而，直接對半導體裸晶片進行探針檢查，會有使個體化半導體裸晶片或半導體晶圓破裂，亦使檢查中所使用的插座(socket)及探針(probe)、測試機(tester)等並不能夠簡便地加以操作的之問題。
因此，為了解決前述課題，有人提出一種在用樹脂封裝半導體裸晶片而成之樹脂封裝件(package)的表面，設有與半導體裸晶片之電極連接的電極及與試驗用機器連接的試驗用電極的半導體裝置(專利文獻1)。該半導體裝置係在安裝至安裝基板上之前就已封裝件化，所以具有不會發生晶片破裂等問題，且可使用較便宜的檢查插座來進行檢查之優點。
此外，有人提出使用上述之封裝件化的半導體裝置來構成SIP化的半導體模組(專利文獻2)。
該半導體模組係如第12圖所示。
第12圖(a)顯示將半導體裸晶片1a安裝在中介片(interposer)4上，然後將間隔件(spacer)15堆疊在半導體裸晶片1a之上，再在 上面堆疊半導體裸晶片1b，並藉由打線接合(wire bonding)而配設銲線(wire)9之後，藉由樹脂5加以樹脂封裝而得到的第一半導體封裝件6。
第12圖(b)顯示將半導體裸晶片2、間隔件15及前述第一半導體封裝件6依序堆疊在封裝基板12上予以樹脂封裝而SIP化的半導體模組10。
就圖示的例子而言，第一半導體封裝件6的大小與半導體裸晶片2大致相同，所以將插入於第一半導體封裝件6與半導體裸晶片2之間之間隔件15設置成不會蓋住半導體裸晶片2的電極銲墊(pad)。
另外，在專利文獻3中記載有：在封裝基板上搭載半導體裸晶片並樹脂封裝而構成第一半導體封裝件後，再在其上搭載第二半導體封裝件而形成半導體模組。
不過，如前述的半導體模組不僅因為要經過複雜的步驟而有成本上升及良率降低之問題，而且也不適於封裝件厚度之薄型化。此外，以堆疊於上述的第一半導體封裝件上之經過測試的半導體封裝件所構成之半導體模組會有測試過的第一半導體封裝件會因為組立過程中所受到的熱而翹曲，以致於與下段的封裝件的銲線接觸，而發生銲線短路(wire short)，或者因為下端的封裝件比測試過的封裝件小而外伸(overhang)，以致於發生樹脂封裝時的未充填等之技術性的課題。
[先前技術文獻] (專利文獻)
專利文獻1：日本特開2002-40095號公報
專利文獻2：日本特許第4303772號公報
專利文獻3：美國專利第7057269號說明書
本發明之目的在於解決在包含封裝基板、第一半導體封裝件、半導體裸晶片的半導體模組中，由於第一半導體封裝件的翹曲所引起之銲線短路的發生、及樹脂封裝時的未充填等之問題。
本發明之諸發明人發現：在包含封裝基板、第一半導體封裝件、及半導體裸晶片的半導體模組中，藉由搭載在封裝基板上搭載有半導體裸晶片並加以樹脂封裝而成的第一半導體封裝件，且在該第一半導體封裝件上搭載半導體裸晶片，而樹脂封裝第一半導體封裝件及前述半導體裸晶片，即可解決前述的問題，因而完成本發明。亦即，本發明係如下述所記載者。
(1)具有在第一封裝基板上搭載半導體裸晶片並加以樹脂封裝而成的半導體封裝件、半導體裸晶片、及第二封裝基板的半導體模組，其中前述半導體封裝件搭載於前述第二封裝基板上，前述半導體裸晶片搭載於前述半導體封裝件上。
(2)如前述(1)所記載之半導體模組，其中，前述半導體封裝件係在與樹脂面相反側的面透過電極銲墊(pad)而藉由焊錫與前述第二封裝基板電性連接。
(3)如前述(1)所記載之半導體模組，其中，前述半導體封裝件係以樹脂面與第二封裝基板接合，且藉由打線接合(wire bonding)而與 第二封裝基板電性連接。
(4)如前述(1)至(3)中任一項所記載之半導體模組，其中，搭載於前述半導體封裝件上之半導體裸晶片係藉由打線接合(wire bonding)而與第二封裝基板電性連接。
(5)如前述(1)至(4)中任一項所記載之半導體模組，其中，前述半導體封裝件上係搭載有相堆疊之兩個以上的前述半導體裸晶片，且前述半導體裸晶片間的電性連接係採取COC(Chip on Chip：晶片堆疊)構造。
(6)如前述(1)至(4)中任一項所記載之半導體模組，其中，前述半導體封裝件上係搭載有相堆疊之兩個以上的前述半導體裸晶片，且前述半導體裸晶片間係藉由打線接合而電性連接。
(7)如前述(1)至(6)中任一項所記載之半導體模組，其中，前述半導體裸晶片係隔著間隔件(spacer)而搭載於前述半導體封裝件上。
(8)如前述(1)至(7)中任一項所記載之半導體模組，其中，前述半導體裸晶片之上搭載有散熱板。
(9)如前述(1)至(8)中任一項所記載之半導體模組，其中，前述半導體封裝件係在第一封裝基板上搭載有複數個半導體裸晶片。
根據本發明，因將第一半導體封裝件搭載於封裝基板上，所以可抑制由於在接下來的組立步驟中所受到的熱而導致之第一半導體封裝件的翹曲。
因此，可解決由於第一半導體封裝件的翹曲所引起之銲線短路的發生、及樹脂封裝時的未充填等之問題。以及，可做成不用顧慮第一半導體封裝件的翹曲之封裝件剖面尺寸，亦可實現封裝 件之薄型化。
1、1a、1b‧‧‧半導體裸晶片
2‧‧‧第一半導體裸晶片
3‧‧‧第二半導體裸晶片
4‧‧‧第一封裝基板
5、5a‧‧‧樹脂
6‧‧‧第一半導體封裝件
7‧‧‧電極銲墊(安裝用電極)
8‧‧‧電極銲墊(試驗用電極)
9、9a、9b、9c‧‧‧銲線
10、20、30、40、50、60、70、80、90‧‧‧半導體模組
11‧‧‧焊錫
12‧‧‧第二封裝基板
13‧‧‧錫球
14‧‧‧接著劑
15‧‧‧間隔件
16‧‧‧散熱板
第1圖係顯示本發明的實施形態1之半導體模組的剖面構造之圖。
第2圖係顯示本發明之屬於構成半導體模組之元件的第一半導體封裝件的剖面構造之圖。
第3圖係示意性地顯示本發明之第一半導體封裝件的第一封裝基板的外觀之圖。
第4圖係顯示本發明的實施形態2之半導體模組的剖面構造之圖。
第5圖係顯示本發明的實施形態3之半導體模組的剖面構造之圖。
第6圖係顯示本發明的實施形態4之半導體模組的剖面構造之圖。
第7圖係顯示本發明的實施形態5之半導體模組的剖面構造之圖。
第8圖係顯示本發明的實施形態6之半導體模組的剖面構造之圖。
第9圖係顯示本發明的實施形態7之半導體模組的剖面構造之圖。
第10圖係顯示本發明的實施形態8之半導體模組的剖面構造之圖。
第11圖係顯示本發明的實施形態9之半導體模組的剖面構造 之圖。
第12圖係顯示習知的半導體模組的剖面構造之圖。
以下，針對本發明之實施形態進行說明。以下將根據圖式來說明本發明之實施形態，但該等圖式係為了圖解之用途而提供者，本發明並不受該等圖式所限定。
本發明之半導體模組，係將封裝基板、搭載於該封裝基板上之第一半導體封裝件、及堆疊於該第一半導體封裝件上之半導體裸晶片予以樹脂封裝而封裝件化者。
以下根據第1、2圖來說明本發明之半導體模組的基本構成。
以下，會有將第一半導體封裝件的封裝基板稱為第一封裝基板，將搭載該第一半導體封裝件之封裝基板稱為第二封裝基板。以及，會有將具備有第一半導體封裝件之本發明的半導體模組稱為第二半導體封裝件。
(實施形態1)
第1圖係顯示本發明的實施形態1之半導體模組10之圖。
本發明之半導體模組10，係藉由樹脂5將封裝基板(以下稱為第二封裝基板)12、搭載於該封裝基板12上之第一半導體封裝件6、及堆疊於該第一半導體封裝件6上之半導體裸晶片2予以樹脂封裝者。
根據第2圖來說明第一半導體封裝件6的詳細構成。
第一半導體封裝件6係在第一封裝基板4上搭載半導體裸晶片1，然後藉由打線接合(wire bonding)以銲線9c來電性連接半導體裸晶片1與第一封裝基板4後，以樹脂5予以樹脂封裝者。
半導體裸晶片1係使用經晶圓級測試(wafer level test)確認為良品之晶片。第一半導體封裝件6則是使用以封裝件的狀態接受測試而經確認為良品者。但並不限定非要經過測試的不可。
第3圖係顯示第一封裝基板4的外觀之圖。第一封裝基板4具備有安裝用電極7及試驗用電極8。
本實施形態係如第1圖所示，首先在第二封裝基板12上搭載第一半導體封裝件6。此搭載係藉由利用焊錫將第一半導體封裝件6的第一封裝基板4的電極銲墊7、8接合至封裝基板12的電極而進行。接著，藉由接著劑14進行接合而使半導體裸晶片2搭載在該第一半導體封裝件6的樹脂面上，然後藉由銲線9而使半導體裸晶片2與第二封裝基板12電性連接後，以樹脂5將第一半導體封裝件6及半導體裸晶片2予以封裝而得到第二半導體封裝件(半導體模組)。
在第12圖(b)所示之習知的例子中，因為在半導體裸晶片2與第一半導體封裝件6的間隙間配置銲線，所以會有因為第一半導體封裝件6之翹曲使得銲線變形而發生銲線短路、或者因為前述間隙太狹窄使得樹脂無法充分填充進入之問題，而相對的，在本實施形態中，因為第一半導體封裝件6係透過電極7、8而以焊錫接合至封裝基板12，所以可矯正第一半導體封裝件6之翹曲，以及防止翹曲之發生。
再者，因為半導體裸晶片2在最上段，所以打線接合作業很容易，也不會有銲線短路及形成樹脂未充填部分之問題。
又，在習知的例子中，第一封裝基板4的試驗用電極8係只使用於試驗，而相對於此，如本實施形態，利用焊錫來進行第一 封裝基板與第二封裝基板的電極間之接合時，還具有可藉由適宜地設計第二封裝基板的配線來將試驗用電極8利用作為安裝用電極之優點。
(實施形態2)
第4圖係顯示本發明之實施形態2的半導體模組20之圖。
本實施形態中與實施形態1同樣地，利用焊錫將第一封裝基板4的電極銲墊7、8接合至封裝基板12的電極而使第一半導體封裝件6搭載至封裝基板12上。然後在第一半導體封裝件6的樹脂面上搭載第一半導體裸晶片2，再在該第一半導體裸晶片2之上搭載第二半導體裸晶片3。第一半導體裸晶片2與第二半導體裸晶片3之間係藉由焊錫等之金屬接合而直接連接，而形成藉由所謂的微細間距(fine pitch)連接之COC(Chip On Chip：晶片堆疊)連接構造。
(實施形態3)
第5圖係顯示本發明之實施形態3的半導體模組30之圖。
在本實施形態中，與實施形態1同樣地，利用焊錫將第一半導體封裝件6的第一封裝基板4的電極銲墊7、8接合至第二封裝基板12的電極而使第一半導體封裝件6搭載至第二封裝基板12上。以及，利用接著劑而使第一半導體裸晶片2搭載在第一半導體封裝件6的樹脂面上，再利用接著劑而使第二半導體裸晶片3搭載在第一半導體裸晶片2之上。第一半導體裸晶片2與第二半導體裸晶片3係藉由銲線9a而電性連接，第一半導體裸晶片2與第二封裝基板12係藉由銲線9而電性連接。另外，第二半導體裸晶片3也可藉由銲線9a而直接與第二封裝基板12電性連接。
第6圖係顯示本發明之實施形態4的半導體模組40之圖。
在本實施形態中，使第一半導體封裝件6的樹脂面側位於第二封裝基板側，而利用接著劑來接合第一半導體封裝件6與第二封裝基板12。如此，使第一半導體封裝件6的樹脂面側位於第二封裝基板側然後接合第一半導體封裝件6與第二封裝基板12，一樣可矯正第一半導體封裝件6之翹曲，以及防止翹曲之發生。
接著，藉由接著劑14進行接合而使半導體裸晶片2搭載在該第一半導體封裝件6之與樹脂面相反側的面上。該第一半導體封裝件係藉由銲線9b而與第二封裝基板12電性連接，半導體裸晶片2係藉由銲線9而與第二封裝基板12電性連接。
第7圖係顯示本發明之實施形態5的半導體模組50之圖。
在本實施形態中，使第一半導體封裝件6的樹脂面側位於第二封裝基板側，而利用接著劑來接合第一半導體封裝件6與第二封裝基板12。接著，使第一半導體裸晶片2搭載在該第一半導體封裝件6之與樹脂面相反側的面上。然後，再使第二半導體裸晶片3搭載在該第一半導體裸晶片2上。第一半導體裸晶片2與第二半導體裸晶片3係藉由焊錫11等之金屬接合而直接電性連接。
第一半導體封裝件6係藉由銲線9b而與第二封裝基板12電性連接，第一半導體裸晶片2係藉由銲線9而與第二封裝基板12電性連接。
第8圖係顯示本發明之實施形態6的半導體模組60之圖。
在本實施形態中，使第一半導體封裝件6的樹脂面側位於第二封裝基板側，而利用接著劑來接合第一半導體封裝件6與第二封裝基板12。接著，利用接著劑進行接合而使第一半導體裸晶片2搭載在第一半導體封裝件之與樹脂面相反側的面上，利用接著劑進行接合而使第二半導體裸晶片3搭載在該第一半導體裸晶片2上。第一半導體裸晶片2與第二半導體裸晶片3係藉由銲線9a而電性連接，第一半導體裸晶片2與第二封裝基板12係藉由銲線9而電性連接，第一半導體封裝件6與第二封裝基板12係藉由銲線9b而電性連接。另外，第二半導體裸晶片3也可藉由銲線9a而直接與第二封裝基板12電性連接。
第9圖係顯示本發明之實施形態7的半導體模組70之圖。
在本實施形態中，在第一半導體封裝件6之上搭載間隔件(spacer)15，在間隔件15之上搭載半導體裸晶片2。第9圖中並未圖示第一半導體封裝件6與第二封裝基板12的電性連接構造以及半導體裸晶片2與第二封裝基板12的電性連接構造。第一半導體封裝件6與第二封裝基板12可在第一半導體封裝件6的電極側接合，亦可在第一半導體封裝件6的樹脂面側接合。
設置間隔件15，就可在即使半導體裸晶片2與第一半導體封裝件6的大小沒有什麼差異之情況也能夠進行第一半導體封裝件6與第二封裝基板12之打線接合。
第10圖係顯示本發明之實施形態8的半導體模組80之圖。
在本實施形態中，在第一半導體封裝件6之上搭載半導體裸 晶片2，在該半導體裸晶片2之上搭載矽板或銅板等之散熱板16。
圖示的例子中雖然是將散熱板16搭載在半導體裸晶片之上，但散熱板16的設置位置並不限於半導體裸晶片2之上。
又，第10圖中也未圖示第一半導體封裝件6與第二封裝基板12的電性連接構造以及半導體裸晶片2與第二封裝基板12的電性連接構造。
第一半導體封裝件6與第二封裝基板12可在第一半導體封裝件6的電極側接合，亦可在第一半導體封裝件6的樹脂面側接合。
設置如此之散熱板16就可提高半導體模組的散熱特性。
第11圖係顯示本發明之實施形態9的半導體模組90之圖。
本實施形態係將半導體裸晶片2安裝在第二封裝基板12之中，然後在將第一半導體封裝件6接合至該第二封裝基板12之後利用樹脂5加以封裝起來而形成為半導體模組90。
根據本實施形態，可將半導體裸晶片2的厚度吸收在第二封裝基板12之中，所以可將半導體模組90予以薄型化。
2‧‧‧第一半導體裸晶片
5‧‧‧樹脂
6‧‧‧第一半導體封裝件
9‧‧‧銲線
10‧‧‧半導體模組
11‧‧‧焊錫
12‧‧‧第二封裝基板
13‧‧‧錫球
14‧‧‧接著劑

Claims (9)

  1. 一種半導體模組，係具有：在第一封裝基板上搭載半導體裸晶片並加以樹脂封裝而成的半導體封裝件、半導體裸晶片、及第二封裝基板的半導體模組，其中前述半導體封裝件係搭載於前述第二封裝基板上，且前述半導體裸晶片係搭載於前述半導體封裝件上。
  2. 如申請專利範圍第1項所述之半導體模組，其中，前述半導體封裝件係在與樹脂面相反側的面透過電極銲墊而藉由焊錫與前述第二封裝基板電性連接。
  3. 如申請專利範圍第1項所述之半導體模組，其中，前述半導體封裝件係以樹脂面與第二封裝基板接合，且藉由打線接合而與第二封裝基板電性連接。
  4. 如申請專利範圍第1至3項中任一項所述之半導體模組，其中，搭載於前述半導體封裝件上之半導體裸晶片係藉由打線接合而與第二封裝基板電性連接。
  5. 如申請專利範圍第1至4項中任一項所述之半導體模組，其中，前述半導體封裝件上係搭載有相堆疊之兩個以上的前述半導體裸晶片，且前述半導體裸晶片間的電性連接係採取晶片堆疊(COC)構造。
  6. 如申請專利範圍第1至4項中任一項所述之半導體模組，其中，前述半導體封裝件上係搭載有相堆疊之兩個以上的前述半導體裸晶片，且前述半導體裸晶片間係藉由打線接合而電性連接。
  7. 如申請專利範圍第1至6項中任一項所述之半導體模組，其中， 前述半導體裸晶片係隔著間隔件而搭載於前述半導體封裝件上。
  8. 如申請專利範圍第1至7項中任一項所述之半導體模組，其中，前述半導體裸晶片之上搭載有散熱板。
  9. 如申請專利範圍第1至8項中任一項所述之半導體模組，其中，前述半導體封裝件係在第一封裝基板上搭載有複數個半導體裸晶片。
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