JP6104928B2 - 層間多結晶シリコン誘電体キャップおよびその形成方法 - Google Patents

層間多結晶シリコン誘電体キャップおよびその形成方法 Download PDF

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Publication number
JP6104928B2
JP6104928B2 JP2014541176A JP2014541176A JP6104928B2 JP 6104928 B2 JP6104928 B2 JP 6104928B2 JP 2014541176 A JP2014541176 A JP 2014541176A JP 2014541176 A JP2014541176 A JP 2014541176A JP 6104928 B2 JP6104928 B2 JP 6104928B2
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containing layer
nitrogen
floating gate
oxygen
layer
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Japanese (ja)
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JP2014533437A (ja
JP2014533437A5 (https=
Inventor
マシュー エス． ロジャーズ，
マシュー エス． ロジャーズ，
クラウス シューグラフ，
クラウス シューグラフ，
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Applied Materials Inc
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Applied Materials Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0451—Apparatus for manufacturing or treating in a plurality of work-stations
    • H10P72/0452—Apparatus for manufacturing or treating in a plurality of work-stations characterised by the layout of the process chambers
    • H10P72/0454—Apparatus for manufacturing or treating in a plurality of work-stations characterised by the layout of the process chambers surrounding a central transfer chamber

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Formation Of Insulating Films (AREA)
JP2014541176A 2011-11-11 2012-11-07 層間多結晶シリコン誘電体キャップおよびその形成方法 Active JP6104928B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/294,608 2011-11-11
US13/294,608 US8994089B2 (en) 2011-11-11 2011-11-11 Interlayer polysilicon dielectric cap and method of forming thereof
PCT/US2012/063841 WO2013070685A1 (en) 2011-11-11 2012-11-07 Interlayer polysilicon dielectric cap and method of forming thereof

Publications (3)

Publication Number Publication Date
JP2014533437A JP2014533437A (ja) 2014-12-11
JP2014533437A5 JP2014533437A5 (https=) 2015-12-24
JP6104928B2 true JP6104928B2 (ja) 2017-03-29

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JP2014541176A Active JP6104928B2 (ja) 2011-11-11 2012-11-07 層間多結晶シリコン誘電体キャップおよびその形成方法

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Country Link
US (1) US8994089B2 (https=)
JP (1) JP6104928B2 (https=)
KR (1) KR102092760B1 (https=)
CN (1) CN103930992B (https=)
WO (1) WO2013070685A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8981466B2 (en) * 2013-03-11 2015-03-17 International Business Machines Corporation Multilayer dielectric structures for semiconductor nano-devices
US10192747B2 (en) 2014-01-07 2019-01-29 Cypress Semiconductor Corporation Multi-layer inter-gate dielectric structure and method of manufacturing thereof
US20150194537A1 (en) * 2014-01-07 2015-07-09 Spansion Llc Multi-layer inter-gate dielectric structure
US20160343722A1 (en) * 2015-05-21 2016-11-24 Sandisk Technologies Inc. Nonvolatile storage with gap in inter-gate dielectric
US11588031B2 (en) * 2019-12-30 2023-02-21 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure for memory device and method for forming the same
US11587796B2 (en) * 2020-01-23 2023-02-21 Applied Materials, Inc. 3D-NAND memory cell structure

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4762036B2 (ja) * 2006-04-14 2011-08-31 株式会社東芝 半導体装置
JP4921848B2 (ja) * 2006-05-09 2012-04-25 株式会社東芝 半導体装置およびその製造方法
JP4764267B2 (ja) * 2006-06-27 2011-08-31 株式会社東芝 半導体装置およびその製造方法
JP4331189B2 (ja) * 2006-09-20 2009-09-16 株式会社東芝 不揮発性半導体メモリ
KR100856165B1 (ko) * 2006-09-29 2008-09-03 주식회사 하이닉스반도체 플래시 메모리 소자의 제조 방법
JP2008098510A (ja) * 2006-10-13 2008-04-24 Toshiba Corp 不揮発性半導体記憶装置
JP4855958B2 (ja) * 2007-01-25 2012-01-18 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
JP5313547B2 (ja) * 2008-05-09 2013-10-09 東京エレクトロン株式会社 半導体装置の製造方法
KR101587198B1 (ko) * 2008-07-09 2016-01-20 샌디스크 테크놀로지스, 인코포레이티드 플로팅 게이트 위의 유전체 캡
US20100093142A1 (en) * 2008-10-09 2010-04-15 Powerchip Semiconductor Corp. Method of fabricating device
JP5361328B2 (ja) * 2008-10-27 2013-12-04 株式会社東芝 不揮発性半導体記憶装置の製造方法
WO2010117703A2 (en) * 2009-03-31 2010-10-14 Applied Materials, Inc. Method of selective nitridation
JP2011077321A (ja) * 2009-09-30 2011-04-14 Tokyo Electron Ltd 選択的プラズマ窒化処理方法及びプラズマ窒化処理装置
US8748259B2 (en) * 2010-03-02 2014-06-10 Applied Materials, Inc. Method and apparatus for single step selective nitridation
KR20110114970A (ko) * 2010-04-14 2011-10-20 삼성전자주식회사 플래시 메모리 소자의 제조 방법
JP2012009700A (ja) * 2010-06-25 2012-01-12 Toshiba Corp 半導体記憶装置及びその製造方法
JP2012089817A (ja) * 2010-09-21 2012-05-10 Toshiba Corp 半導体記憶装置およびその製造方法
JP2012114199A (ja) * 2010-11-24 2012-06-14 Toshiba Corp 半導体装置および半導体装置の製造方法

Also Published As

Publication number Publication date
US20130119451A1 (en) 2013-05-16
JP2014533437A (ja) 2014-12-11
KR20140100948A (ko) 2014-08-18
KR102092760B1 (ko) 2020-03-24
CN103930992A (zh) 2014-07-16
US8994089B2 (en) 2015-03-31
WO2013070685A1 (en) 2013-05-16
CN103930992B (zh) 2017-02-15

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