KR102092760B1 - 층간 폴리실리콘 유전체 캡 및 그것을 형성하는 방법 - Google Patents

층간 폴리실리콘 유전체 캡 및 그것을 형성하는 방법 Download PDF

Info

Publication number
KR102092760B1
KR102092760B1 KR1020147015276A KR20147015276A KR102092760B1 KR 102092760 B1 KR102092760 B1 KR 102092760B1 KR 1020147015276 A KR1020147015276 A KR 1020147015276A KR 20147015276 A KR20147015276 A KR 20147015276A KR 102092760 B1 KR102092760 B1 KR 102092760B1
Authority
KR
South Korea
Prior art keywords
containing layer
nitrogen
oxygen
floating gate
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020147015276A
Other languages
English (en)
Korean (ko)
Other versions
KR20140100948A (ko
Inventor
매튜 에스. 로저스
클라우스 슈에그라프
Original Assignee
어플라이드 머티어리얼스, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어플라이드 머티어리얼스, 인코포레이티드 filed Critical 어플라이드 머티어리얼스, 인코포레이티드
Publication of KR20140100948A publication Critical patent/KR20140100948A/ko
Application granted granted Critical
Publication of KR102092760B1 publication Critical patent/KR102092760B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0451—Apparatus for manufacturing or treating in a plurality of work-stations
    • H10P72/0452—Apparatus for manufacturing or treating in a plurality of work-stations characterised by the layout of the process chambers
    • H10P72/0454—Apparatus for manufacturing or treating in a plurality of work-stations characterised by the layout of the process chambers surrounding a central transfer chamber

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Formation Of Insulating Films (AREA)
KR1020147015276A 2011-11-11 2012-11-07 층간 폴리실리콘 유전체 캡 및 그것을 형성하는 방법 Active KR102092760B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/294,608 2011-11-11
US13/294,608 US8994089B2 (en) 2011-11-11 2011-11-11 Interlayer polysilicon dielectric cap and method of forming thereof
PCT/US2012/063841 WO2013070685A1 (en) 2011-11-11 2012-11-07 Interlayer polysilicon dielectric cap and method of forming thereof

Publications (2)

Publication Number Publication Date
KR20140100948A KR20140100948A (ko) 2014-08-18
KR102092760B1 true KR102092760B1 (ko) 2020-03-24

Family

ID=48279770

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020147015276A Active KR102092760B1 (ko) 2011-11-11 2012-11-07 층간 폴리실리콘 유전체 캡 및 그것을 형성하는 방법

Country Status (5)

Country Link
US (1) US8994089B2 (https=)
JP (1) JP6104928B2 (https=)
KR (1) KR102092760B1 (https=)
CN (1) CN103930992B (https=)
WO (1) WO2013070685A1 (https=)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8981466B2 (en) * 2013-03-11 2015-03-17 International Business Machines Corporation Multilayer dielectric structures for semiconductor nano-devices
US10192747B2 (en) 2014-01-07 2019-01-29 Cypress Semiconductor Corporation Multi-layer inter-gate dielectric structure and method of manufacturing thereof
US20150194537A1 (en) * 2014-01-07 2015-07-09 Spansion Llc Multi-layer inter-gate dielectric structure
US20160343722A1 (en) * 2015-05-21 2016-11-24 Sandisk Technologies Inc. Nonvolatile storage with gap in inter-gate dielectric
US11588031B2 (en) * 2019-12-30 2023-02-21 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure for memory device and method for forming the same
US11587796B2 (en) * 2020-01-23 2023-02-21 Applied Materials, Inc. 3D-NAND memory cell structure

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008010480A (ja) 2006-06-27 2008-01-17 Toshiba Corp 半導体装置およびその製造方法
JP2009272547A (ja) 2008-05-09 2009-11-19 Tokyo Electron Ltd 半導体装置の製造方法
US20110217834A1 (en) 2010-03-02 2011-09-08 Applied Materials, Inc. Method and apparatus for single step selective nitridation

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4762036B2 (ja) * 2006-04-14 2011-08-31 株式会社東芝 半導体装置
JP4921848B2 (ja) * 2006-05-09 2012-04-25 株式会社東芝 半導体装置およびその製造方法
JP4331189B2 (ja) * 2006-09-20 2009-09-16 株式会社東芝 不揮発性半導体メモリ
KR100856165B1 (ko) * 2006-09-29 2008-09-03 주식회사 하이닉스반도체 플래시 메모리 소자의 제조 방법
JP2008098510A (ja) * 2006-10-13 2008-04-24 Toshiba Corp 不揮発性半導体記憶装置
JP4855958B2 (ja) * 2007-01-25 2012-01-18 株式会社東芝 不揮発性半導体記憶装置及びその製造方法
KR101587198B1 (ko) * 2008-07-09 2016-01-20 샌디스크 테크놀로지스, 인코포레이티드 플로팅 게이트 위의 유전체 캡
US20100093142A1 (en) * 2008-10-09 2010-04-15 Powerchip Semiconductor Corp. Method of fabricating device
JP5361328B2 (ja) * 2008-10-27 2013-12-04 株式会社東芝 不揮発性半導体記憶装置の製造方法
WO2010117703A2 (en) * 2009-03-31 2010-10-14 Applied Materials, Inc. Method of selective nitridation
JP2011077321A (ja) * 2009-09-30 2011-04-14 Tokyo Electron Ltd 選択的プラズマ窒化処理方法及びプラズマ窒化処理装置
KR20110114970A (ko) * 2010-04-14 2011-10-20 삼성전자주식회사 플래시 메모리 소자의 제조 방법
JP2012009700A (ja) * 2010-06-25 2012-01-12 Toshiba Corp 半導体記憶装置及びその製造方法
JP2012089817A (ja) * 2010-09-21 2012-05-10 Toshiba Corp 半導体記憶装置およびその製造方法
JP2012114199A (ja) * 2010-11-24 2012-06-14 Toshiba Corp 半導体装置および半導体装置の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008010480A (ja) 2006-06-27 2008-01-17 Toshiba Corp 半導体装置およびその製造方法
US20080121972A1 (en) 2006-06-27 2008-05-29 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
JP2009272547A (ja) 2008-05-09 2009-11-19 Tokyo Electron Ltd 半導体装置の製造方法
US20110073931A1 (en) 2008-05-09 2011-03-31 Tokyo Electron Limited Semiconductor device manufacturing method
US20110217834A1 (en) 2010-03-02 2011-09-08 Applied Materials, Inc. Method and apparatus for single step selective nitridation

Also Published As

Publication number Publication date
US20130119451A1 (en) 2013-05-16
JP2014533437A (ja) 2014-12-11
KR20140100948A (ko) 2014-08-18
CN103930992A (zh) 2014-07-16
US8994089B2 (en) 2015-03-31
WO2013070685A1 (en) 2013-05-16
JP6104928B2 (ja) 2017-03-29
CN103930992B (zh) 2017-02-15

Similar Documents

Publication Publication Date Title
JP2023027173A (ja) エアギャップの形成方法
US20230178419A1 (en) Scaled liner layer for isolation structure
TWI708322B (zh) 製造用於半導體應用的環繞式水平閘極裝置的奈米線的方法
TWI881953B (zh) 用於3d nand應用之記憶體單元製造與裝置
KR102483741B1 (ko) 진보된 패터닝 프로세스에서의 스페이서 퇴적 및 선택적 제거를 위한 장치 및 방법들
US7910497B2 (en) Method of forming dielectric layers on a substrate and apparatus therefor
KR101106882B1 (ko) 높은―ｋ 물질 게이트 구조물을 고온 에칭하는 방법
TWI604562B (zh) 選擇性氮化方法
US9640385B2 (en) Gate electrode material residual removal process
TWI594331B (zh) Semiconductor device and method of manufacturing the same
TWI903529B (zh) 在基板上製造記憶體單元裝置的方法
TWI839600B (zh) 低溫無蒸汽氧化物間隙填充
KR102092760B1 (ko) 층간 폴리실리콘 유전체 캡 및 그것을 형성하는 방법
US10249507B2 (en) Methods for selective etching of a silicon material
CN106504991B (zh) 用于制造半导体应用的水平全环栅极器件的纳米线的方法
KR102093551B1 (ko) 티타늄 실리사이드 영역을 형성하는 방법
KR102959651B1 (ko) 순차적인 플라즈마 및 열적 처리

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

D13-X000 Search requested

St.27 status event code: A-1-2-D10-D13-srh-X000

D14-X000 Search report completed

St.27 status event code: A-1-2-D10-D14-srh-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000