JP5965841B2 - ＨＯＴ（ｈｙｂｒｉｄｏｒｉｅｎｔａｔｉｏｎｔｅｃｈｎｏｌｏｇｙ）を選択的エピタキシーに関連して用いて移動度を改善する方法およびそれに関連する装置 - Google Patents

ＨＯＴ（ｈｙｂｒｉｄｏｒｉｅｎｔａｔｉｏｎｔｅｃｈｎｏｌｏｇｙ）を選択的エピタキシーに関連して用いて移動度を改善する方法およびそれに関連する装置 Download PDF

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JP5965841B2
JP5965841B2 JP2012534387A JP2012534387A JP5965841B2 JP 5965841 B2 JP5965841 B2 JP 5965841B2 JP 2012534387 A JP2012534387 A JP 2012534387A JP 2012534387 A JP2012534387 A JP 2012534387A JP 5965841 B2 JP5965841 B2 JP 5965841B2
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substrate
epitaxial layer
semiconductor device
transistor
crystal plane
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JP2013508951A (ja
JP2013508951A5 (enExample
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エイチ オーウェン アレクサンダー
エイチ オーウェン アレクサンダー
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National Semiconductor Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/751—Insulated-gate field-effect transistors [IGFET] having composition variations in the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
JP2012534387A 2009-10-16 2010-10-15 ＨＯＴ（ｈｙｂｒｉｄｏｒｉｅｎｔａｔｉｏｎｔｅｃｈｎｏｌｏｇｙ）を選択的エピタキシーに関連して用いて移動度を改善する方法およびそれに関連する装置 Active JP5965841B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/589,027 2009-10-16
US12/589,027 US8395216B2 (en) 2009-10-16 2009-10-16 Method for using hybrid orientation technology (HOT) in conjunction with selective epitaxy to form semiconductor devices with regions of different electron and hole mobilities and related apparatus
PCT/US2010/052816 WO2011047244A2 (en) 2009-10-16 2010-10-15 Method for improved mobility using hybrid orientation technology (hot) in conjunction with selective epitaxy and related apparatus

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JP2013508951A JP2013508951A (ja) 2013-03-07
JP2013508951A5 JP2013508951A5 (enExample) 2013-11-28
JP5965841B2 true JP5965841B2 (ja) 2016-08-10

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US (2) US8395216B2 (enExample)
JP (1) JP5965841B2 (enExample)
CN (1) CN102549747B (enExample)
TW (1) TWI566378B (enExample)
WO (1) WO2011047244A2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5772068B2 (ja) 2011-03-04 2015-09-02 富士通セミコンダクター株式会社 半導体装置及びその製造方法
JP6019599B2 (ja) * 2011-03-31 2016-11-02 ソニー株式会社 半導体装置、および、その製造方法
JP5612035B2 (ja) 2012-07-31 2014-10-22 株式会社東芝 半導体装置
US9666493B2 (en) 2015-06-24 2017-05-30 International Business Machines Corporation Semiconductor device structure with 110-PFET and 111-NFET curent flow direction
US9972683B2 (en) 2015-10-27 2018-05-15 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US10109638B1 (en) * 2017-10-23 2018-10-23 Globalfoundries Singapore Pte. Ltd. Embedded non-volatile memory (NVM) on fully depleted silicon-on-insulator (FD-SOI) substrate
US12020980B2 (en) * 2021-07-07 2024-06-25 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and forming method thereof
CN115050631A (zh) * 2022-08-15 2022-09-13 合肥晶合集成电路股份有限公司 半导体器件及其制造方法

Family Cites Families (55)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04372166A (ja) * 1991-06-21 1992-12-25 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US5308782A (en) * 1992-03-02 1994-05-03 Motorola Semiconductor memory device and method of formation
JP3771283B2 (ja) * 1993-09-29 2006-04-26 株式会社ルネサステクノロジ 半導体集積回路装置
US5770482A (en) * 1996-10-08 1998-06-23 Advanced Micro Devices, Inc. Multi-level transistor fabrication method with a patterned upper transistor substrate and interconnection thereto
US6140163A (en) * 1997-07-11 2000-10-31 Advanced Micro Devices, Inc. Method and apparatus for upper level substrate isolation integrated with bulk silicon
TW449869B (en) * 1998-06-04 2001-08-11 United Microelectronics Corp Manufacturing method for stacked integrated circuit
JP2001338988A (ja) 2000-05-25 2001-12-07 Hitachi Ltd 半導体装置及びその製造方法
JP4322453B2 (ja) * 2001-09-27 2009-09-02 株式会社東芝 半導体装置およびその製造方法
JP2003243528A (ja) * 2002-02-13 2003-08-29 Toshiba Corp 半導体装置
US7138310B2 (en) * 2002-06-07 2006-11-21 Amberwave Systems Corporation Semiconductor devices having strained dual channel layers
JP4850387B2 (ja) * 2002-12-09 2012-01-11 ルネサスエレクトロニクス株式会社 半導体装置
JP3974542B2 (ja) * 2003-03-17 2007-09-12 株式会社東芝 半導体基板の製造方法および半導体装置の製造方法
US7329923B2 (en) * 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US6830962B1 (en) * 2003-08-05 2004-12-14 International Business Machines Corporation Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processes
KR100554465B1 (ko) * 2003-11-19 2006-03-03 한국전자통신연구원 ＳＯＩ 기판 위에 구현된 ＳｉＧｅ ＢｉＣＭＯＳ 소자 및그 제조 방법
US6995456B2 (en) * 2004-03-12 2006-02-07 International Business Machines Corporation High-performance CMOS SOI devices on hybrid crystal-oriented substrates
US6998684B2 (en) * 2004-03-31 2006-02-14 International Business Machines Corporation High mobility plane CMOS SOI
US7087965B2 (en) * 2004-04-22 2006-08-08 International Business Machines Corporation Strained silicon CMOS on hybrid crystal orientations
JP2006032543A (ja) * 2004-07-14 2006-02-02 Seiko Instruments Inc 半導体集積回路装置
US7199451B2 (en) 2004-09-30 2007-04-03 Intel Corporation Growing [110] silicon on [001]-oriented substrate with rare-earth oxide buffer film
JP2006108365A (ja) * 2004-10-05 2006-04-20 Renesas Technology Corp 半導体装置およびその製造方法
US7274073B2 (en) * 2004-10-08 2007-09-25 International Business Machines Corporation Integrated circuit with bulk and SOI devices connected with an epitaxial region
US7226833B2 (en) * 2004-10-29 2007-06-05 Freescale Semiconductor, Inc. Semiconductor device structure and method therefor
DE102004052578B4 (de) * 2004-10-29 2009-11-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Erzeugen einer unterschiedlichen mechanischen Verformung in unterschiedlichen Kanalgebieten durch Bilden eines Ätzstoppschichtstapels mit unterschiedlich modifizierter innerer Spannung
US7230270B2 (en) * 2004-11-24 2007-06-12 Taiwan Semiconductor Manfacturing Company, Ltd. Self-aligned double gate device and method for forming same
US7268377B2 (en) * 2005-02-25 2007-09-11 International Business Machines Corporation Structure and method of fabricating a hybrid substrate for high-performance hybrid-orientation silicon-on-insulator CMOS devices
JP2006261235A (ja) 2005-03-15 2006-09-28 Toshiba Corp 半導体装置
US7432149B2 (en) 2005-06-23 2008-10-07 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS on SOI substrates with hybrid crystal orientations
US7358551B2 (en) 2005-07-21 2008-04-15 International Business Machines Corporation Structure and method for improved stress and yield in pFETs with embedded SiGe source/drain regions
US7524707B2 (en) 2005-08-23 2009-04-28 Freescale Semiconductor, Inc. Modified hybrid orientation technology
US7696574B2 (en) * 2005-10-26 2010-04-13 International Business Machines Corporation Semiconductor substrate with multiple crystallographic orientations
US8159030B2 (en) * 2005-11-30 2012-04-17 Globalfoundries Inc. Strained MOS device and methods for its fabrication
JP5322148B2 (ja) * 2005-12-22 2013-10-23 国立大学法人東北大学 半導体装置
US7691698B2 (en) * 2006-02-21 2010-04-06 International Business Machines Corporation Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain
US7573104B2 (en) 2006-03-06 2009-08-11 International Business Machines Corporation CMOS device on hybrid orientation substrate comprising equal mobility for perpendicular devices of each type
US7385257B2 (en) * 2006-04-26 2008-06-10 International Business Machines Corporation Hybrid orientation SOI substrates, and method for forming the same
US7452784B2 (en) 2006-05-25 2008-11-18 International Business Machines Corporation Formation of improved SOI substrates using bulk semiconductor wafers
US7803690B2 (en) * 2006-06-23 2010-09-28 Taiwan Semiconductor Manufacturing Company, Ltd. Epitaxy silicon on insulator (ESOI)
JP2008108999A (ja) * 2006-10-27 2008-05-08 Sony Corp 半導体装置および半導体装置の製造方法
US7482209B2 (en) 2006-11-13 2009-01-27 International Business Machines Corporation Hybrid orientation substrate and method for fabrication of thereof
US20080128821A1 (en) 2006-12-04 2008-06-05 Texas Instruments Incorporated Semiconductor Device Manufactured Using Passivation of Crystal Domain Interfaces in Hybrid Orientation Technology
US7521776B2 (en) * 2006-12-29 2009-04-21 International Business Machines Corporation Soft error reduction of CMOS circuits on substrates with hybrid crystal orientation using buried recombination centers
US20080203484A1 (en) * 2007-02-23 2008-08-28 Infineon Technologies Ag Field effect transistor arrangement and method of producing a field effect transistor arrangement
US7818702B2 (en) * 2007-02-28 2010-10-19 International Business Machines Corporation Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates
US7575968B2 (en) * 2007-04-30 2009-08-18 Freescale Semiconductor, Inc. Inverse slope isolation and dual surface orientation integration
US7790528B2 (en) * 2007-05-01 2010-09-07 Freescale Semiconductor, Inc. Dual substrate orientation or bulk on SOI integrations using oxidation for silicon epitaxy spacer formation
JP2008300575A (ja) * 2007-05-30 2008-12-11 Oki Electric Ind Co Ltd 半導体記憶装置およびその製造方法
US7906381B2 (en) 2007-07-05 2011-03-15 Stmicroelectronics S.A. Method for integrating silicon-on-nothing devices with standard CMOS devices
JP2009064860A (ja) * 2007-09-05 2009-03-26 Renesas Technology Corp 半導体装置
US20090072312A1 (en) * 2007-09-14 2009-03-19 Leland Chang Metal High-K (MHK) Dual Gate Stress Engineering Using Hybrid Orientation (HOT) CMOS
KR20090038653A (ko) 2007-10-16 2009-04-21 삼성전자주식회사 Ｃｍｏｓ 소자 및 그 제조방법
US8120110B2 (en) * 2008-08-08 2012-02-21 International Business Machines Corporation Semiconductor structure including a high performance FET and a high voltage FET on a SOI substrate
US20100047985A1 (en) * 2008-08-19 2010-02-25 Advanced Micro Devices, Inc. Method for fabricating a semiconductor device with self-aligned stressor and extension regions
JP5032418B2 (ja) * 2008-08-22 2012-09-26 株式会社東芝 電界効果トランジスタ、集積回路素子、及びそれらの製造方法
US8048791B2 (en) * 2009-02-23 2011-11-01 Globalfoundries Inc. Method of forming a semiconductor device

Also Published As

Publication number Publication date
CN102549747B (zh) 2019-03-22
US8765534B2 (en) 2014-07-01
US20130157424A1 (en) 2013-06-20
JP2013508951A (ja) 2013-03-07
WO2011047244A2 (en) 2011-04-21
TWI566378B (zh) 2017-01-11
US20110089473A1 (en) 2011-04-21
WO2011047244A3 (en) 2011-07-21
CN102549747A (zh) 2012-07-04
TW201131742A (en) 2011-09-16
US8395216B2 (en) 2013-03-12

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