JP5947293B2 - オプトエレクトロニクス部品の製造方法 - Google Patents
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- 239000012777 electrically insulating material Substances 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 19
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Description
Claims (12)
- オプトエレクトロニクス部品を製造する方法であって、
前記オプトエレクトロニクス部品は、
活性層(3)を有する半導体積層体(20)を備えた半導体チップ(1)と、金属または金属合金の接合層(14)によって前記半導体チップ(1)に接合されているキャリア(12)と、を有するオプトエレクトロニクス部品であって、
− 前記半導体チップ(1)が、第1の電気接続領域(18)および第2の電気接続領域(19)を備えており、
− 前記第1の電気接続領域(18)および前記第2の電気接続領域(19)が前記キャリア(12)の側にあり、
− 前記キャリア(12)が、前記半導体チップ(1)とは反対側のその裏面に、第1の裏面電気コンタクト(28)および第2の裏面電気コンタクト(29)を備えており、
− 前記第1の裏面電気コンタクト(28)が、前記キャリア(12)を貫いている少なくとも1つのビア(15)によって、前記第1の電気接続領域(18)に導電接続されており、
− 前記第2の裏面電気コンタクト(29)が、前記キャリア(12)を貫いている少なくとも1つのビア(16)によって、前記第2の電気接続領域(19)に導電接続されており、
− 前記第1の裏面電気コンタクト(28)もしくは前記第2の裏面電気コンタクト(29)またはその両方が、それぞれ、前記キャリア(12)を貫いている少なくとも1つのさらなるビア(15,16)によって、前記第1の電気接続領域(18)または前記第2の電気接続領域(19)に接続されており、
前記ビア(15,16)が、前記接合層(14)と同じ金属または同じ金属合金から形成されており、
前記接合層(14)が、互いに電気的に絶縁されている少なくとも2つのサブ領域(14a,14b)を備えており、前記少なくとも2つのサブ領域(14a,14b)が、電気的絶縁材料(17)によって互いに隔てられている、オプトエレクトロニクス部品であり、
以下の方法ステップ、すなわち、
− 前記キャリア(12)を形成するステップであって、前記キャリア(12)が、前記ビア(15,16)を形成するための複数の開口部(22)を備えている、ステップと、
− 前記半導体チップ(1)を形成するステップであって、前記半導体チップ(1)が前記第1の電気接続領域(18)および前記第2の電気接続領域(19)を備えており、前記第1の電気接続領域(18)と前記第2の電気接続領域(19)が、前記半導体チップ(1)内の凹部(23)によって互いに隔てられている、ステップと、
− 前記凹部(23)に電気的絶縁材料(17)を満たすステップであって、前記電気的絶縁材料(17)が前記接続領域(18,19)のサブ領域の上に突き出すように行われる、ステップと、
− 前記半導体チップ(1)の上に前記キャリア(12)を配置するステップであって、前記接続領域(18,19)の上に突き出している前記電気的絶縁材料(17)がスペーサ層として機能し、したがって前記半導体チップ(1)と前記キャリア(12)との間に空間(24)が生じる、ステップと、
− 前記キャリア(12)における前記開口部(22)を通じて前記空間(24)内に液体金属または液体金属合金を注入するステップであって、前記金属または前記金属合金が、凝固後に前記接合層(14)および前記ビア(15,16)を形成する、ステップと、
を有する、方法。 - 前記接合層(14)および前記ビア(15,16)を形成するときに前記裏面コンタクト(28,29)も形成され、前記開口部(22)の中に前記液体金属または前記液体金属合金を注入する前に、前記キャリア(12)の前記裏面に、パターニングされた層(26)が形成され、前記パターニングされた層(26)が、前記第1の裏面電気コンタクト(28)および前記第2の裏面電気コンタクト(29)を形成するためのマスクとしての役割を果たす、
請求項1に記載の方法。 - 前記電気的絶縁材料(17)がポリマーである、
請求項1または請求項2に記載の方法。 - 前記第1の裏面電気コンタクト(28)および前記第2の裏面電気コンタクト(29)の両方が、それぞれ、前記キャリア(12)を貫いている少なくとも2つのビア(15,16)によって、前記第1の電気接続領域(18)または前記第2の電気接続領域(19)に接続されている、
請求項1から請求項3のいずれかに記載の方法。 - 前記ビア(15,16)の少なくとも1つが、少なくとも30μmの幅を有する、
請求項1から請求項4のいずれかに記載の方法。 - 前記ビア(15,16)の少なくとも1つが、少なくとも60μmの幅を有する、
請求項1から請求項5のいずれかに記載の方法。 - − 前記半導体積層体(20)が、n型ドープ半導体領域(2)とp型ドープ半導体領域(4)とを備えており、前記p型ドープ半導体領域(4)が前記キャリアの側にあり、
− 前記半導体チップ(1)が、前記第1の電気接続領域(18)を前記p型ドープ半導体領域(4)に接続している第1の電気接続層(8)を備えており、
− 前記半導体チップ(1)が、前記第2の電気接続領域(19)を前記n型ドープ半導体領域(2)に接続している第2の電気接続層(9)を備えており、
− 前記第2の電気接続層(9)のサブ領域が、少なくとも1つの孔(25)の中に延在しており、前記少なくとも1つの孔(25)が、前記p型ドープ半導体領域(4)と前記活性層(3)とを通って前記n型ドープ半導体領域(2)内まで達している、
請求項1から請求項6のいずれかに記載の方法。 - 前記第2の電気接続層(9)が複数のサブ領域を備えており、前記複数のサブ領域が、前記活性層(3)における複数の孔(25)の中を、前記n型ドープ半導体領域(2)内まで延在している、
請求項7に記載の方法。 - 前記電気的絶縁材料(17)がポリマーである、
請求項1から請求項8のいずれかに記載の方法。 - 前記第1の裏面電気コンタクト(28)および前記第2の裏面電気コンタクト(29)が、前記ビア(15,16)と同じ金属または同じ金属合金から形成されている、
請求項1から請求項9のいずれかに記載の方法。 - 前記金属または前記金属合金が、Cu、Au、AuSn、またはBiAgを含んでいる、
請求項1から請求項10のいずれかに記載の方法。 - 前記金属または前記金属合金に収縮巣が存在しない、
請求項1から請求項6のいずれかに記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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DE102010025320.0 | 2010-06-28 | ||
DE102010025320.0A DE102010025320B4 (de) | 2010-06-28 | 2010-06-28 | Optoelektronisches Bauelement und Verfahren zu dessen Herstellung |
PCT/EP2011/058579 WO2012000725A1 (de) | 2010-06-28 | 2011-05-25 | Optoelektronisches bauelement und verfahren zu dessen herstellung |
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JP2013529853A JP2013529853A (ja) | 2013-07-22 |
JP2013529853A5 JP2013529853A5 (ja) | 2014-07-10 |
JP5947293B2 true JP5947293B2 (ja) | 2016-07-06 |
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US (1) | US9263655B2 (ja) |
EP (1) | EP2586068A1 (ja) |
JP (1) | JP5947293B2 (ja) |
KR (1) | KR101781061B1 (ja) |
CN (1) | CN102959741B (ja) |
DE (1) | DE102010025320B4 (ja) |
WO (1) | WO2012000725A1 (ja) |
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DE102010025320B4 (de) | 2010-06-28 | 2021-11-11 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Optoelektronisches Bauelement und Verfahren zu dessen Herstellung |
EP2859597B1 (en) | 2012-06-07 | 2020-03-18 | Lumileds Holding B.V. | Chip scale light emitting device with metal pillars in a molding compound formed at wafer level |
US8816383B2 (en) * | 2012-07-06 | 2014-08-26 | Invensas Corporation | High performance light emitting diode with vias |
US9257579B2 (en) * | 2012-07-30 | 2016-02-09 | Electronics And Telecommunications Research Institute | Electronic devices and method of fabricating the same |
DE102012107921A1 (de) | 2012-08-28 | 2014-03-06 | Osram Opto Semiconductors Gmbh | Verfahren zur Herstellung eines optoelektronischen Halbleiterchips |
DE102012108883A1 (de) | 2012-09-20 | 2014-03-20 | Osram Opto Semiconductors Gmbh | Optoelektronischer Halbleiterchip und Verfahren zur Herstellung von optoelektronischen Halbleiterchips |
DE102012109028A1 (de) | 2012-09-25 | 2014-03-27 | Osram Opto Semiconductors Gmbh | Optoelektronisches Halbleiterbauteil und Verfahren zur Herstellung eines optoelektronischen Halbleiterbauteils |
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KR101781061B1 (ko) | 2017-09-25 |
CN102959741A (zh) | 2013-03-06 |
DE102010025320A1 (de) | 2011-12-29 |
JP2013529853A (ja) | 2013-07-22 |
CN102959741B (zh) | 2017-05-10 |
US20130187192A1 (en) | 2013-07-25 |
WO2012000725A1 (de) | 2012-01-05 |
US9263655B2 (en) | 2016-02-16 |
DE102010025320B4 (de) | 2021-11-11 |
KR20130036756A (ko) | 2013-04-12 |
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