JP5936513B2 - 横型高耐圧トランジスタの製造方法 - Google Patents
横型高耐圧トランジスタの製造方法 Download PDFInfo
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- 238000004519 manufacturing process Methods 0.000 title claims description 35
- 238000009792 diffusion process Methods 0.000 claims description 119
- 239000004065 semiconductor Substances 0.000 claims description 90
- 239000000758 substrate Substances 0.000 claims description 37
- 238000005468 ion implantation Methods 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 16
- 238000010438 heat treatment Methods 0.000 claims description 9
- 230000015556 catabolic process Effects 0.000 description 50
- 239000012535 impurity Substances 0.000 description 22
- 238000009826 distribution Methods 0.000 description 12
- 230000005684 electric field Effects 0.000 description 11
- 230000000694 effects Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 230000008054 signal transmission Effects 0.000 description 4
- 239000012141 concentrate Substances 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000000691 measurement method Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
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Description
<構成>
図15に、前提技術としての横型高耐圧トランジスタの断面斜視図を示す。従来の横型高耐圧トランジスタの例として、PチャネルMOSFETについて説明する。第1導電型、即ちP−型の半導体基板1の主面側には、リサーフ領域として第2導電型即ちN型の半導体層3が形成される。N型の半導体層3の表面には、P+型拡散層としてのソース領域6およびドレイン領域5が、互いに距離を隔てて形成されている。
図17に示す様に、配線9とドレイン電極10を同電位にした状態で、ソース電極11に高電圧が印加されると、点線の内側領域に空乏領域20が広がる。つまり、ドレイン領域5と、各拡散層5fと、半導体層3の大部分とが、空乏化されることにより、高耐圧が保持される。この状態で、ゲート電極8に閾値電圧以上の電圧が印加されると、ゲート絶縁膜直下の半導体層表面に反転層(チャネル)が形成されて、横型高耐圧トランジスタはオン状態となり、ドレイン電流が流れる。
<構成>
まず、本実施の形態における横型高耐圧トランジスタ100の使用例について説明する。本実施の形態における横型高耐圧トランジスタ100が形成される集積回路の部分的な平面図を図1(a)に示す。また、図1(a)の破線部における断面図を図1(b)に示す。この集積回路は、低電位回路部50と、高耐圧島領域30内に形成される高電位回路部を1つのチップ内に備える集積回路である。
本実施の形態における横型高耐圧トランジスタ100の製造方法を説明する。特に、ドリフト領域13の製造工程について詳しく述べる。
本実施の形態における横型高耐圧トランジスタ100の動作について説明する。なお、横型高耐圧トランジスタ100の基本動作は、従来技術で説明したため省略する。
本実施の形態における高耐圧トランジスタは、第1導電型の半導体基板1と、半導体基板1の一方主面に設けられた第2導電型の半導体層3と、半導体層3の表面に選択的に設けられた第1導電型のソース領域6と、半導体層3の表面に、ソース領域6と間隔を隔てて選択的に設けられた第1導電型のドレイン領域5と、ソース領域6とドレイン領域5の間の半導体層3上に、一端がソース領域6と平面視重なって、ゲート絶縁膜を介して設けられたゲート電極8と、半導体層3の表面に、一端がドレイン領域5と接続し、他端がゲート電極8の他端と平面視重なって選択的に設けられた第1導電型のドリフト領域13とを備え、ドリフト領域13は、ドレイン領域5からソース領域6方向に平行に延びるストライプ状の拡散層から構成され、ストライプ状の拡散層を構成する線状の拡散層5bの各々は、互いに隣接しかつ隣接部分が2重に拡散するストライプ状の拡散領域5eにより形成されることを特徴とする。
<構成>
実施の形態1では、各拡散層5bは、隣接する2つのストライプ状の拡散領域5eから構成された。一方、本実施の形態では、各拡散層5bは、隣接する3つのストライプ状の拡散領域5eから構成される。その他の構成は実施の形態1(図2)と同じであるため、説明を省略する。
<構成>
本実施の形態における横型高耐圧トランジスタ100の製造工程において、ドリフト領域13にイオンを注入する際に用いるマスク12に形成される複数のスリット12aは、実施の形態1においてスリットが延びる方向、即ち図2のx方向に断続して形成されている。各スリット12aのスリットが延びる方向の断続間隔は、熱処理工程において、少なくとも拡散領域がスリットが延びる方向につながる間隔であることを特徴とする。
本実施の形態における横型高耐圧トランジスタ100の製造方法において、複数のスリット12aは、スリット12aが延びる方向に断続して形成されており、スリット12aが断続する間隔は、熱処理工程において、少なくとも拡散層5bが、スリット12aが延びる方向につながる間隔であることを特徴とする。従って、拡散層5bは、スリット12aが延びる方向につながっているため、実施の形態1で述べた効果と同様の効果を得ることが可能である。
実施の形態1〜3における横型高耐圧トランジスタ100においては、ソース領域6が形成される半導体層3と、高耐圧島領域(図1参照)は、同一の半導体層3で形成されているため、これらは電気的に分離されていなかった。
図14に、本実施の形態における横型高耐圧トランジスタ100の断面斜視図を示す。本実施の形態における横型高耐圧トランジスタは、ドレイン領域5の表面にN型の拡散層17をさらに備える。それ以外の構成は、実施の形態1(図2)と同じであるため、説明を省略する。
Claims (7)
- 横型高耐圧トランジスタの製造方法であって、
前記横型高耐圧トランジスタは、
第1導電型の半導体基板と、
前記半導体基板の一方主面に設けられた第2導電型の半導体層と、
前記半導体層の表面に選択的に設けられた第1導電型のソース領域と、
前記半導体層の表面に選択的に、前記ソース領域と間隔を隔てて設けられた第1導電型のドレイン領域と、
前記ソース領域と前記ドレイン領域の間の前記半導体層上に、一端が前記ソース領域と平面視重なって、ゲート絶縁膜を介して設けられたゲート電極と、
前記半導体層の表面に選択的に、一端が前記ドレイン領域と接続し、他端が前記ゲート電極の他端と平面視重なって設けられた第1導電型のドリフト領域とを備え、
前記ドリフト領域は、前記ドレイン領域から前記ソース領域方向に平行に延びるストライプ状の拡散層から構成され、
前記ストライプ状の拡散層を構成する線状の拡散層の各々は、互いに隣接しかつ隣接部分が2重に拡散するストライプ状の拡散領域により形成され、
前記横型高耐圧トランジスタの製造方法は、
(a)前記半導体基板を準備する工程と、
(b)前記半導体基板の一方主面に前記半導体層を形成する工程と、
(c)前記半導体層にマスクを被せてイオン注入を行う工程と、
(d)前記工程(c)の後に熱処理により前記拡散層を形成する工程と、
を備え、
前記マスクは、間隔L2以上で形成される複数のスリット群を備え、
前記スリット群の各々は、間隔L1以下で形成される複数のスリットを備え、
前記間隔L1は、前記工程(d)において、隣接する前記スリット間で前記拡散領域がつながる間隔であり、
前記間隔L2は、前記工程(d)において、隣接する前記スリット群間で前記拡散層がつながらない間隔であり、
前記スリットの幅が、1μm以下であることを特徴とする、
横型高耐圧トランジスタの製造方法。 - 前記半導体層は、エピタキシャル層であることを特徴とする、
請求項1に記載の横型高耐圧トランジスタの製造方法。 - 前記半導体層は、前記ソース領域の前記ゲート電極とは反対側の領域において、第1導電型半導体層により分離されていることを特徴とする、
請求項1または2に記載の横型高耐圧トランジスタの製造方法。 - 前記ドレイン領域の表面に第2導電型の拡散層をさらに備えることを特徴とする、
請求項1〜3のいずれかに記載の横型高耐圧トランジスタの製造方法。 - 前記第1導電型とは、P型であり、
前記第2導電型とは、N型であることを特徴とする、
請求項1〜4のいずれかに記載の横型高耐圧トランジスタの製造方法。 - 前記スリット群の間隔は、L2以上の一定値であり、
前記スリットの間隔は、L1以下の一定値であることを特徴とする、
請求項1〜5のいずれかに記載の横型高耐圧トランジスタの製造方法。 - 前記複数のスリットは、前記スリットが延びる方向に断続して形成されており
前記スリットが断続する間隔は、前記工程(d)において、少なくとも前記拡散層が、前記スリットが延びる方向につながる間隔であることを特徴とする、
請求項1〜6のいずれかに記載の横型高耐圧トランジスタの製造方法。
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