JP5934759B2 - チャージポンプ回路およびその動作方法 - Google Patents
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0083—Converters characterised by their input or output configuration
- H02M1/009—Converters characterised by their input or output configuration having two or more independently controlled outputs
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/071—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps adapted to generate a negative voltage output from a positive voltage source
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/072—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps adapted to generate an output voltage whose value is lower than the input voltage
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Description
状態シーケンスにおいて前記異なる端子間にフライングキャパシタを接続し、前記入力供給から前記リザーバキャパシタに、直接または前記フライングキャパシタを介して電荷のパケットを繰り返し転送し、これにより、選択された動作モードに応じて、合計して前記入力電圧にほぼ等しい電圧になり、かつ前記共通端子の電圧を中心とする正負の出力電圧か、それぞれが実質的に前記入力供給に達する正負の出力電圧を有する前記分割レール供給を生成するステップを有する方法が提供される。
1つのフライングキャパシタを使用して、選択された動作モードに応じて、合計して前記入力電圧にほぼ等しい電圧になり、かつ前記共通端子の電圧を中心とする正負の出力電圧か、それぞれが実質的に前記入力供給に達する正負の出力電圧を有する前記分割レール供給を生成する方法も開示される。
−入力電圧への接続のための入力端子および共通端子と、
−前記複数の出力電圧を出力するための第1出力端子および第2出力端子と、前記第1出力端子および第2出力端子は、使用時に、個々の第1負荷および第2負荷と、個々の第1リザーバキャパシタおよび第2リザーバキャパシタとを介して前記共通端子に接続され、
−1つのフライングキャパシタへの接続のための第1フライングキャパシタ端子および第2フライングキャパシタ端子と、
−前記端子間を相互接続するために、複数の異なる状態で動作可能なスイッチ網と、
−前記スイッチ網を前記異なる状態のシーケンスで作動させるためのコントローラと、を有し、
前記コントローラは、第1モードと第2モードで動作可能であり、前記モードの第1モードでは、前記状態に応じて、前記入力供給から前記リザーバキャパシタに、前記フライングキャパシタを介して電荷のパケットを繰り返し転送し、これにより、合計して前記入力電圧にほぼ等しい電圧になり、かつ前記共通端子の電圧を中心とする正負の出力電圧が生成されるように適合されている回路が提供される。
−入力電圧への接続のための入力端子および共通端子と、
−前記複数の出力電圧を出力するための第1出力端子および第2出力端子と、前記第1出力端子および第2出力端子は、使用時に、個々の第1負荷および第2負荷と、個々の第1リザーバキャパシタおよび第2リザーバキャパシタとを介して前記共通端子に接続され、
−複数のフライングキャパシタへの接続のための複数の第1フライングキャパシタ端子および第2フライングキャパシタ端子と、
−前記端子間を相互接続するために、複数の異なる状態で動作可能なスイッチ網と、
−前記スイッチ網を前記異なる状態のシーケンスで作動させるためのコントローラと、を有し、
前記コントローラは、第1モードおよび第2モードにおいて動作可能であり、前記モードの第1モードでは、前記シーケンスは、前記状態に応じて、前記入力供給から前記リザーバキャパシタに、前記フライングキャパシタを介して電荷のパケットを繰り返し転送し、これにより、実質的に前記入力電圧の分数の値の正負の出力電圧が生成されるように適合されており、前記入力電圧の分数が実質的に1/(n+1)である(nは、フライングキャパシタの個数を表す整数)回路が提供される。
1.最初に全てのスイッチが開いている。
2.スイッチSA1,SA2を閉じ(SB1,SB2は開のまま)、これにより、ICP回路100が第1状態で動作する。フライングキャパシタCfが、(図2bに示すように)入力電圧ノードN1と共通基準電圧ノードN3間に接続される。このため、フライングキャパシタCfが電圧+VDDまで充電される。
3.次にスイッチSA1,SA2を開く(SB1,SB2は開いたまま)。
4.次にスイッチSB1,SB2を閉じ(SA1,SA2は開のまま)、これにより、ICP回路100が第2状態で動作する。この状態では、フライングキャパシタCfが、(図2cに示すように)共通基準電圧ノードN3と出力電圧ノードN2間に接続されている負のリザーバキャパシタCR2と並列に接続される。この第1のサイクルでは、最初にキャパシタCR2の充電が0ボルトであるとすると、キャパシタCR2はキャパシタCfと電荷を共有し、両キャパシタの電圧が等しくなる。キャパシタCfの陽極板とCR2の陽極板が共通基準電圧ノードN3(グランド)に接続されているため、CfとCR2のそれぞれのサイズに応じて、ノードN2は、ノードN3に対して−VDDよりやや正の電圧となる。
モード1の主要動作の実施形態では、3段階の高周波数のサイクルで繰り返される3つの基本動作状態が存在し、これらの状態をP1、P2、P3と呼ぶ。DMCP400がモード1で動作しているときは、スイッチS7(存在する場合)は常時開いており、このため、このモードの説明では記載しない。
上で述べたように、DMCPは、±VDD(この場合も、+VDDはノードN10における入力源電圧レベルである)のデュアルレール出力を発生させる第2の主要モード(モード2)でも動作可能である。モード2では、スイッチS4は、常に開いている。
(1)アナログコンポジットビデオ信号を処理する回路用の電圧供給。グランド参照のDCカップリングされた出力信号により、黒色レベルの垂下が回避される。
(2)データリンクまたはモデム(例えばADSL)用のラインドライバ。グランド参照のDCカップリングされた出力信号により、ベースラインワンダーの影響を低減することができる。
Claims (8)
- チャージポンプ回路(400)であって、前記回路(400)は、
入力電圧を受け取るための入力端子(N10)と、
1つのフライングキャパシタへの接続のための、第1フライングキャパシタ端子および第2フライングキャパシタ端子と、
共通端子(N11)と、
第1出力端子(N12)および第2出力端子(N13)であって、前記第1出力端子(N12)および前記第2出力端子(N13)は、使用中に、第1リザーバキャパシタおよび第2リザーバキャパシタを介して前記共通端子(N11)にそれぞれ連結される、第1出力端子(N12)および第2出力端子(N13)と、
前記入力端子(N10)、前記第1フライングキャパシタ端子および前記第2フライングキャパシタ端子、前記共通端子(N11)、ならびに前記第1出力端子(N12)および前記第2出力端子(N13)を相互接続するためのスイッチ網(410)と、
前記スイッチ網(410)を作動させるためのコントローラ(420)であって、前記コントローラ(420)は、前記チャージポンプ回路(400)に接続された単一のフライングキャパシタのみを用いて、第1モードでの使用中に作動可能である、コントローラ(420)と、を備え、
前記第1モードでは、前記コントローラ(420)が少なくとも第1状態および第2状態を有する状態のシーケンスで前記スイッチ網(410)を作動させ、第1正出力電圧および第1負出力電圧を前記第1出力端子(N12)および前記第2出力端子(N13)において生成し、前記第1正出力電圧および前記第1負出力電圧の大きさは、前記入力電圧の大きさの半分にそれぞれ等しく、前記スイッチ網(410)は、直列の前記フライングキャパシタおよび前記第1リザーバキャパシタの間で前記入力電圧を分配するように前記第1状態で作動可能であり、かつ、分配された前記入力電圧のうち前記フライングキャパシタの分を前記第2リザーバキャパシタの全域にわたり印加するように前記第2状態で作動可能である、回路。 - 前記第1状態は、前記フライングキャパシタを前記入力端子(N10)および前記第1出力端子(N12)の全域にわたり接続することにより得られ、前記第2状態は、前記フライングキャパシタを前記共通端子(N11)および前記第2出力端子(N13)の全域にわたり接続することにより得られる、請求項1に記載の回路。
- 前記第1モードにおけるシーケンスは、分配された前記入力電圧のうち前記フライングキャパシタの分が前記第1リザーバキャパシタの全域にわたり印加される第3状態を含む、請求項1または2に記載の回路。
- 前記出力電圧を調節するための比較器(910)を更に備える、請求項1乃至3のいずれか一項に記載の回路。
- 装置であって、
フライングキャパシタ(Cf)と、
第1リザーバキャパシタ(CR1)および第2リザーバキャパシタ(CR2)と、
請求項1乃至4のいずれか一項に記載のチャージポンプ回路と、
を備える、装置。 - 前記装置は、オーディオ装置、携帯電話、MP3プレイヤー、マルチメディアプレイヤー、およびラップトップ型コンピュータのうち少なくとも1つである、請求項5に記載の装置。
- 前記スイッチ網(410)は、
前記入力端子(N10)を前記第1フライングキャパシタ端子に結合するための第1スイッチ(S1)と、
前記第1フライングキャパシタ端子を前記第1出力端子(N12)に結合するための第2スイッチ(S2)と、
前記第1フライングキャパシタ端子を前記共通端子(N11)に結合するための第3スイッチ(S3)と、
前記第2フライングキャパシタ端子を前記第1出力端子(N12)に結合するための第4スイッチ(S4)と、
前記第2フライングキャパシタ端子を前記共通端子(N11)に結合するための第5スイッチ(S5)と、
前記第2フライングキャパシタ端子を前記第2出力端子(N13)に結合するための第6スイッチ(S6)と、
を備える、請求項1乃至6のいずれか一項に記載の回路。 - 入力端子(N10)および共通端子(N11)の全域にわたり受け取られた単一の入力電圧から分割レール電圧供給を生成する方法であって、前記分割レール電圧供給は、前記共通端子(N11)における電圧と、第1リザーバキャパシタおよび第2リザーバキャパシタをそれぞれ介して前記共通端子(N11)に接続された第1出力端子(N12)および第2出力端子(N13)における出力とに集中され、前記方法は、
前記第1出力端子(N12)、前記第2出力端子(N13)、前記入力端子(N10)および前記共通端子(N11)を、1つのフライングキャパシタに接続された第1フライングキャパシタ端子および第2フライングキャパシタ端子と相互接続することと、
単一のフライングキャパシタのみを用いる使用中の状態のシーケンスで作動することであって、前記シーケンスは、直列の単一のフライングキャパシタおよび前記第1リザーバキャパシタの間で前記入力電圧が分配される第1状態と、分配された前記入力電圧のうち前記フライングキャパシタの分が前記第2リザーバキャパシタの全域にわたり印加される第2状態とを含み、それにより第1正出力電圧および第1負出力電圧を生成し、前記第1正出力電圧および前記第1負出力電圧の大きさは、前記入力電圧の大きさの半分にそれぞれ等しいことと、
を含む、方法。
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GB0625954A GB2444984B (en) | 2006-12-22 | 2006-12-22 | Charge pump circuit and methods of operation thereof |
GB0625954.3 | 2006-12-22 |
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KR (3) | KR101194508B1 (ja) |
CN (2) | CN101611531B (ja) |
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EP1758235A3 (en) * | 2005-08-26 | 2013-07-10 | TPO Displays Corp. | Charge pump |
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GB2446843B (en) | 2006-06-30 | 2011-09-07 | Wolfson Microelectronics Plc | Amplifier circuit and methods of operation thereof |
GB2478458B (en) | 2006-12-22 | 2011-12-07 | Wolfson Microelectronics Plc | Charge pump circuit and methods of operation thereof |
GB2444988B (en) * | 2006-12-22 | 2011-07-20 | Wolfson Microelectronics Plc | Audio amplifier circuit and electronic apparatus including the same |
GB2447426B (en) * | 2006-12-22 | 2011-07-13 | Wolfson Microelectronics Plc | Charge pump circuit and methods of operation thereof |
GB2444984B (en) * | 2006-12-22 | 2011-07-13 | Wolfson Microelectronics Plc | Charge pump circuit and methods of operation thereof |
JP5038706B2 (ja) * | 2006-12-27 | 2012-10-03 | ルネサスエレクトロニクス株式会社 | 昇圧回路 |
US7791520B2 (en) * | 2007-04-23 | 2010-09-07 | Qualcomm Incorporated | Low power, low noise digital-to-analog converter reference circuit |
GB0715254D0 (en) * | 2007-08-03 | 2007-09-12 | Wolfson Ltd | Amplifier circuit |
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US20080150619A1 (en) | 2008-06-26 |
KR101374510B1 (ko) | 2014-03-13 |
TWI432936B (zh) | 2014-04-01 |
KR101076989B1 (ko) | 2011-10-26 |
CN101611531B (zh) | 2013-08-14 |
EP2095495B1 (en) | 2015-09-30 |
JP2010530726A (ja) | 2010-09-09 |
KR20120112876A (ko) | 2012-10-11 |
JP5599431B2 (ja) | 2014-10-01 |
KR20090094153A (ko) | 2009-09-03 |
EP2975750A1 (en) | 2016-01-20 |
KR20110069181A (ko) | 2011-06-22 |
US7626445B2 (en) | 2009-12-01 |
JP2012213320A (ja) | 2012-11-01 |
WO2008078120A1 (en) | 2008-07-03 |
GB2444984A (en) | 2008-06-25 |
JP2014239649A (ja) | 2014-12-18 |
EP2095495A1 (en) | 2009-09-02 |
TW200844703A (en) | 2008-11-16 |
CN103401418A (zh) | 2013-11-20 |
CN101611531A (zh) | 2009-12-23 |
KR101194508B1 (ko) | 2012-10-25 |
CN103401418B (zh) | 2016-12-07 |
GB0625954D0 (en) | 2007-02-07 |
GB2444984B (en) | 2011-07-13 |
EP2975750B1 (en) | 2020-08-19 |
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