EP3232553B1

EP3232553B1 - Dc-dc converter

Info

Publication number: EP3232553B1
Application number: EP16165172.4A
Authority: EP
Inventors: Gerard Villar Piqué
Original assignee: NXP BV
Current assignee: NXP BV
Priority date: 2016-04-13
Filing date: 2016-04-13
Publication date: 2022-09-07
Anticipated expiration: 2036-04-13
Also published as: US10008934B2; CN107294382A; EP3232553A1; US20170302180A1; CN107294382B

Description

FIELD

This disclosure relates to DC-DC Power converters.

BACKGROUND

DC-DC power converters also referred to as DC-DC converters typically can be inductive or based on one or more switched-capacitors. In a switched-capacitor power converter (SCPC), charge is transferred from the input to the output nodes by using a number of floating capacitors. Depending on the signals generated by a control loop, power switches are used to transfer charge from one capacitor to another, and finally to the output node, in time discrete events aligned to two phases of a clock signal. The switching results in a certain amount of ripple to the output voltage, which depends on the amount of charge being transferred and the size of the capacitor at the output node. To avoid short-circuits, there is always a pause between turning off the first power switches and turning on the complementary power switches during the charge transfer between capacitors. This pause or period of time is called non-overlapping time, and has a fixed duration which is insignificant compared to the remainder of the switching period.
US 2015/0229207 A1 discloses a charge pump (CP) that operates at low input voltage with high power conversion efficiency.

SUMMARY

The invention provides a DC-DC power converter according to claim 1 and a corresponding method of controlling a DC-DC power converter according to claim 9. Preferred embodiments are defined in the dependent claims.
In the figures and description like reference numerals refer to like features. Embodiments of the invention are now described in detail, by way of example only, illustrated by the accompanying drawings in which:

Figure 1 a) Shows a typical example of a DC-DC converter including a switch capacitor power converter with a pulse frequency modulated (PFM) control loop, b) a graph illustrating the output ripple of the switch capacitor power converter of figure 1a, c) an example waveform of a two-phase non-overlapping clock, and d) an example circuit of a SCPC including an example implementation of a switchable capacitor.
Figure 2 shows a) a DC-DC converter according to an embodiment and b) an illustration of the modulated clock waveforms
Figure 3 shows a DC-DC converter according to an embodiment.
Figure 4 shows a graph of the qualitative evolution of output voltage ripple vs output current for various PFM control loops.
Figure 5a shows a DC-DC converter according to an embodiment.
Figure 5b shows an example time reference circuit for the embodiment of figure 5a.
Figure 6a shows a simulation of the behaviour of the DC-DC converter of figure 5a for an output current of 0.6 mA
Figure 6b shows a simulation of the behaviour of the DC-DC converter of figure 5a for an output current of 6mA
Figure 7a shows a graph illustrating the difference in output ripple between the DC-DC converters of figure 5a and figure 1, for 2 different values of output current.
Figure 7b shows a graph illustrating the voltage swing for the floating capacitor of the DC-DC converters of figure 5a and figure 1.
Figure 7c shows a graph illustrating the variation of output ripple vs output current for the DC-DC converters of figure 5a and figure 1.
Figure 8 shows a method of controlling a DC-DC converter according to an embodiment.

DESCRIPTION

Figure 1a shows a typical example of a DC-DC converter 100 including a switch capacitor power converter (SCPC) 112 that uses pulse-frequency modulated (PFM) control. A comparator 102 has a first input operably connected to a voltage reference Vref and a second input connected to an output 114 of the DC-DC converter 100 for monitoring the output voltage Vo. The output of the comparator 102 is connected to an oscillator 104. The output of the oscillator 104 is connected to a non-overlapping clock phase generator 106. The two outputs 108, 110 of the non-overlapping clock phase generator 106 are connected to the switch capacitor power converter 112, which may convert the power from Vin 116 to Vo 114. The two outputs 108, 110 of the non-overlapping clock phase generator 106 may generate the non-overlapping clocks denoted ph1 and ph2 respectively. The output of the SCPC 114 may be connected to a first terminal of an output capacitor Co. A second terminal of the output capacitor Co may be connected to a ground potential.
Figure 1d shows further detail of an example switch capacitor power converter 112. A first series arrangement of NMOS transistors S1 and S2 may be connected between an input voltage source 118 and the SCPC output 114. A second series arrangement of NMOS transistors S3 and S4 may be connected between the SCPC output 114 and a ground potential. A first terminal of capacitor Cs may be connected to a common connection between transistors S1 and S2. A second terminal of the capacitor Cs may be connected to a common connection between transistors S3 and S4. The gate terminals of NMOS transistors S1 and S4 may be connected to the ph1 non-overlapping clock via connection 108. The gate terminals of NMOS transistors S2 and S3 may be connected to the ph2 non-overlapping clock via connection 110. The capacitor Cs may be considered as a floating capacitor since it can be isolated from the input voltage source 118, the SCPC output, and the ground potential during operation. Capacitor Cs in combination with transistor s1, s2, s3 and s4 may be considered to form a switchable capacitor 116.
In this example switch capacitor power converter 112, during operation when ph1 is a logic high value then NMOS transistors s1 and s4 are enabled or switched on, the SCPC output 114 is coupled to the second terminal of the capacitor Cs and the input voltage Vin is supplied to the first terminal of the capacitor Cs. When ph2 is a logic high value then NMOS transistors s2 and s3 are enabled or switched on, the SCPC output 114 is coupled to the first terminal of the capacitor Cs and the ground potential is supplied to the other terminal. The capacitor Cs is charged to a voltage equal to the difference between Vin and Vo during the first phase of the operation (s1 and s4 are on). During the second phase the accumulated charge in Cs is transferred to the output voltage node (s2 and s3 are on). This alternate operation results in a charge transfer from input to output of the SCPC in time discrete events. During the non-overlapping time when both ph1 and ph2 are logic low value then all NMOS transistors s1 to s4 are switched off and the capacitor Cs is floating. It will be appreciated that in other implementations multiple capacitors and switch arrangements using other transistors for example PMOS transistors, or other elements for forming switches may be used in a switch capacitor power converter.
In operation of the DC-DC converter 100, the output voltage Vo of the SCPC 112 may be monitored continuously with the voltage comparator or error amplifier 102, which compares the output voltage Vo with a reference voltage Vref corresponding to the desired output voltage value. The voltage comparator or error amplifier 102 may be considered to act as an error detector. In other typical examples the comparator may be a clocked comparator that compares the output at discrete time intervals. In other examples the comparator may be an error amplifier for continuous control of the frequency of the oscillator or a mixed-signal circuit including an analog-to-digital converter and additional digital circuitry. The output of the comparator 102 is used to enable and disable the oscillator 104, which may be set to run at a fixed frequency, which may for example be 10 MHz to 20MHz. The oscillator may be enabled when the output voltage Vo is below the reference voltage Vref and disabled if the output voltage Vo is above Vref. The reference voltage Vref may be for example 1.2 volts. The output of the oscillator 104 is connected to the non-overlapping clock phase generator 106 which that generates two complimentary signals (ph1 and ph2) required to drive the power switches s1, s2, s3, s4, with a non-overlapping pause to avoid short-circuits. In other examples, the comparator output may be a variable voltage that controls a voltage controlled oscillator to modulate the frequency dependent on the difference between Vo and Vref. Figure 1c shows example waveforms for a two-phase non-overlapping clock system 140. Waveforms 142, 144 shows the relationship between clocks ph1 and ph2 respectively in a first mode of operation. The non-overlapping time duration is indicated by regions 146. If the reference voltage Vref changes to a lower value corresponding to a lower required output voltage, the time period of the clocks ph1 and ph2 increases as shown in waveforms 142',144' which will lead to a reduction in the output voltage Vo.
Figure 1b shows the variation of output voltage for 2 different values of output current 120. The x-axis 122 indicates time in microseconds between a value of 29 us and 30.7 us corresponding to a duration of approximately 1.7 us. The y-axis 124 indicates the output voltage Vo changing in a range between 1.19 volts and 1.23 volts. The voltage reference value of 1.2 volts in this example is shown be horizontal line 130. The graph line 126 shows the variation in output voltage for an output current of 6 mA. The graph line 128 shows the variation in output voltage for an output current of 0.6 mA. As can be seen from graph 120, the voltage ripple at a lower output current of 0.6 mA shown by line 128 is approximately 25 mV peak-to-peak compared to the voltage ripple at 6 mA of 4 mV peak-to-peak.
Figure 2a shows a DC-DC power converter 200 according to an embodiment. A controller 206 may have a first input 204 operably connected to a voltage reference, a second input connected to a power converter output 214 of the DC-DC power converter 200, and a third input connected to a DC-DC power converter input 216. The clock outputs 210,212 of the controller 206 may be connected to a switch capacitor power converter (SCPC) 208. The switch capacitor power converter 208 may have an input connected to the DC-DC converter input 216. The output of the switched capacitor power converter 208 may be connected to the output 214 of the DC-DC converter 200. An output capacitor Co may be connected between the output 214 and a supply rail which may operably be at a ground potential.
In operation, the controller 206 may vary the frequency of the clock generator 206 in response to the difference between the output voltage and the reference voltage. The clock generator may output a first phase of a non-overlapping clock ph1mod from a first clock output 210 and a second phase of a non-overlapping clock ph2mod from a second clock output 212. The controller 206 may also vary the non-overlapping time duration between ph1mod and ph2mod. The controller 206 may detect the output current drawn from the DC-DC converter 200 by a connected load (not shown) either directly by measuring a current value of Io or indirectly from detecting the value of voltage output Vo. The controller 206 may also detect the changes in the input voltage on DC-DC converter input 216 or the reference value setting on the reference input 204. In other examples the controller may have a predetermined reference value. The controller 206 may vary the non-overlapping time duration of the two clock phases in response to the output current I_o changing, the input voltage changing or the reference setting changing. For example if the controller 206 detects an increase in the current I_ο, the controller 206 may reduce the non-overlap time period between ph1mod and ph2mod.
Consequently when the output current I_o reduces and the switching frequency reduces accordingly, the operation of the SCPC power stage 208 is effectively frozen in the non-overlapping state, that is to say when all the floating capacitors are disconnected, as soon as or shortly after the nominal charge/discharge time has passed.
Figure 2b shows an example waveform of the non-overlapping modulated clocks 220 for DC-DC converter 200. Waveforms 222, 224 shows the relationship between clocks ph1mod and ph2mod respectively in a first mode of operation. The non-overlapping time duration is indicated by regions 226,226'. If a lower output voltage or current is required, the time period of the clocks ph1mod and ph2mod may increase as shown in waveforms 222' and 224'. By increasing the non-overlapping time region 226', the time period 228 corresponding to the on-period of the clock phases 222' and 224' may correspond to a discharge/charge time of a switchable capacitor in the SCPC 208.
In this way the charge/discharge time of the floating capacitors in the SCPC 208 becomes independent of the output current and operating switching frequency. The switching frequency of the DC-DC converter 200 is also being modulated according to the output current, input voltage or reference setting; but instead of modulating the charge/discharge times of the floating capacitors, the controller 206 modulates the duration of the non-overlapping time. This allows a smaller output capacitor Co to be used for a given maximum required output voltage ripple than would otherwise be the case. The DC-DC power converter 200 may reduce the amount of voltage ripple by 50%. In a conventional DC-DC converter, to achieve the same result an output capacitor having twice the capacitance may be required.
Figure 3 shows a DC-DC converter 250 according to an embodiment. A controller 206 may include control logic 252, a comparator 254 and a clock generator 256. The comparator 254 may have a first input operably connected to a reference input 276 which may be a voltage reference, and a second input connected to an output 274 of the DC-DC converter 250. The output of comparator 254 may be connected to the clock generator 256. The modulated clock outputs 260,272 of the clock generator 256 may be connected to a switch capacitor power converter 268. The output of the switched capacitor power converter 268 may be connected to the output 274 of the DC-DC converter 250. An output capacitor Co may be connected between the output 274 and a supply rail which may operably be at a ground potential. The output of the DC-DC converter 250 may be connected to the control logic circuit 252. The control logic circuit 252 may be connected to the clock generator 256.
In operation the comparator 254 may provide a control signal to vary the frequency of the clock generator 256 in response to the difference between the output voltage and the reference voltage. The clock generator may output a first phase of a non-overlapping clock ph1mod from a first clock generator output 260 and a second phase of a non-overlapping clock ph2mod 272 from a second clock generator output 272. The controller 206 may detect the output current drawn from the DC-DC converter 250 by a connected load (not shown) either directly by measuring a current value of I_o or indirectly from detecting the value of voltage output V_o. The controller 206 may also detect the changes in the input voltage on DC-DC converter input 266 or the reference setting on reference input 276 which may be a voltage reference. The controller 206 may vary the non-overlapping time duration of the two clock phases by altering the duty cycle of the clock phases in response to a change in the output current I_ο, the input voltage or the reference setting.
For example if the controller 206 detects an increase in the current I_ο, the controller 206 may reduce the non-overlap time period between ph1mod and ph2mod. When the output current I_ο reduces, the switching frequency may reduce, the operation of the SCPC power stage 268 is effectively frozen in the non-overlapping state, that is to say when all the floating capacitors are disconnected, as soon as or shortly after the nominal charge/discharge time has passed. As a result the non-overlapping time increases.
In this way the charge/discharge time of the floating capacitors in the SCPC 268 becomes independent of the output current and operating switching frequency. The switching frequency of the DC-DC converter 250 is also being modulated according to the output current, input voltage or reference setting; but instead of modulating the charge/discharge times of the floating capacitors, the controller modulates the duration of the non-overlapping time. This allows a smaller output capacitor Co to be used for a given maximum required output voltage ripple than would otherwise be the case.
The variation of the output voltage ripple with output current for embodiments of the DC-DC converter described herein compared with other DC-DC converters is further explained and qualitatively illustrated with respect to figure 4. Graph 280 has an x axis 284 showing output current and a y-axis 282 showing the amount of output voltage ripple. Line 292 shows a typical DC-DC converter with a clocked comparison stage sampled at a frequency fs (fs being equal to the nominal switching frequency of the DC-DC converter). Line 286 shows a typical DC-DC converter with a clocked comparison stage sampled at a higher sampling frequency than fs. Line 288 shows a typical DC-DC converter with a continuous comparison stage similar to that described in figure 1a. Line 290 shows a qualitative variation in output voltage ripple with respect to output current for embodiments of the DC-DC converter described herein.
The DC-DC converters having responses shown in graph 280, use pulse-frequency modulation (PFM) to regulate the output voltage of a SCPC. The output voltage ripple may only reach its minimum value when the output current is maximum. As soon as the output current reduces, there is an increase of the output ripple. Depending on the implementation of the control loop, different effects can be observed at the output:
For example if the control loop of a DC-DC converter samples the output, for example by using a clocked voltage comparator, the increase of the output ripple might be quite sudden due to the finite sampling frequency of the output voltage as shown in lines 292, 286. This problem can be minimized by increasing the sampling frequency, resulting in a reduced voltage ripple shown in line 286 when compared to line 292. However, this may result in increased power consumption due to the higher sampling frequency.
If the control loop continuously monitors the output voltage as described in DC-DC converter 100 and shown in line 288, the increase of the output voltage ripple as the output current decreases may still occur but in a smoother shape than in previous case.
The increase of output voltage ripple when the output current becomes smaller may be caused because the injection of charge to the output node occurs in a finite amount of time. During this time, if the output current is high, a significant amount of charge flows directly to the output and never reaches the output capacitor; which means that it does not increase the output voltage. At low output current, the charge that flows directly to the output during the charge injection event becomes insignificant, resulting in almost all the charge being accumulated at the output node (which increases the output ripple).
The increase of output voltage ripple when the output current becomes smaller may be due to the reduced switching frequency of the DC-DC converter. This may result in an increase of the charge/discharge times of the capacitors and a consequent increase in the charge variation stored in the floating capacitors in the SCPC, which results in a higher output ripple. The DC-DC converter 250 decouples the charge-discharge time of capacitors from the switching frequency of the DC-DC converter resulting in a reduced output voltage ripple as indicated qualitatively by line 290.
Figure 5a shows a DC-DC converter 300 according to an embodiment including a switch capacitor power converter (SCPC) 326 that uses pulse-frequency modulated (PFM) control.
A controller 330 may include a control circuit 310 and a clock generator 318.
The control circuit 310 may include a comparator 302 a time reference 306 and a digital controller 308. The clock generator 318 may include an oscillator 304, a non-overlapping clock phase generator 316, and multiplexers 312,314.
A comparator 302 has a first input operably connected to a voltage reference and a second input connected to the output 324 of the DC-DC converter 300 for monitoring the output voltage Vo. The output of the comparator or error amplifier 302 may be connected to an oscillator 304 such as a voltage controlled oscillator. The output of the oscillator 304 is connected to a non-overlapping clock phase generator 316. Each of the two outputs of the non-overlapping clock phase generator 316 are connected to a respective first input of a respective multiplexer 312,314. A second input of each of the multiplexers 312,314 is connected to a reference node which may operably be at a ground potential or any other off voltage value that is required to turn-off the corresponding power switches of the switch capacitor power converter 326. The outputs 320, 322 of the multiplexers 312,314 may be connected to the switch capacitor power converter 326. A control input of the multiplexers 312, 314 may be connected to a digital control circuit 308. As will be appreciated, the multiplexers act as a selection circuit which in other examples may be implemented using other logic circuitry or other type of signal selector. The digital control circuit 308 may be connected to a time reference 306. The time reference 306 may generate a signal having a duration of half the nominal switching period. The nominal switching period may be equal to the switching period at which the switch capacitor power converter can provide the maximum output power for which it has been designed.
The output 324 of the switch capacitor power converter 326 may be connected to a first terminal of an output capacitor Co. A second terminal of the output capacitor Co may be connected to a ground potential. The time reference 306 and digital control circuit 308 may be included in a controller 310. The oscillator 304, non-overlapping clock phase generator 316, first and second multiplexers 312, 314 may be included in a clock generator 318.
Figure 5B shows an example timing reference circuit 306. A switch 332 which may typically be implemented by a transistor may be arranged between a ground potential and a non-inverting input of a comparator 336. An inverting input of the comparator 336 may be connected when in operation to a reference voltage for example half the supply voltage value. A current source 334 may be connected to the non-inverting input 338 of the comparator 336. A capacitor C may be connected between the non-inverting input 338 and a ground potential.
The operation of DC-DC converter 300 is described with reference to figure 6A and 6B which have simulation results 400, 400' for an output current of 0.6mA and 6 mA respectively. The y axes 404,404' show the voltage value for the various signals, and the x-axes 424,424' indicate time.
In operation, the comparator 302 may provide a control signal to enable the oscillator 304 in response to the output voltage Vo shown on lines 406,406' being at a level below the reference voltage Vref shown on lines 408,408' . The output of the comparator 302 shown on lines 410,410' may trigger the time reference circuit 306 by closing the switch 332. The time reference circuit 306 is a monostable circuit and generates a pulse of a duration determined by the capacitance C and the value of current provided by the current source 334. The non-overlapping clock phase generator 316 may output a first phase of a non-overlapping clock ph1 shown on lines 416,416' and a second phase of a non-overlapping clock ph2 shown on lines 420,420' The digital control circuit 308 may, in response to the timing reference 306, control the multiplexers 312,314 to output either the non-overlapping clock signals ph1, ph2 or a reference potential which may be a ground potential, or any other off-voltage value that turns off the corresponding power switches in the switch capacitor power converter 326. The signals at the multiplexer outputs 320,322 are non-overlapping clock phases ph1mod shown on lines 418,418' and ph2mod shown on lines 422,422' which may have varying non-overlapping time dependent on the clock frequency. Because the timing reference 306 may have a predetermined duration 428,428' which may be fixed or programmable, at lower switching frequencies which may correspond to lower output current, the non-overlap time 426 between the clocks ph1mod and ph2mod may increase. At higher switching frequencies the non-overlapping time 426' between ph1mod and ph2mod may reduce.
During the non-overlapping time of ph1mod and ph2mod, the NMOS FET switches in the SCPC 308 will be switched off so the capacitors will be in a floating state after a nominal charge/discharge time has passed. It will be appreciated that in other examples, other transistors used, for example PMOS FET switches may be used in which case a supply potential or voltage (or any other required potential) would be required to switch off the PMOS FET switches and so leave the floating capacitors in the SCPC 326 disconnected or isolated from the inputs and outputs of the SCPC 326.
In other examples, the time reference may be connected to the oscillator and the signal derived from the oscillator (or the other way around). Alternatively the timing reference may include an auxiliary oscillator (not shown) coupled to the comparator. Other examples may combine the oscillator and time reference in a single circuit.
Consequently when the output current Io reduces and the switching frequency reduces accordingly, the operation of the SCPC power stage 326 is effectively frozen in the non-overlapping state and so all the floating capacitors in the SCPC are disconnected from both SCPC inputs and outputs and ground potential, as soon as, or shortly after the nominal charge/discharge time has passed.
The DC-DC converter 300 allows a smaller output capacitor Co to be used for a given maximum required output voltage ripple than would otherwise be the case. The DC-DC converter 300 may reduce the amount of output voltage ripple by 50% compared to a conventional DC-DC converter for the same value of output capacitor Co. The improvement in voltage ripple at low output currents is further shown in figures 7a to 7c.
Figure 7a shows the variation of output voltage for two different values of output current 500 for the DC-DC converter 300 and the DC-DC converter 100. The x-axis 502, 502' indicates time in microseconds between a value of approximately 27 us and 28 us i.e. a duration of approximately 1 us. The y- axis 504, 504' each indicate the voltage change in a range between 1.19 volts and 1.23 volts. The graph line 506 shows the variation in output voltage for an output current of 0.6 mA for the DC-DC converter 100. The graph line 508 shows the variation in output voltage ripple for an output current of 0.6 mA for the DC-DC converter 300. The peak to peak voltage ripple for DC-DC converter 300 is approximately 15 mV compared to approximately 27 mV for DC-DC converter 100.
The graph line 510 shows the variation in output voltage for an output current of 6 mA for the DC-DC converter 100. The graph line 512 shows the variation in output voltage for an output current of 6 mA for the DC-DC converter 300. At this higher current level the peak to peak voltage levels in each case are similar.
Figure 7b shows a graph 520 the voltage swing on the floating capacitors in the DC-Converter 100 and the DC-DC Converter 300 for an output current Io of 0.6mA. The x-axis 374 indicates time in microseconds between a value of 25 us and 29 us i.e. a duration of approximately 4 us. The y-axis 522 each indicate the voltage change in a range between 1.1 volts and 1.9 volts. The graph line 526 shows the variation in voltage on the floating capacitors in the SCPC for an output current of 0.6 mA for the DC-DC converter 100. The graph line 528 shows the variation in output voltage floating capacitors in the SCPC for an output current of 0.6 mA for the DC-DC converter 300. The peak to peak voltage on the floating capacitors for DC-DC converter 300 is approximately 0.28 V compared to approximately 0.6 V for DC-DC converter 100.
Figure 7c shows a graph 540 indicating a comparison of output voltage ripple vs output current for the DC-DC converter 100 and DC-DC converter 300. The x-axis 544 indicates the output current between a value of 0 and 6 mA. The y-axis 542 indicates the voltage ripple value between 0 and 35 mV. Line 546 shows that for DC-DC converter 100 the ripple voltage decreases from a value of 32 mV at 0.1 mA output current to approximately 4mV at 6 mA output current. Line 548 shows that for DC-DC converter 300 the ripple voltage decreases from a value of 16 mV at 0.1 mA output current to approximately 4mV at 6 mA output current.
Figure 8 shows a method 600 of operating a DC-DC converter according to an embodiment. In step 602 two non-overlapping clocks may be provided to a switch capacitor power converter having a switchable capacitor. In step 604 a change in the output current drawn from the DC-DC converter, or the input voltage, or the reference setting corresponding to the required output voltage may be detected either directly or indirectly via monitoring the output voltage. In step 606 the non-overlapping time duration of the non-overlapping clocks may be modulated. By modulating the non-overlapping time duration of the non-overlapping clocks in response to changes in output current, the input voltage or the reference setting, the output voltage may be regulated while minimizing the potential increase of the output voltage ripple of the DC-DC converter. Consequently a lower value of output capacitance may be used for the same specification of output voltage ripple.
A DC-DC power converter is described having a power converter input for receiving a supply voltage; a power converter output for outputting a converted supply voltage; a reference input for supplying a reference value; a switch capacitor power converter coupled to the power converter input and the power converter output and comprising at least one switchable capacitor controllable by at least two non-overlapping clock signals; a controller coupled to the switch capacitor power converter, and the power converter output. The controller is configured to generate at least two non-overlapping clock signals and to vary the non-overlapping time duration dependent on the voltage and/or current value of at least one of the power converter output, the reference input, and the power converter input.

Claims

A DC-DC power converter (250) comprising:
a switch capacitor power converter (268) coupled to a power converter input (266), a power converter output (274) and comprising at least one switchable capacitor;

a controller (206) coupled to the switch capacitor power converter (268);

wherein the controller (206) is configured to generate at least two non-overlapping clock signals (260, 272) and to modulate the non-overlapping time duration of the at least two non-overlapping clock signals (260, 272) dependent on the voltage and/or current value of at least one of the power converter output (274), a reference value (276), and the power converter input (266) and further configured to decrease the non-overlapping time duration in response to at least one of an increase in the output current supplied by the DC-DC power converter (250), an increase in the reference value (276), and a decrease in the input voltage (266) of the DC-DC power converter

characterised in that

the controller (206) is coupled to the power converter input (266), the power converter output (274) and a reference input arranged to receive the reference value (276), and wherein the switch capacitor power converter (268) is configured to be controlled by the at least two non-overlapping clock signals (260, 272); and

wherein the controller (330) comprises an error detector (302), a non-overlapping clock generator (318) and a control module (310), wherein the error detector (302) comprises a first input for receiving the reference value, a second input coupled to the power converter output (324) and an output coupled to the non-overlapping clock generator (318) and the control module (310) and wherein the control module (310) is configured to generate a modulation control signal for the non-overlapping clock generator (318) and the non-overlapping clock generator (318) is configured to modulate the clock frequency dependent on the difference between the output voltage (324) and the reference value.
The DC-DC power converter (300) of claim 1 wherein the non-overlapping clock generator (318) comprises a plurality of selectors (312, 314), each selector (312, 314) having a first input coupled to a respective output of a non-overlapping clock phase generator (316), a second input operably coupled to an off-voltage level that is a voltage level that is configured to turn off corresponding power switches in the switch capacitor power converter (326), and a control input coupled to the controller (310) wherein the controller (310) is configured to modulate the non-overlapping time duration by selecting between the first and second inputs in response to a time reference signal.
The DC-DC power converter (300) of claim 2 wherein the controller (310) comprises a timing reference generator (306).
The DC-DC power converter (300) of claim 3 wherein the timing reference generator (306) is configured to generate the time reference signal such that it is equal to half a nominal switching period, wherein the nominal switching period is equal to the switching period at which the switch capacitor power converter can provide maximum output power for which it has been designed.
The DC-DC power converter (300) of claim 3 wherein the timing reference generator (306) generates the time reference signal dependent on at least one of a charge time and a discharge time of the switchable capacitor.
The DC-DC power converter (300) of any preceding claim wherein the controller (310) is configured to be operated to increase the non-overlapping time duration in response to at least one of a decrease in output current supplied by the DC-DC power converter (300), a decrease in the reference value, and an increase in the input voltage of the DC-DC power converter (300).
The DC-DC power converter of any preceding claim further comprising an output capacitor coupled to the output of the switch capacitor power converter.
The DC-DC power converter of claim 7 when dependent on claims 3 to 5 wherein the timing reference generator (306) is coupled to an oscillator.
A method of controlling a DC-DC power converter (250) comprising a switch capacitor power converter (268) having at least one switchable capacitor, the method comprising:
providing at least two non-overlapping clock signals (260, 272) to the switch capacitor power converter (268), and modulating the non-overlapping time duration of the non-overlapping clock signals (260, 272) in dependence on the voltage and/or the current value of at least one of the power converter output (274), the power converter input (266) and a reference value (276), and decreasing the non-overlapping time duration in response to at least one of an increase of the output current provided by the DC-DC power converter (250), an increase in the reference value (276), and a decrease of the input voltage (266) of the DC-DC power converter;

controlling the switch capacitor power converter (268) by the at least two non-overlapping clock signals (260, 272); and

modulating the clock frequency dependent on the difference between the output voltage (324) and the reference value.
The method of claim 9 further comprising increasing the non-overlapping time duration in response to at least one of a decrease in the output current provided by the DC-DC power converter, a decrease in the reference value, and an increase of the input voltage of the DC-DC power converter.