KR100831746B1 - Multi-phase converter with improved load step-up transient response - Google Patents

Abstract

According to the present invention, the following multi-phase converter is provided. A plurality of switching circuits each providing a switched voltage to an output node of the converter, wherein each switching circuit sequentially provides a switched output voltage to the output node from which the output voltage of the converter is generated; A clock circuit for providing a plurality of clock signals of different phases to the switching circuits to determine when each switching circuit should provide the switched voltage to the output node; Each switching circuit comprises a first and a second switch connected in series connected to both ends of the DC voltage bus; Comparing a second signal including a ramp signal with a first signal proportional to a difference between an output voltage at the output node of the converter and a first reference voltage, and controlling on times of switches of a connected switching circuit; Further comprising a first circuit for producing a pulse width modulated signal; Comparing the first signal proportional to the difference between the output voltage and the first reference voltage with a second reference voltage, and when the first signal exceeds the second reference voltage by a predetermined amount, And a second circuit for turning on at least one of said switching circuits for providing to said output node prior to generation of said clock signal.

 Multi-Phase Converter, Buck Converter, Transient Response

Description

MULTI-PHASE CONVERTER WITH IMPROVED LOAD STEP-UP TRANSIENT RESPONSE}

The invention will be described in detail with reference to the accompanying drawings in the following detailed description.

Figure 1 shows a six-phase multi-phase converter to which the present invention can be applied.

Figure 2 shows the multi-phase converter of Figure 1 in detail, showing only two phases in detail.

3 shows the waveform of FIG. 2 for four phases.

5 shows a block diagram of one phase control circuit for controlling a buck converter output stage, in accordance with an embodiment of the present invention.

FIG. 6 shows the waveform of the circuit shown in FIG.

Figure 7 shows how the circuit responds to step-up load transients.

FIELD OF THE INVENTION The present invention relates to DC to DC converters, and more particularly to multi-phase converters capable of producing a DC output voltage at a common output of a plurality of coupled switching power supplies. For example a plurality of buck converters.

Multi-phase converters have been known. For example, in a typical multi-phase converter, such as a multi-phase buck converter, a plurality of buck converters are provided, each having output inductors coupled to the output node. In a typical application, each buck converter is controlled by a control circuit, and in different phases can operate so that the control switch of each buck converter switching stage is turned on at different times. In this way, each phase sequentially provides power to the load, reducing ripple and reducing the size of the output capacitance.

An exemplary six-phase multiphase converter is shown in Figure 1, which employs an IR 3500 control integrated circuit 10, and is six-phase, so six IR3505 phase integrated circuits controlled by the control integrated circuit. 30 is adopted. Each phase integrated circuit 30 is ideally equipped with an output connected to each buck converter, each buck converter located above and serving as a control switch, below which a synchronous switch and It comprises a switch (Q2) that serves the same role.

The switch nodes V _s 1 to V _s 6 for each phase are connected from the output inductor L1 to the output inductor L6 for each phase, and the output inductors L1 to L6 are connected to the common node VC. It is connected to the output node VOUT through the distribution impedance. The output capacitor, COUT, is coupled to the output to filter the switched output voltage.

In a typical multi-phase converter, each control switch Q1 is turned on to provide an output current, which charges the output inductor at a predetermined time determined by a clock pulse (which may be provided by the control integrated circuit). To supply current. Thus, the control switch will only turn on when a clock pulse occurs. Clock pulses for each phase integrated circuit (named PHSIN) are shown in FIG. As shown in Fig. 3, the PHSIN signals (integrated circuit 1 PHSIN, integrated circuit 2 PHSIN, integrated circuit 3 PHSIN, integrated circuit 4 PHSIN) are each turned on to turn on the respective phase control switches Q1 that are out of phase with each other. Delay. The turn on of the synchronous switches Q2 is similarly delayed but turned on in a manner complementary to the control switches.

Although only two phase integrated circuits 30 are shown, referring to FIG. 2, which shows the circuit of FIG. 1 in more detail, a clock pulse is supplied at CLKOUT from the control integrated circuit 10. FIG. 4A and 2, when a clock pulse occurs, a ramp signal PWMRMP is started, which can be seen at the non-inverting input of the PWM comparator 45 of FIG. Referring to Fig. 4C, it also turns on control switch Q1, which PWMRMP is shown in waveform B of Fig.4. The base level of the PWMRMP signal is the signal VDAC, and the VDAC signal is provided by the control integrated circuit 10 based on the reference voltage level set by the VID signals from VID0 to VID7 (see FIG. 1). ). When the PWMRMP signal is equal to the output of the error amplifier 20 in the control chip 10, where the error amplifier compares FB, which is the feedback from the output voltage of the converter, and VDAC, which is the reference voltage, as shown in FIG. Q1, the control switch (or switch located above), is turned off, and Q2, the synchronous switch (or switch located below), is turned on. Referring to waveforms C and D of Fig. 4, as shown, the control switch (or upper switch) Q1 is turned on when a clock pulse occurs, and the control switch Q1 is turned on when the ramp voltage is equal to the output of the error amplifier. Is off. This is illustrated in waveform B of FIG. 4 for the error amplifier signal range. As shown, when the output of the error amplifier increases due to the load step-up shown in I of waveform B of FIG. 4, the control switch Q1 is turned on only when a clock pulse occurs, and the PWM ramp voltage is It is turned off only when it reaches EAIN, which is the output of the error amplifier. As shown in Figure 4, the increased output of the error amplifier results in an increase in the duty cycle of Q1. Therefore, the duty cycle follows the error amplifier signal, and the duty cycle also decreases once the output of the error amplifier decreases, for example due to a decrease in load, as shown in waveform C of FIG.

Thus, as can be understood from the above, the control switch is turned on only when a clock pulse occurs. Thus, there is a delay until a clock pulse occurs before the converter responds to a load transient. Thus, for example, if a load transient occurs before a clock pulse, such as a dashed line in waveform B of FIG. 4, the converter cannot respond by turning on the control switch until a clock pulse occurs.

This can be further exacerbated in the following situations: a very large load transient occurs and the turn-on of the next phase control switch Q1 is not adequate to solve the requirements caused by the load transient. .

Thus, it is possible to provide an instant response to load transients and provide a multi-phase converter that does not need to wait for a clock pulse to turn on at least one or more converter control switches, and preferably all phase control switches. It is desirable to have.

It is therefore an object of the present invention to provide a multi-phase converter that can provide fast response to increased load transients.

Related application

This application is based on and claims priority of "IR3550 / 3505 CHIP" (Provisional Application No. 60 / 717,841), which was provisionally filed in the United States of 16 September 2005. The entire contents of these provisional applications are incorporated herein by reference.

FIELD OF THE INVENTION The present invention relates to DC to DC converters, and more particularly to multi-phase converters capable of producing a DC output voltage at a common output of a plurality of coupled switching power supplies. For example a plurality of buck converters.

According to the invention, there is provided a multi-phase converter in which at least one control switch and preferably all control switches of the multi-phase converter are turned on in response to the occurrence of an increased load transient, without waiting for a system clock pulse to be generated. do.

According to the present invention, a plurality of switching circuits respectively providing a switched voltage to an output node of a converter, wherein each switching circuit sequentially provides a switched output voltage to the output node where the output voltage of the converter is generated. and; A clock circuit for providing a plurality of clock signals of different phases to the switching circuits to determine when each switching circuit should provide the switched voltage to the output node; Each switching circuit comprises a first and a second switch connected in series connected to both ends of the DC voltage bus; Comparing a second signal including a ramp signal with a first signal proportional to a difference between an output voltage at the output node of the converter and a first reference voltage, and controlling on times of switches of a connected switching circuit; Further comprising a first circuit for producing a pulse width modulated signal; Comparing the first signal proportional to the difference between the output voltage and the first reference voltage with a second reference voltage, and when the first signal exceeds the second reference voltage by a predetermined amount, And a second circuit for turning on at least one of said switching circuits for providing to said output node prior to generation of said clock signal.

Other objects, features and advantages of the invention will be apparent from the following detailed description.

1 and 2 show a multi-phase converter to which the present invention can be applied. FIG. 2 shows the circuit of FIG. 1 in more detail, showing only two identical phase integrated circuits 30 in detail. Each integrated circuit 30 controls a buck converter comprising two transistors Q1 and Q2 and an output inductor L _N. Transistor Q1 is a control switch, and transistor Q2 is a synchronous switch. Although the use of a synchronous switch provides greater efficiency, the synchronous switch can be replaced by a diode as is known to those skilled in the art.

Although FIGS. 1 and 2 show separate control integrated circuits 10 and phase integrated circuits 30, the circuit may be, for example, a single integrated circuit or an individual circuit or any number of integrated circuits (eg, all Phases correspond to one integrated circuit).

As shown in FIG. 2, the control integrated circuit 10 provides a clock signal CLKOUT to an input CLKIN of each of the phase integrated circuits as shown in FIG. 3. Dotted lines 15 in FIG. 2 show that additional phases or phase integrated circuits may be used depending on the load requirements, in which case signal lines 16 will be added to the additional phase integrated circuits.

As shown in FIGS. 2 and 3, a clock signal CLKIN is provided to each phase integrated circuit 30. In addition, a reduced frequency signal PSHIN is provided to the first phase integrated circuit, which is a clock signal that sets the PWM frequency of the phase integrated circuit. The first phase integrated circuit provides a signal (PHSOUT) provided to the input of the subsequent phase integrated circuit, which provides a delayed clock signal (PHSIN) to the subsequent phase integrated circuit. This is shown in more detail in the six-phase converter of FIG. 1. Figure 3 shows how out of phase clock signals PHSIN are provided to each phase integrated circuit in order to control respective on times of the control switch and the synchronous switch of each of the buck converters. Shows. FIG. 3 illustrates sequentially delayed clock signals PHSIN for each of the four integrated circuits of the phase integrated circuits 1 to 4. As can be seen in FIG. 3, each of the clock signals PHSIN for each phase integrated circuit is sequentially delayed to provide timing control that is out of phase, which means that the respective switches Q1 and This is to turn on Q2).

As noted above, FIG. 4 shows gate output signals for PHSIN, exemplary PWM ramp, error amplifier (EAIN) signals, and control and sync (SYNC) switches, which are phase integrated circuit clock pulses for a single phase. .

As mentioned above, if a step-up load transient occurs before a clock pulse (see I in waveform B of Figure 4), a problem arises in that the converter must wait until the clock pulse before responding to the transient. . This delay can cause an undesirable decrease in output voltage.

According to the present invention, to solve this problem, a circuit for determining whether the error amplifier voltage is greater than the reference voltage by a predetermined amount is used. If the error amplifier output voltage exceeds the reference voltage by a prescribed amount, the gate signal for the control switch is turned on immediately, and the gate signal for the synchronous switch is turned off. This is done for a single phase, but preferably the control switches for all phases are turned on simultaneously to provide an instant burst of power that meets the load requirements.

2, 5 and 6, in normal operation, the output voltage VOUT is monitored by the error amplifier 20 (see FIG. 2). The error amplifier 20, shown as being in the control integrated circuit 10, receives a signal FB from the remote sense amplifier 32, which senses the output voltage across the terminals VOSENSE + and VOSENSE−. Generate the output (V _O ). This output V _O (FIG. 2) is provided to the inverting input of error amplifier 20 via voltage divider circuit 35. The non-inverting input of the error amplifier 20 is provided with a signal VDAC, which is provided at the input VSEPT. This sets the desired converter output voltage. The VDAC signal is itself the output of the digital-to-analog converter in the control chip 10 which receives the digital inputs VID0 to VID7 from the microprocessor to set the output voltage. The error amplifier output EAOUT represents the deviation of the output voltage from the reference VDAC. This error amplifier signal, shown as EAIN at the input of the phase integrated circuits 30, starts as shown in FIG. 4 when the clock pulse PHSIN is generated by the PWM comparator 45 in each phase integrated circuit. It is compared with the ramp voltage PWM RMP. When the clock signal is generated, the PWM latch 70 is set to turn on the control switch Q1. Synchronous switch Q2 is turned off before control switch Q1 is turned on to avoid shoot-through. Once the ramp voltage matches the error amplifier voltage, the PWM comparator 45 output resets the PWM latch 70 to turn off the control switch Q1 and the sync switch Q2 after a slight time delay. Turn on to prevent the shoot-through again.

6 shows the operation of the circuit of FIG. 5 showing the circuit of FIG. 2 in more detail. Also within each phase integrated circuit 30 is a current sense amplifier 62, which monitors the current in the output inductor for that phase. The output of the current sense amplifier 62 is added to the voltage VDAC (DAC IN) at the summing stage 40 and compared with the average current signal ISHARE at the share adjust amplifier 60. The output of the sharing control amplifier 60 adjusts the charge rate of the charging capacitor C _c to adjust the sharing of the phases of the overall output current. For example, if the current sensed in a particular phase is higher than the average (ISHARE), the PWM ramp generator 80 adjusts the PWM ramp to reduce the current in that phase to be closer to the average. do. This is done in each phase integrated circuit so that each phase with respect to the load bears the entire current supply evenly.

As shown in FIG. 6, the circuit's response to overvoltage at the output voltage (Over Voltage Protection (OVP)) is shown where a fault in the control integrated circuit occurs when the output voltage exceeds the OVP threshold. A latch latch is activated to prevent control switch Q1 from turning on for the next clock pulse, resulting in a decrease in error amplifying output EAIN in the phase integrated circuits to reduce the output voltage.

7 shows the response of the circuit to stepped-up load transients. When a stepped rise load transient occurs, the error amplifier output voltage increases because the converter output voltage decreases. If the output voltage EAIN of the error amplifier 20 exceeds a predefined amount (e.g., 1.3 volts or more than the reference voltage VDAC ¹ as shown in Fig. 7), the comparator 50 (the comparator is illustratively voltage VDAC). It has a reference voltage 55 that is 1.3 volts higher than ¹ , which in turn is set by sharing control amplifier 60 via addition stage 65. The output sets PWM latch 70 high. Note that VDAC ¹ is a modified form of VDAC. This is because it is regulated by the output of shared control amplifier 60. Without shared control amplifier 60, VDAC and VDAC ¹ are the same. The setting of the PWM latch adjusts the output gate H (gate of the control switch Q1) high through the gate 75 and the driver 80. Shortly before this time, the complementary output of the PWM latch 70 resets the PWM ramp generator 80 and through the gates 90, 95, 100 and the gate driver 105 the synchronous switch Q2. Turn off).

This is shown in FIG. 7, where the gate signal (gate H) to the control switch is turned on in III before the clock signal pulse in IV. As shown in Fig. 7, once the clock signal is generated, the PWM ramp restarts as shown in V and turns on the control switch as shown in VI.

According to the invention, in order to prevent the upper switch Q1 from conducting too long, the PWM ramp slope is increased (e.g. doubled) during this mode of operation. This is seen by the increased slope in Fig. 7. Once the PWM ramp signal rises above the error amplifier output, phase integrated circuit 30 exits from this mode.

While the present invention has been described with respect to specific embodiments, many other variations, modifications, and other uses will be apparent to those of ordinary skill in the art. Accordingly, the invention is not to be limited by the specific disclosure herein, but should only be limited by the appended claims.

According to the present invention, there is provided a multi-phase converter capable of an immediate response to load transients and not having to wait for a clock pulse to turn on at least one or more converter control switches and preferably all phase control switches. can do.

Claims (10)

In a multi-phase converter, A plurality of switching circuits each providing a switched voltage to an output node of the converter, wherein each switching circuit sequentially provides a switched output voltage to the output node from which the output voltage of the converter is generated; A clock circuit for providing a plurality of clock signals of different phases to the switching circuits to determine when each switching circuit should provide the switched voltage to the output node; Each switching circuit comprises a first and a second switch connected in series connected to both ends of the DC voltage bus; Comparing a second signal including a ramp signal with a first signal proportional to a difference between an output voltage at the output node of the converter and a first reference voltage, and controlling on times of switches of a connected switching circuit; Further comprising a first circuit for producing a pulse width modulated signal; A first output voltage that is proportional to a difference between the output voltage and the first reference voltage and a second reference voltage, and when the first signal exceeds the second reference voltage by a predetermined amount, a switched output voltage A second circuit for turning on at least one of said switching circuits to provide said output node with said output node prior to generation of said clock signal; Multi-phase converter characterized in that it further comprises. The method of claim 1, Each switching circuit, A control switch and a synchronous switch, wherein the control switch and the synchronous switch are connected in series with a switching node at a common contact therebetween, And said control switch of at least one of said switching circuits is turned on in response to said first signal exceeding said second reference voltage by a predetermined amount. The method of claim 2, The control switches of the at least two or more switching circuits, And turn on in response to the first signal exceeding the second reference voltage by a predetermined amount. The method of claim 3, wherein The control switch of the respective switching circuits, And turn on in response to the first signal exceeding the second reference voltage by a predetermined amount. The method of claim 1, wherein the second circuit A multiphase converter comprising a comparator circuit. The method of claim 1, The second reference voltage is regulated by the output of the current divider circuit, which adjusts the first reference voltage to generate a second reference voltage in response to the output current provided by the switching circuit. Multi-phase converter for equalizing the output currents provided by the circuits. The method of claim 1, The ramp signal has a first slope and the first slope increases when the first signal exceeds the second reference voltage by a predetermined amount. The method of claim 7, wherein And said increased first slope is twice the first slope. 2. The multiple phase converter of claim 1, wherein the first and second reference voltages are identical. The method of claim 2, Each switching circuit, And a buck converter having an output inductor connecting the switching node and the output node of the converter.

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