JP2022154921A - switching power supply circuit - Google Patents

Abstract

To provide a switching power supply circuit capable of suppressing a peak current.SOLUTION: A switching power supply circuit comprises: a controller that outputs a plurality of PWM signals; and a plurality of converters connected in parallel with an output path, each performing switching according to a corresponding PWM signal among the plurality of PWM signals. Each of the plurality of converters has: a high-side arm; a low-side arm connected in series with the high-side arm; and an inductor connected between a connection point between the high-side arm and the low-side arm, and the output path. The controller stops outputting any one PWM signal among the plurality of PWM signals when a voltage drop amount of the output path becomes equal to or more than a predetermined value. Each of the plurality of converters, when the outputting of the corresponding PWM signal is stopped, stops PWM outputting to a gate of the high-side arm and stops outputting to the output path.SELECTED DRAWING: Figure 8

Description

The present disclosure relates to switching power supply circuits.

A multiphase DC-DC converter that drives a plurality of converter units connected in parallel to an output path is known (see, for example, Patent Document 1).

Japanese Patent Application Laid-Open No. 2006-204002

In a switching power supply circuit including a plurality of converters connected in parallel to an output path, the sum of currents output from each of the plurality of converters is supplied to a load connected to the output path. Therefore, when the load current changes abruptly, an excessive peak current may temporarily flow through some converters.

The present disclosure provides a switching power supply circuit capable of suppressing peak current.

This disclosure is
a controller that outputs a plurality of PWM signals;
a plurality of converters connected in parallel to an output path and switching according to corresponding PWM signals among the plurality of PWM signals;
Each of the plurality of converters is connected between a high side arm, a low side arm connected in series with the high side arm, a connection point between the high side arm and the low side arm, and the output path. and an inductor
the controller stops outputting any one of the plurality of PWM signals when the amount of voltage drop in the output path reaches or exceeds a predetermined value;
Each of the plurality of converters provides a switching power supply circuit that stops PWM output to the gate of the high side arm and stops output to the output path when the output of the corresponding PWM signal stops.

According to the present disclosure, peak current can be suppressed.

1 is a diagram illustrating a configuration example of a switching power supply circuit according to an embodiment; FIG. 4 is a timing chart showing an operation example of the switching power supply circuit according to one embodiment; It is a figure which shows the structural example of a converter. FIG. 5 is a diagram showing an example of droop characteristics; 1 is a diagram showing a specific example of a switching power supply circuit according to one embodiment; FIG. FIG. 4 is a diagram illustrating the state of each signal within the controller; FIG. 4 is a diagram illustrating the state of each signal within the converter; 1 is a diagram showing a specific example of a switching power supply circuit according to one embodiment; FIG. FIG. 5 is a diagram showing peak currents according to a comparative example; FIG. 4 is a diagram showing peak current according to one embodiment;

Embodiments will be described below.

FIG. 1 is a diagram illustrating a configuration example of a switching power supply circuit according to one embodiment. The switching power supply circuit 101 shown in FIG. 1 generates DC power with an output voltage Vout and supplies it to the load 60 . The switching power supply circuit 101 is provided, for example, in an electronic device 201 having a load 60 . The switching power supply circuit 101 may be built in the electronic device 201 or may be externally attached.

Electronic device 201 includes load 60 and switching power supply circuit 101 . Specific examples of the electronic device 201 include supercomputers, servers, personal computers, mobile terminal devices, and the like, but the electronic device 201 is not limited to these devices.

The load 60 operates using the DC output voltage Vout generated by the switching power supply circuit 101 as a power supply voltage. Load 60 may be a single device or a circuit block containing multiple devices. FIG. 1 illustrates a case where the load 60 is a CPU (Central Processing Unit).

The switching power supply circuit 101 includes a controller 70 that outputs a plurality of PWM (Pulse Width Modulation) signals, and a plurality of converters 51 to 54 that supply power of an output voltage Vout to a load 60 . Each of the plurality of converters 51 to 54 has a switching circuit that performs switching according to a corresponding PWM signal out of a plurality of PWM signals, an inductor to which the output of the switching circuit is input, and one end connected to the output side of the inductor. and a capacitor.

The converter 51 includes a switching circuit 11 that performs switching according to a PWM signal (PWM1) corresponding to a plurality of PWM signals, an inductor 21 to which the output of the switching circuit 11 is input, and a capacitor whose one end is connected to the output side of the inductor 21. 61. The converter 52 includes a switching circuit 12 that switches according to a corresponding PWM signal (PWM2) among a plurality of PWM signals, an inductor 22 to which the output of the switching circuit 12 is input, and a capacitor whose one end is connected to the output side of the inductor 22. 62. The converter 53 includes a switching circuit 13 that performs switching according to a corresponding PWM signal (PWM3) among a plurality of PWM signals, an inductor 23 to which the output of the switching circuit 13 is input, and a capacitor whose one end is connected to the output side of the inductor 23. 63. The converter 54 includes a switching circuit 14 that performs switching according to a PWM signal (PWM4) corresponding to a plurality of PWM signals, an inductor 24 to which the output of the switching circuit 14 is input, and a capacitor whose one end is connected to the output side of the inductor 24. 64.

Capacitors 61-64 are capacitive elements each having one end connected to the output side of the corresponding inductor among inductors 21-24 and the other end connected to low power supply potential GND such as ground.

Converters 51 - 54 are connected in parallel to common output path 31 . An output voltage Vout is generated in an output path 31 in which the output ends of inductors 21-24 are connected to each other. Output voltage Vout is smoothed by capacitor 30 . The capacitor 30 has one end connected to the output path 31 and the other end connected to the low power supply potential GND. Capacitors 61-64 may be omitted if capacitor 30 is present.

Switching power supply circuit 101 includes a plurality of converters 51 to 54 connected in parallel to output path 31 . The switching power supply circuit 101 is, for example, a multiphase converter capable of suppressing ripples in the output voltage Vout by performing control to shift the output phases of the plurality of converters 51 to 54 with respect to each other. The switching circuits 11 to 14 of the plurality of converters 51 to 54 feed back operation information of each phase such as output current, output voltage, temperature, presence/absence of abnormality, etc. to the controller 70 .

The controller 70 is, for example, a digital power supply controller connected to PMBUS (Power Management Bus) and SVID (Serial Voltage Identification). The controller 70 may be, for example, a control device including a processor such as a CPU (Central Processing Unit) and a memory. The functions of the controller 70 may be implemented by the processor operating according to a program readable and stored in the memory. The functions of the controller 70 may be realized by FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit).

FIG. 2 is a timing chart showing an operation example of the switching power supply circuit according to one embodiment. As shown in FIG. 2, the controller 70 sequentially operates the switching circuits 11 to 14 in one operation cycle (=1/Fsw) so that the output phases of the converters 51 to 54 are shifted from each other (multiphase operation). . Fsw represents a switching frequency in which one cycle is from the operation of converter 51 (switching circuit 11) to the operation of converter 54 (switching circuit 14). The ripple period of the output voltage Vout is 1/(Fsw×4) in the case of four phases.

Switching power supply circuit 101 shown in FIG. 1 supplies load 60 connected to output path 31 with output current Iout, which is the sum of the currents output from each of a plurality of converters 51-54. However, when a plurality of converters 51 to 55 connected in parallel to output path 31 operate (especially when controlled by multiphase operation), if the current of load 60 changes sharply, a temporary excessive peak Current may flow in some converters. Depending on the timing at which the current of the load 60 abruptly changes and the individual difference of each converter, some converters follow the abrupt change by feedback control, and a steep peak current instantaneously flows through the part of the converters. It is from. An excessive peak current can be one of the factors that cause deterioration and failure of the converter, so it is preferable to suppress the magnitude of the peak current.

A switching power supply circuit 101 according to an embodiment of the present disclosure has a configuration for suppressing this peak current. Next, a configuration example of the switching power supply circuit 101 will be described in more detail.

FIG. 3 is a diagram showing a configuration example of a converter. The converter 51 shown in FIG. 3 is the first phase converter among the plurality of converters. The converters 52 , 53 , 54 of other phases have the same configuration as the converter 51 , so the description of the converters 52 , 53 , 54 is omitted by citing the description of the converter 51 .

The converter 51 is a DC-DC converter (DC: Direct Current) that steps down the input voltage Vin to the output voltage Vout. The input voltage Vin is a DC voltage input between the high power supply potential section 84 and the low power supply potential section GND, and corresponds to the potential difference between the high power supply potential section 84 and the low power supply potential section GND.

The controller 70 detects the voltage (output voltage Vout) of the output path 31 and obtains the detected output voltage Vout as the detection voltage Vs. The controller 70 preferably detects the output voltage Vout by remote sensing in order to ensure detection accuracy of the output voltage Vout. The controller 70 has a signal generator 71 that generates a plurality of PWM signals (only PWM1 is explicitly shown in FIG. 3). The signal generator 71 is an example of a PWM signal generator.

The signal generator 71 determines the pulse width or duty ratio of each of the plurality of PWM signals (PWM1 to PWM4) that converges the deviation D to zero according to the deviation D between the detected voltage Vs and the reference voltage Vcm. The duty ratio represents the ratio of high level time (pulse width) to one cycle of the PWM signal. The signal generator 71 outputs a plurality of PWM signals with the determined pulse width or duty ratio.

The switching circuit 11 has a structure (also referred to as a leg) in which a high-side transistor 15 and a low-side transistor 16 are connected in series, and drivers 17 and 18 for switching the transistors 15 and 16 .

Transistor 15 has a drain connected to high power supply potential section 84 , a source connected to the drain of transistor 16 , and a gate connected to high side driver 17 . The transistor 15 is an example of a high side arm, and is a semiconductor switching element provided on the high power supply potential section 84 side with respect to the connection point 19 . Transistor 16 has a source connected to low power supply potential GND, a drain connected to the source of transistor 15 , and a gate connected to low side driver 18 . The transistor 16 is an example of a low side arm, and is a semiconductor switching element provided on the low power supply potential GND side with respect to the connection point 19 . The transistors 15 and 16 are, for example, N-channel MOSFETs (Metal Oxide Semiconductor Field Effect Transistors).

A junction 19 where the source of transistor 15 and the drain of transistor 16 are connected is an intermediate point between transistors 15 and 16 . The connection point 19 is connected to one end of the inductor 21 . The other end of the inductor 21 is connected to one end of the capacitor 61 and the power input portion of the load 60 .

The drivers 17 and 18 complementarily turn on or off the high-side transistor 15 and the low-side transistor 16 according to the PWM signal (PWM1) output from the controller 70 . The high side driver 17 is a drive circuit that outputs a PWM drive signal to the gate of the transistor 15 according to the PWM signal (PWM1), and switches the gate voltage HSG of the transistor 15 between high level and low level. The low-side driver 18 is a drive circuit that outputs a PWM drive signal to the gate of the transistor 16 according to the PWM signal (PWM1), and switches the gate voltage LSG of the transistor 16 between low level and high level.

The converter 51 includes a bootstrap circuit 80 to secure a gate voltage HSG that turns on the high-side transistor 15 (specifically, an N-channel MOSFET). The bootstrap circuit 80 is a circuit that makes the gate voltage HSG of the transistor 15 higher than the input voltage Vin. The bootstrap circuit 80 has, for example, a bootstrap capacitor 81 and a bootstrap diode 82 . The bootstrap capacitor 81 is a capacitive element having one end connected to the connection point 19 and the other end connected to the driving power supply section of the high side driver 17 . The bootstrap diode 82 is a rectifying element whose anode is connected to the power supply 83 and whose cathode is connected to the other end of the bootstrap capacitor 81 and the drive power supply section of the high side driver 17 . A power supply 83 generates a DC voltage Vcc that is lower than the input voltage Vin.

Transistor 16 is turned on by low side driver 18 according to PWM1, and transistor 15 is turned on by high side driver 17 according to PWM1. As a result, the potential of the connection point 19 becomes GND (the voltage Vsw of the connection point 19 becomes substantially zero volts). The bootstrap capacitor 81 is charged by the voltage Vcc of the power supply 83 through the bootstrap diode 82, and the voltage of the bootstrap diode 82 (bootstrap voltage Vbst) is charged up to the DC voltage Vcc. Next, transistor 16 is turned off by low side driver 18 according to PWM1, and transistor 15 is turned on by high side driver 17 according to PWM1. As a result, the bootstrap capacitor 81 is discharged and the gate voltage HSG is boosted to (Vin+Vbst). Therefore, a gate voltage HSG equal to or higher than the threshold voltage of the transistor 15 can be secured.

The voltage for charging the bootstrap capacitor 81 may be the input voltage Vin higher than the DC voltage Vcc, instead of the DC voltage Vcc, as long as the conditions such as the gate withstand voltage of the transistor 15 are satisfied.

The switching power supply circuit 101 according to an embodiment of the present disclosure uses the bootstrap circuit 80 to suppress the temporarily excessive peak current. The switching power supply circuit 101 operates the bootstrap circuit 80 before the current (output current Iout) output to the load 60 via the output path 31 exceeds a predetermined limit value, at an operation cycle (1/Fsw). Turn off (skip) by unit. By turning off (skipping) the operation of the bootstrap circuit 80, the high-side transistor 15 cannot be turned on during the skip period. This can temporarily stop the flow of current from the transistor 15 to the load 60 . The period to be skipped may be a period of one operating cycle, or may be a continuous period of integer multiples of one operating cycle. In this manner, switching power supply circuit 101 skips the operation of bootstrap circuit 80 in units of operation cycles (1/Fsw), thereby temporarily reducing excessive current flowing through some of converters 51 to 54. Peak can be suppressed.

The switching power supply circuit 101 has, for example, a droop characteristic in which the voltage of the output path 31 (output voltage Vout) decreases as the output current Iout flowing in the output path 31 increases, as a trigger for skipping the bootstrap circuit 80. use.

FIG. 4 is a diagram showing an example of droop characteristics. The droop characteristic is a characteristic in which as the output current Iout flowing through the output path 31 increases, the amount of drop in the output voltage Vout also increases proportionally. This characteristic appears because the output path 31 has a resistance (also called "droop resistance"). For example, the droop resistance Rd is 1.8 [mΩ], the voltage value V0 of the reference voltage Vcm at the output point where the currents output from the plurality of converters 51 to 54 finally join is 1 [V], and the Assume that the current value I1 of the output current Iout flowing from the output point to the output path 31 is 60 [A]. At this time, the droop voltage generated in the droop resistor Rd (the amount of voltage drop ΔV in the output path 31) is 108 [mV], and the voltage value of the output voltage Vout drops to 0.892 [V].

The droop voltage is proportional to the current flowing. Utilizing this characteristic, the controller 70 stops outputting any one of the plurality of PWM signals (PWM1 to PWM4) when a droop voltage (amount of drop ΔV) equal to or higher than a predetermined value Va is detected. The predetermined value Va corresponds to the current value I1 of the output current Iout in the case of FIG. The PWM signal whose output is stopped may be a part of the PWM signals or all of the PWM signals. When each of the plurality of converters 51 to 54 detects that the output of the PWM signal supplied thereto has stopped, the bootstrap circuit 80 prevents the gate voltage HSG of the high-side transistor 15 from becoming higher than the input voltage Vin. do. As a result, the transistor 15 in any one of the converters 51 to 54 is not turned on, so that the peak of the output current Iout can be suppressed.

In this way, each of the plurality of converters 51 to 54 stops the operation of its own bootstrap circuit 80 when the output of the PWM signal corresponding to itself stops. Output (specifically, PWM drive signal) is stopped. As a result, the current output to the output path 31 is stopped, so that a temporary excessive peak current can be suppressed.

For example, when the amount of voltage drop ΔV in the output path 31 reaches or exceeds a predetermined value Va, the controller 70 stops outputting one of the PWM signals (for example, PWM1). Then, when the amount of descent ΔV becomes less than the predetermined value Va, the controller 70 resumes the output of the PWM signal that has been stopped. Each of the plurality of converters 51 to 54 resumes PWM output to the gate of its own transistor 15 when the output of the PWM signal corresponding thereto resumes. As a result, the current output to the output path 31 is resumed, so that the converter whose output has been stopped can quickly recover from the temporary output stop state.

FIG. 5 is a diagram showing a specific example of a switching power supply circuit according to one embodiment. The controller 70 has a signal generator 71 that generates a plurality of PWM signals each having a pulse width and a duty ratio that converge the deviation D between the reference voltage Vcm and the detected voltage Vs to zero. The signal generation section 71 has a voltage detection circuit 72 , an integration circuit 73 , a PWM modulator 74 and an overcurrent protection setting section 75 .

The voltage detection circuit 72 amplifies the monitored value of the output voltage Vout to generate the detection voltage Vs. The integration circuit 73 adjusts the set value that determines the droop characteristic. The PWM modulator 74 generates a plurality of PWM signals each having a pulse width and a duty ratio that converge the deviation D to zero according to the deviation D between the reference voltage Vcm and the detected voltage Vs.

Controller 70 has an overcurrent protection setting unit 75 for each of converters 51-54. FIG. 5 shows overcurrent protection setting 75 for converter 51 . When the voltage difference obtained by subtracting the detection voltage Vs from the reference voltage Vcm (corresponding to the amount of drop ΔV) reaches or exceeds a predetermined value Va, the overcurrent protection setting unit 75 outputs a PWM signal (PWM1 in the case of FIG. 5) corresponding to itself. Stop output. On the other hand, when the drop amount ΔV becomes less than the predetermined value Va, the overcurrent protection setting unit 75 resumes outputting the PWM signal corresponding to itself.

For example, the overcurrent protection setting unit 75 has a logic circuit 75a that calculates a logical product. A PWM signal generated by the PWM modulator 74 is input to the logic circuit 75a. As shown in FIG. 6, when the overcurrent protection setting unit 75 detects that the amount of drop ΔV is equal to or greater than a predetermined value Va, the logic circuit 75a sets the level of the PWM signal to low level (GND in this example). On the other hand, when the overcurrent protection setting unit 75 detects that the drop amount ΔV is less than the predetermined value Va, the logic circuit 75a sets the level of the PWM signal to high level (in this case, the same voltage as the bootstrap voltage Vbst).

In FIG. 5, for example, the high-side driver 17 has a logic circuit 17a for calculating AND, and the low-side driver 18 has an inverter 18a for inverting the level of PWM1. Logic circuit 17 a compares the level of PWM 1 with the level of voltage Vbst of bootstrap capacitor 81 .

As shown in FIG. 7, when the level of PWM1 is high (in this case, the same voltage as bootstrap voltage Vbst), the output level of logic circuit 17a is high (same voltage as bootstrap voltage Vbst). As a result, the high-side driver 17 boosts the gate voltage HSG to (Vin+Vbst) and turns on the transistor 15 . On the other hand, when PWM1 is at high level, the output level of inverter 18a is at low level (GND). As a result, the low-side driver 18 sets the gate voltage LSG to low level to turn off the transistor 16 .

On the other hand, as shown in FIG. 7, when the level of PWM1 is low level (GND in this case), the output level of logic circuit 17a is low level. As a result, the high-side driver 17 sets the gate voltage HSG to low level to turn off the transistor 15 . On the other hand, when PWM1 is at low level, the output level of inverter 18a is at high level. This causes the low-side driver 18 to set the gate voltage LSG to high level and turn on the transistor 16 .

FIG. 8 is a diagram showing a specific example of a switching power supply circuit according to one embodiment, showing a configuration in which four circuits shown in FIG. 5 are combined. Controller 70 has overcurrent protection setting unit 75 shown in FIG. 5 for each of converters 51-54. In FIG. 8, the PWM modulator 74 generates a plurality of PWM signals each having a pulse width and a duty ratio that converge the deviation D to zero according to the deviation D between the reference voltage Vcm and the detected voltage Vs. A plurality of PWM signals generated by the PWM modulator 74 are supplied to corresponding overcurrent protection setting units 75 . With this configuration, when the amount of descent ΔV becomes equal to or greater than the predetermined value Va, the signal generation unit 71 stops outputting one of the PWM signals and adjusts the pulse width or duty ratio of the remaining PWM signals. The remaining PWM signal can be output without modification. This allows the remaining converters to continue outputting to the output path 31 according to the PWM signal having the pulse width and duty ratio determined by the PWM modulator 74 even if the output of some converters is stopped.

FIG. 9 is a diagram showing peak currents according to a comparative example in the configuration shown in FIG. FIG. 10 is a diagram showing peak current according to one embodiment in the configuration shown in FIG. 9 and 10 illustrate a case where the controller 70 shifts the output phases of the plurality of converters 51-54 by 90 degrees and controls the plurality of converters 51-54 so that they are not turned on at the same time.

In FIG. 9, when the controller 70 detects an output current Iout equal to or greater than a predetermined threshold value I2, the controller 70 performs control to switch the high-side transistors of some converters from on to off. In the method of controlling the off-timing of switching a transistor that is conducting electricity from on to off, an excessive peak current temporarily flows due to a delay in turning off the transistor.

On the other hand, in FIG. 10, when the controller 70 detects an output current Iout equal to or greater than the predetermined threshold value I1, the controller 70 controls the gates of the high-side transistors of some converters so that the high-side transistors do not switch from off to on. control to stop the PWM output of By controlling the on-timing of the transistor, it is possible to prohibit switching from off to on of the transistor, so that peak current can be suppressed.

In the example shown in FIG. 10, the signal generator 71 determines the pulse width or duty ratio of each of the plurality of PWM signals for each operating cycle. When the amount of descent ΔV becomes equal to or greater than a predetermined value Va, the signal generator 71 stops outputting one of the PWM signals, and sets the pulse width or duty ratio of the remaining PWM signals to the next operation cycle. , the remaining PWM signal is output without change. As a result, there is no change in the PWM command value for converters other than the converter whose output is stopped, so the other converters do not compensate for the decrease in the current of the converter whose output is stopped. Therefore, it is possible to suppress an increase in the current burden of the other converter.

Although the power supply circuit and the electronic device have been described above with reference to the embodiments, the present invention is not limited to the above embodiments. Various modifications and improvements such as combination or replacement with part or all of other embodiments are possible within the scope of the present invention.

For example, the number of converters may be other than four. For example, in the configuration of FIG. 3, the number of converters connected in parallel may be two or more. Also, the number of converters may be one.

The following additional remarks are disclosed regarding the above embodiments.
(Appendix 1)
a controller that outputs a plurality of PWM signals;
a plurality of converters connected in parallel to an output path and switching according to corresponding PWM signals among the plurality of PWM signals;
Each of the plurality of converters is connected between a high side arm, a low side arm connected in series with the high side arm, a connection point between the high side arm and the low side arm, and the output path. and an inductor
the controller stops outputting any one of the plurality of PWM signals when the amount of voltage drop in the output path reaches or exceeds a predetermined value;
The switching power supply circuit, wherein each of the plurality of converters stops PWM output to the gate of the high side arm and stops output to the output path when output of the corresponding PWM signal is stopped.
(Appendix 2)
The controller resumes outputting one of the PWM signals when the amount of descent becomes less than the predetermined value,
2. The switching power supply circuit according to claim 1, wherein each of the plurality of converters resumes PWM output to the gate and resumes output to the output path when output of the corresponding PWM signal resumes.
(Appendix 3)
The controller has a PWM signal generator that determines the pulse width or duty ratio of each of the plurality of PWM signals according to the difference between the reference voltage and the voltage of the output path,
3. The switching power supply circuit according to appendix 1 or 2, wherein the PWM signal generator stops outputting any one of the plurality of PWM signals when the difference becomes equal to or greater than the predetermined value.
(Appendix 4)
The PWM signal generation unit stops outputting one of the plurality of PWM signals when the difference becomes equal to or greater than the predetermined value, and does not change the pulse width or duty ratio of the remaining PWM signals. 3. The switching power supply circuit according to claim 3, wherein the remaining PWM signal is output to .
(Appendix 5)
The PWM signal generation unit determines the pulse width or duty ratio of each of the plurality of PWM signals for each operation cycle, and determines the pulse width or duty ratio of the remaining PWM signals without changing the pulse width or duty ratio until the next operation cycle. 5. The switching power supply circuit of claim 4, which outputs a remaining PWM signal.
(Appendix 6)
6. The switching power supply circuit according to any one of appendices 3 to 5, wherein the PWM signal generator resumes outputting any of the PWM signals when the difference becomes less than the predetermined value.
(Appendix 7)
The controller has a PWM signal generator that determines the pulse width or duty ratio of each of the plurality of PWM signals for each operation cycle,
The PWM signal generator stops outputting any one of the plurality of PWM signals when the amount of descent reaches or exceeds the predetermined value, and sets the pulse width or duty ratio of the remaining PWM signals as follows. 3. The switching power supply circuit according to appendix 1 or 2, wherein the remaining PWM signal is output without changing up to the operation period.
(Appendix 8)
Each of the plurality of converters has a bootstrap circuit that makes the gate voltage of the high side arm higher than the input voltage of the high side arm, and when the output of the corresponding PWM signal stops, the gate voltage 8. The switching power supply circuit according to any one of appendices 1 to 7, wherein the switching power supply circuit is prohibited from becoming higher than the input voltage.
(Appendix 9)
a load;
a controller that outputs a plurality of PWM signals;
a plurality of converters connected in parallel to an output path to which the load is connected and switching according to corresponding PWM signals among the plurality of PWM signals;
Each of the plurality of converters is connected between a high side arm, a low side arm connected in series with the high side arm, a connection point between the high side arm and the low side arm, and the output path. and an inductor
the controller stops outputting any one of the plurality of PWM signals when the amount of voltage drop in the output path reaches or exceeds a predetermined value;
The electronic device, wherein each of the plurality of converters stops PWM output to the gate of the high side arm and stops output to the output path when output of the corresponding PWM signal stops.

11 to 14 switching circuit 15, 16 transistor 17 high side driver 18 low side driver 19 connection point 21, 22, 23, 24 inductor 51, 52, 53, 54 converter 60 load 70 controller 71 signal generator 72 voltage detection circuit 73 integration circuit 74 PWM modulator 75 overcurrent protection setting section 80 bootstrap circuit 81 bootstrap capacitor 82 bootstrap diode 83 power supply 84 high power supply potential section 101 switching power supply circuit 201 electronic device

Claims (8)

a controller that outputs a plurality of PWM signals;
a plurality of converters connected in parallel to an output path and switching according to corresponding PWM signals among the plurality of PWM signals;
Each of the plurality of converters is connected between a high side arm, a low side arm connected in series with the high side arm, a connection point between the high side arm and the low side arm, and the output path. and an inductor
the controller stops outputting any one of the plurality of PWM signals when the amount of voltage drop in the output path reaches or exceeds a predetermined value;
The switching power supply circuit, wherein each of the plurality of converters stops PWM output to the gate of the high side arm and stops output to the output path when output of the corresponding PWM signal is stopped. The controller resumes outputting one of the PWM signals when the amount of descent becomes less than the predetermined value,
2. The switching power supply circuit according to claim 1, wherein each of said plurality of converters resumes PWM output to said gate and resumes output to said output path when output of said corresponding PWM signal resumes. The controller has a PWM signal generator that determines the pulse width or duty ratio of each of the plurality of PWM signals according to the difference between the reference voltage and the voltage of the output path,
3. The switching power supply circuit according to claim 1, wherein said PWM signal generator stops outputting any one of said plurality of PWM signals when said difference reaches said predetermined value or more. The PWM signal generation unit stops outputting one of the plurality of PWM signals when the difference becomes equal to or greater than the predetermined value, and does not change the pulse width or duty ratio of the remaining PWM signals. 4. The switching power supply circuit according to claim 3, outputting said remaining PWM signal to . The PWM signal generation unit determines the pulse width or duty ratio of each of the plurality of PWM signals for each operation cycle, and determines the pulse width or duty ratio of the remaining PWM signals without changing the pulse width or duty ratio until the next operation cycle. 5. The switching power supply circuit of claim 4, which outputs a remaining PWM signal. 6. The switching power supply circuit according to claim 3, wherein said PWM signal generator resumes outputting said one of said PWM signals when said difference becomes less than said predetermined value. The controller has a PWM signal generator that determines the pulse width or duty ratio of each of the plurality of PWM signals for each operation cycle,
The PWM signal generator stops outputting any one of the plurality of PWM signals when the amount of descent reaches or exceeds the predetermined value, and sets the pulse width or duty ratio of the remaining PWM signals as follows. 3. The switching power supply circuit according to claim 1, wherein said remaining PWM signal is output without changing up to an operation period. Each of the plurality of converters has a bootstrap circuit that makes the gate voltage of the high side arm higher than the input voltage of the high side arm, and when the output of the corresponding PWM signal stops, the gate voltage 8. The switching power supply circuit according to claim 1, wherein the switching power supply circuit is prohibited from becoming higher than the input voltage.

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