JP6875873B2 - DC / DC converter and its control circuit, in-vehicle electrical equipment - Google Patents

Description

The present invention relates to a DC / DC converter.

In various electronic devices, vehicles, and industrial machines, DC / DC converters that convert a DC voltage of one voltage value into a DC voltage of another voltage value are used. FIG. 1 is a circuit diagram of a synchronous rectification type buck DC / DC converter 900. The DC / DC converter 900 receives a DC input voltage V _IN at the input terminal 902 and generates a step-down output voltage V _{OUT at the output terminal 904. A switching transistor M 1} , a synchronous rectifier transistor M ₂ , an inductor L ₁ , and an output capacitor C ₁ are provided in the output stage of the DC / DC converter 900.

The pulse modulator 910 changes the duty ratio, frequency, or combination thereof so that the state of the DC / DC converter 900 or the state of the load (not shown) connected to the output terminal 904 approaches the target state. Pulse signal S _PWM is generated. The driver 912 switches the switching transistor M ₁ and the synchronous rectifier transistor M _{2 based on the pulse signal S PWM.}

For example, in a constant voltage output DC / DC converter 900, the pulse modulator 910 generates a pulse signal S _{PWM so that the output voltage V OUT} approaches the target voltage V _{OUT (REF).} In the constant current output DC / DC converter 900, the pulse signal S _{PWM is generated so that the current I OUT} flowing through the load approaches the target value I _REF . In the following description, the constant voltage output converter will be described. To do.

In DC / DC converter 900 immediately after the start the soft-start period _{T SS,} in order to prevent an inrush current to the output capacitor _{C 1,} the soft-start control is performed to raise gradually the output voltage _{V OUT.} FIG. 2A is a diagram illustrating soft start control.

The soft-start circuit 914 generates a soft start voltage V _SS to change slowly over time. A feedback signal V _FB obtained by dividing the output voltage V _OUT by the resistors R ₁₁ and R ₁₂ is input to the pulse modulator 910. Pulse modulator 910, in a soft-start period immediately after starting, the feedback signal V _FB generates a pulse signal S _PWM to follow the soft-start voltage V _SS, after the soft-start completion, the feedback signal V _FB reference voltage The _{pulse signal S PWM} is generated so as to match _{V REF.}

The switching frequency of the DC / DC converter 900, that _{is, the frequency of the pulse signal S PWM} is selected so as not to adversely affect the peripheral equipment, and varies depending on the application. As an example, the switching frequency of the DC / DC converter used for the vehicle-mounted power supply is set above the radio frequency band (for example, 2 MHz or more).

Japanese Unexamined Patent Publication No. 2011-83129 Japanese Unexamined Patent Publication No. 2011-78240

As a result of studying a DC / DC converter having a high switching frequency, the present inventor has come to recognize the following problems.

FIG. 2B is a diagram illustrating a problem that occurs in a DC / DC converter having a high switching frequency. The duty ratio of the pulse signal S _PWM is determined according to the ratio of the input voltage V _IN and the output voltage V _{OUT. Since the ratio of the input voltage V IN} to the output voltage V _OUT is large immediately after the start-up, the duty ratio of the pulse signal S _{PWM becomes very small.} The pulse width of the pulse signal S _PWM is the product of the duty ratio and the switching cycle (PWM cycle). In a DC / DC converter having a high switching frequency, _{the pulse width of the pulse signal S PWM} becomes very short.

The pulse generator 910 and the driver 912 have a response delay. The pulse width can be effectively turned the switching transistors M _1, there is a lower limit due to the response delay. Further, the pulse width that can be generated by the pulse generator 910 itself also has a lower limit due to the response delay. In the soft-start period, the pulse width of the pulse signal S _PWM is, becomes shorter than these lower limit (the minimum pulse width T _MIN), it is impossible to switch the switching transistor M ₁ in cycle-by-cycle, the teeth of the missing pulse (Called pulse skip) occurs. In the cycle in which the switching transistor M ₁ does not turn on, the output voltage V _OUT does not rise, and therefore _{the error between the feedback signal V FB} and the soft start voltage V _SS becomes large. Then, in the next cycle, _{the duty ratio of the pulse signal S PWM} becomes large, and the fluctuation range of the output voltage V _{OUT in one cycle becomes large.}

Due to such an operation, in a DC / DC converter having a high switching frequency, _{there arises a problem that the ripple width of the output voltage V OUT} during the soft start period becomes large or overshoot occurs and the start-up becomes unstable. This problem is especially noticeable in applications with long soft start times.

The present invention has been made in view of such a problem, and one of an exemplary purpose of the embodiment is to provide a DC / DC converter whose operation is stabilized during a soft start period.

One aspect of the present invention relates to a control circuit of a DC / DC converter. The control circuit consists of a frequency setting terminal to which an external resistor that defines the switching frequency should be connected, a soft start circuit that generates a frequency soft start voltage that gradually rises with time when the DC / DC converter is started, and a first reference voltage. The frequency setting voltage corresponding to the lower of the frequency soft start voltage is applied to the frequency setting terminal for the voltage selection circuit, the oscillator that oscillates at the frequency corresponding to the current flowing through the external resistor, and the periodic signal generated by the oscillator. A pulse modulator having a corresponding frequency and generating a pulse signal whose duty ratio is adjusted so that the output signal of the DC / DC converter approaches a target voltage is provided.

In this embodiment, the switching frequency gradually increases during the soft start period, and the switching cycle, which is the reciprocal of the switching frequency, becomes shorter. That is, in a state where the duty ratio immediately after startup is small, the switching cycle becomes long, so that the pulse width corresponding to the product of the duty ratio and the switching cycle can be maintained in a state larger than the minimum pulse width. As a result, pulse skipping can be suppressed, and ripple and overshoot of the output signal can be suppressed.

When the DC / DC converter is started, the target voltage may correspond to the lower of the output soft start voltage and the second reference voltage, which gradually increase with time. The frequency soft start voltage and the output soft start voltage may be in a proportional relationship.
The duty ratio of the pulse signal increases with the output soft start voltage. On the other hand, the frequency of the pulse signal increases in proportion to the frequency soft start voltage, and its period decreases in inverse proportion to the frequency soft start voltage. Therefore, when the frequency soft start voltage and the output soft start voltage have a substantially proportional relationship, the product of the duty ratio of the pulse signal and the pulse period, that is, the fluctuation of the pulse width can be reduced. Further, since a part or all of the hardware that generates the two soft start voltages can be shared, an increase in the circuit area can be suppressed.

The frequency soft start voltage may be a constant voltage for a predetermined time from the start of startup. As a result, the switching frequency can be fixed for a predetermined time from the start of activation.

The time it takes for the frequency soft-start voltage to reach the first reference voltage may be shorter or substantially equal than the time it takes for the output soft-start voltage to reach the second reference voltage.
As a result, the switching frequency can be stabilized after the soft start of the output signal is completed.

The soft start circuit includes a slope voltage generation circuit that generates a slope voltage that increases with time, a voltage divider circuit that divides the slope voltage to generate a frequency soft start voltage, and a switch provided in series with the voltage divider circuit. It may be included.

In the voltage selection circuit, one end is connected to the frequency setting terminal of the first transistor, one end is connected to the control terminal of the first transistor, the other end is grounded, and the first reference voltage is applied to the control terminal. It may include a transistor and a third transistor whose one end is connected to the control terminal of the first transistor, the other end is grounded, and a frequency soft start voltage is applied to the control terminal. According to this configuration, the lower of the first reference voltage and the frequency soft start voltage can be set as the frequency setting voltage.

The voltage selection circuit receives a frequency soft start voltage from a first transistor whose one end is connected to a frequency setting terminal and a first non-inverting input, a first reference voltage from a second non-inverting input, and an inverting input. A first error amplifier, which is connected to a frequency setting terminal and whose output is connected to a control terminal of a first transistor, may be included. According to this configuration, the lower of the first reference voltage and the frequency soft start voltage can be set as the frequency setting voltage.

The pulse modulator receives an output soft start voltage at the first non-inverting input, a second reference voltage at the second non-inverting input, and a feedback voltage at the inverting input according to the output signal of the DC / DC converter. A second error amplifier may be included.

The pulse modulator may be a modulator in peak current mode.

In some embodiments, the control circuit may be integrated into a single semiconductor substrate. "Integrated integration" includes cases where all the components of a circuit are formed on a semiconductor substrate or cases where the main components of a circuit are integrated integrally, and some of them are used for adjusting circuit constants. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate.

Another aspect of the invention relates to a DC / DC converter. The DC / DC converter includes any of the above control circuits.

Another aspect of the present invention relates to an in-vehicle electrical device. The in-vehicle electrical equipment includes the above-mentioned DC / DC converter.

It should be noted that any combination of the above components or components and expressions of the present invention that are mutually replaced between methods, devices, systems, and the like are also effective as aspects of the present invention.

Furthermore, the description of this item (means for solving the problem) does not explain all the essential features of the present invention, and therefore subcombinations of these features described may also be the present invention. ..

According to an aspect of the present invention, ripple and overshoot of the output signal during the soft start period can be suppressed.

It is a circuit diagram of a synchronous rectification type step-down DC / DC converter. FIG. 2A is a diagram for explaining soft start control, and FIG. 2B is a diagram for explaining a problem that occurs in a DC / DC converter having a high switching frequency. It is a circuit diagram of the DC / DC converter which concerns on 1st Embodiment. It is an operation waveform diagram of the DC / DC converter of FIG. It is another waveform diagram of the frequency soft start voltage. 6 (a) and 6 (b) are circuit diagrams showing a configuration example of a voltage selection circuit. It is a circuit diagram which shows the structural example of the soft start circuit. It is a circuit diagram which shows the specific configuration example of a control circuit. It is a circuit diagram of the DC / DC converter which concerns on 2nd Embodiment. It is an operation waveform diagram of the DC / DC converter of FIG. The voltage _{V RT} of the RT terminal in the control circuit of FIG. 9 is a diagram showing an oscillation signal _{S OSC} generated by the oscillator. It is a figure which shows the spectrum of the noise in the control circuit of FIG. It is a circuit diagram which shows the structural example of a spread spectrum circuit. 14 (a) and 14 (b) are circuit diagrams showing a configuration example of the voltage selection circuit of FIG. It is a circuit diagram of the DC / DC converter which concerns on 3rd Embodiment. It is an operation waveform diagram of the DC / DC converter of FIG. It is a circuit diagram which shows the structural example of the voltage selection circuit. It is a block diagram of the in-vehicle electrical equipment provided with a DC / DC converter.

Hereinafter, the present invention will be described with reference to the drawings based on preferred embodiments. The same or equivalent components, members, and processes shown in the drawings shall be designated by the same reference numerals, and redundant description will be omitted as appropriate. Further, the embodiment is not limited to the invention but is an example, and all the features and combinations thereof described in the embodiment are not necessarily essential to the invention.

In the present specification, the "state in which the member A is connected to the member B" means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. It also includes the case of being indirectly connected via other members that do not affect the state.
Similarly, "a state in which the member C is provided between the member A and the member B" means that the member A and the member C, or the member B and the member C are directly connected, and also electrically. It also includes the case of being indirectly connected via another member that does not affect the connection state.

The vertical and horizontal axes of the waveform charts and time charts referred to in the present specification are appropriately enlarged or reduced for ease of understanding, and each waveform shown is also simplified for ease of understanding. Or exaggerated or emphasized.

Further, "the signal A (voltage, current) corresponds to the signal B (voltage, current)" means that the signal A has a correlation with the signal B, and specifically, (i) the signal A. Is signal B, (ii) signal A is proportional to signal B, (iii) signal A is obtained by level-shifting signal B, (iv) signal A is obtained by amplifying signal B. If (v) signal A is obtained by inverting signal B, it means (vi) or any combination thereof, and the like. Those skilled in the art will understand that the range of "according to" is determined according to the types and uses of signals A and B.

(First Embodiment)
FIG. 3 is a circuit diagram of the DC / DC converter 100A according to the first embodiment. The DC / DC converter 100A is a synchronous rectification type buck converter, _{receives a DC input voltage V IN} at the input terminal 102, and generates a step-down output voltage V _{OUT at the output terminal 104.} The DC / DC converter 100A includes an output circuit 110 and a control circuit 200A. In this embodiment, a constant voltage output DC / DC converter will be described as an example.

The output circuit 110 includes a switching transistor M ₁ , a synchronous rectifier transistor M ₂ , an inductor L ₁ , an output capacitor C ₁ , and resistors R ₁₁ and R ₁₂ . In the present embodiment, the switching transistor M ₁ is a P-channel MOSFET and the synchronous rectifier transistor M ₂ is an N-channel MOSFET, which are built in the control circuit 200A.

The connection point between the switching transistor M ₁ and the synchronous rectifier transistor M ₂ is referred to as a switching (SW) terminal. The terminal may be read as a pin. The inductor L ₁ is provided between the SW terminal and the output terminal 104. The output capacitor C ₁ is connected to the output terminal 104. The resistors R ₁₁ and R ₁₂ supply the detection voltage (feedback signal) V _FB obtained by dividing the output voltage V _OUT to be controlled to the feedback (FB) terminal of the control circuit 200A. The resistors R ₁₁ and R ₁₂ may be built in the control circuit 200A.

The control circuit 200A includes a pulse modulator 210, a driver 230, a frequency setting circuit 220A, and an oscillator 260 in addition to _{the switching transistor M 1} and the synchronous rectifier transistor M _2. The control circuit 200A is preferably a functional IC (Integrated Circuit) integrally integrated on one semiconductor substrate. The source of the switching transistor M ₁ is connected to the VIN terminal, and its drain is connected to the SW terminal. Further, the drain of the synchronous rectifier transistor M ₂ is connected to the SW terminal, and its source is connected to the GND terminal. An enable signal EN instructing the operation and stop of the control circuit 200A (DC / DC converter 100A) is input to the enable (EN) terminal from the outside.

The pulse modulator 210 includes a main logic 218. When the enable signal EN is asserted (for example, high), the internal reference voltage source and reference current source (not shown) are activated, the other circuit blocks are put into an operable state, and the soft start voltage V _{SS1 is} applied to the soft start circuit 240. Instructs the start of V _{SS2 generation.} Upon receiving an instruction to start operation, the soft start circuit 240 generates _{soft start voltages V SS1} and V _{SS2 that gradually increase with time.} Soft start voltage _V SS2 _{period (V SS1)} is increased (which may include the front and back) is referred to as the soft-start period _{T SS.}

Pulse modulator 210, as state of the load (not shown) connected to the DC / DC converter 100A or the output terminal 104 approaches the target value, the pulse signal _{S PWM} (the high side for instructing on and off of the switching transistor _{M 1} pulse S _H) and to generate a low side pulse S _L for instructing the on-off of the synchronous rectifier transistor M _2.

As described above, the DC / DC converter 100A has a constant voltage output, and the pulse modulator 210 controls _{the output voltage V OUT of the DC / DC converter 100A.} Specifically pulse modulator 210, the feedback voltage _{V FB} that is fed back to the FB terminal, so as to approach its target value _{V REF,} the pulse signal _S PWM _{(S H} and _{S L)} is generated.

The pulse modulator 210 may use a known technique, and its control method and configuration are not particularly limited. As the control method, a voltage mode, a peak current mode, an average current mode, a hysteresis control (Bang-Bang control), a fixed bottom detection on time (COT) method, or the like can be adopted. Further, as the modulation method of the pulse signal S _PWM , although not limited to this, pulse width modulation (PWM) can be adopted. Regarding the configuration of the pulse modulator 210, it may be configured by an analog circuit using an error amplifier or a comparator, may be configured by a processor that performs digital arithmetic processing, or may be configured by a combination of an analog circuit and a digital circuit. You may. Further, the pulse modulator 210 may switch the control method according to the load state.

The operation mode of the pulse modulator 210 may be variable depending on the load condition. For example, the pulse modulator 210 may operate in the PWM mode in the heavy load state, and may operate in the PFM (Pulse Frequency Modulation) mode in the light load state. In PWM mode (especially continuous current mode), the high-side pulse S _H and the low-side pulse S _L becomes complementary signals.

The driver 230 drives the switching transistor _{M 1} based on the pulse signal _{S PWM} (the high-side pulse _{S H),} based on the low-side pulse _{S L} to drive the synchronous rectification transistor _{M 2.}

The frequency setting terminal (RT terminal), the external R _T resistor for defining the switching frequency f _SW is connected. _{The frequency setting circuit 220A applies a frequency setting voltage VRT} to the RT terminal, which gradually rises with time when the DC / DC converter 100A is started, and then maintains a constant value.
The frequency setting circuit 220A includes a soft start circuit 240 and a voltage selection circuit 250. The soft start circuit 240 generates a _{frequency soft start voltage V SS1} and an output soft start voltage V _SS2 that gradually increase with time when the DC / DC converter 100A is started. The frequency soft start voltage V _SS1 and the output soft start voltage V _SS2 are preferably proportional to each other, and one (for example, V _SS1 ) may be generated by dividing the other (for example, V _SS2).

The voltage selection circuit 250 applies a voltage (frequency setting voltage) V _{RT corresponding to the lower of the first reference voltage V REF1} and the frequency soft start voltage V _SS1 to the RT terminal. As a result, a current flows _{I OSC} through the RT terminal to the external resistor _{R T.}
I _OSC = _V RT / _{R T}

The oscillator 260 oscillates at a frequency corresponding to the current I _{OSC flowing through the external resistor RT.} The configuration of the oscillator 260 is not particularly limited. For example, the oscillator 260 includes a capacitor, _{a charging circuit that charges the capacitor with a current proportional to the current IOSC} , a comparator that compares the voltage of the capacitor with a threshold value, and a capacitor voltage threshold value according to the output of the comparator. It may include a discharge circuit that discharges the charge of the capacitor when it reaches.

_{The pulse modulator 210 operates in synchronization with the oscillation signal SOSC} generated by the oscillator 260, so that the pulse signal S _PWM has a frequency corresponding to the oscillation signal _SOSC.

Pulse modulator 210, when starting the DC / DC converter, as the feedback signal _{V FB} is closer to a target voltage corresponding to the lower of the output soft start voltage _{V SS2} second reference voltage _{V REF2,} the pulse signal S _{Adjust the PWM} duty ratio.

It is desirable that the time required for the frequency soft start voltage V _SS1 to reach the first reference voltage V _REF1 and the time required for the output soft start voltage V _SS2 to reach the second reference voltage V _{REF2 are substantially equal.}

The above is the configuration of the control circuit 200A and the DC / DC converter 100A. Next, the operation will be described.

FIG. 4 is an operation waveform diagram of the DC / DC converter 100A of FIG. When the enable signal EN is asserted at time _{t 0,} the frequency soft-start voltage _{V SS1} and outputs the soft-start voltage _{V SS2} begins to increase. Following the rise in the output soft start voltage V _SS2 , the output voltage V _OUT gradually rises. When the output soft-start voltage _{V SS2} at time _{t 1} reaches the second reference voltage _{V REF2,} thereafter, the output voltage _{V OUT} is stabilized at the target voltage _{V OUT (REF).}

Immediately after the start is started, since the frequency soft start voltage _VSS1 is low, the oscillation frequency of the oscillator 260, that is, the switching frequency f _SW of the DC / DC converter 100A is low, and the PWM cycle T _SW is long. As the frequency soft start voltage _VSS1 rises, the switching frequency f _SW rises and the PWM cycle T _SW becomes shorter.

And also the time almost the time _{t 1,} the output soft-start voltage _{V SS2} reaches the second reference voltage _{V REF2.} After time _{t 1,} the switching frequency _{f SW} is _the are stabilized to a value corresponding to the first reference voltage _{V REF1.}

The above is the operation of the DC / DC converter 100A.
In the soft start period _TSS , the switching frequency _fSW gradually increases, and the reciprocal of the switching period _TSW becomes shorter. That is, immediately after startup, when the input / output voltage ratio is large and _{the duty ratio of the pulse signal S PWM} is small, the switching cycle _TSW becomes long. As a result, the pulse width (ON time of the _{switching transistor M 1 ) T ON} corresponding to the product of the duty ratio and the switching period T _P can be maintained in a state larger than the minimum pulse width T _{M IN.} As a result, pulse skipping can be suppressed, and ripple and overshoot of _{the output voltage V OUT can be suppressed.}

Further, the frequency soft start voltage V _SS1 that defines the switching frequency f _SW is the first reference at substantially the same time that the output soft start voltage V _SS2 that defines the output voltage V _OUT reaches the second reference voltage V _REF2. The voltage V _REF1 is reached. When the output voltage V _OUT is stabilized to the target voltage V _{OUT (REF)} , the load starts to operate. According to the first embodiment _{, after the output voltage V OUT} is stabilized, the switching frequency f _SW Can be stabilized.

The time when the frequency soft start voltage V _SS1 reaches the first reference voltage V _REF1 may be earlier than the time when the output soft start voltage V _SS2 reaches the second reference voltage V _REF2.

Further, by generating the two soft start voltages V _SS1 and V _SS2 so as to have a proportional relationship, the following advantages can be enjoyed. The duty ratio of the pulse signal _{S PWM} is increased in accordance with the output soft-start voltage _{V SS2,} the frequency _{f SW} of the pulse signal _{S PWM} increases in proportion to the frequency soft-start voltage _{V SS1,} frequency software that cycle _{T SW} It decreases in inverse proportion to the start voltage V _SS1. Therefore, the product of the duty ratio of the pulse signal S _{PWM and the pulse period T SW} , that is, the fluctuation of the _{pulse width T ON can be reduced.}

FIG. 5 is another waveform diagram of the frequency soft start voltage _VSS1. Upon activation start, when 0V (zero volts) starting frequency soft start voltage V _SS, there is a case where the switching frequency just after the start is low, PWM cycle T _SW is too long. Therefore, as shown in FIG. 5, the frequency soft start voltage V _SS1 may be fixed to a certain lower limit voltage V _{MIN for a predetermined time TFIX from the start of the soft start.} In this case, the lower limit of the switching frequency at startup, in other words, the upper limit of the _{PWM cycle T SW , can be defined according to the lower limit voltage V MIN.} After completion of the predetermined time _{T FIX} In this case, the frequency soft start voltage _{V SS1} is proportional output soft-start voltage _{V SS2} is maintained.

The present invention extends to various devices and methods grasped as a block diagram or a cross-sectional view of FIG. 3 or derived from the above description, and is not limited to a specific configuration. Hereinafter, more specific configuration examples and examples will be described not for narrowing the scope of the present invention but for helping to understand the essence and operation of the invention and clarifying them.

6 (a) and 6 (b) are circuit diagrams showing a configuration example of the voltage selection circuit 250. The voltage selection circuit 250 of FIG. 6A includes the first transistor Q ₂₁ to the third transistor Q ₂₃ . The first transistor Q ₂₁ is an NPN bipolar transistor, and one end (emitter) thereof is connected to an RT terminal. The second transistor Q ₂₂ and the third transistor Q ₂₃ are PNP bipolar transistors, one end (emitter) of them is grounded, and the other end (collector) of them is connected to the control terminal (base) of _{the first transistor Q 21.} Will be done. To the control terminal of the second transistor _{Q 22} (base) the first reference voltage _{V REF1} is applied, the frequency soft-start voltage _{V SS1} is applied to the control terminal of the third transistor _{Q 23.} The base of the first transistor Q _{21 is biased by the resistor R 21} (or current source).

At the base of the first transistor Q _{21 , one of V SS1} + V _BE and V _REF1 + V _BE , whichever is lower, appears. The first transistor Q ₂₁ operates as an emitter follower, and the RT terminal has a _{voltage V BE} lower than the base potential of _{the first transistor Q 21} , that is, one of V _SS1 and V _{REF 1} , which is lower, min (V _SS1 , V _REF1 ). Is applied. As a result, I _OSC = min (V _SS1 , V _REF1 ) / _RT is supplied to the oscillator.

Voltage selection circuit 250 of FIG. 6 (b), includes a 3-input error amplifier (op amp) EA1, the transistor _{Q 31.} One end (emitter) of the transistor Q _{31 is connected to the RT terminal.} The error amplifier EA1 has two non-inverting input terminals (+) and one inverting input terminal (-), and one of the lower voltages of the two non-inverting input terminals (+) and the inverting input terminal (-). ) Amplifies the voltage error. The _{R T} resistor voltage selection circuit 250 forms a constant current source, the RT _terminal, appear low voltage of _{V SS1} and _{V REF1, the oscillator, I OSC = min (V SS1} , V REF1) / _RT is supplied.

In FIGS. 6A and 6B, the bipolar transistor may be replaced with an FET, in which case the base, emitter and collector may be read as gate, source and drain.

FIG. 7 is a circuit diagram showing a configuration example of the soft start circuit 240. The soft start circuit 240 includes a slope voltage generation circuit 242, a voltage divider circuit 244, and a switch 246. The slope voltage generation circuit 242 generates a slope voltage _VC41 that increases with time. For example, the slope voltage generation circuit 242 includes a capacitor C ₄₁ and a current source CS ₄₁ . One end of the capacitor C _{41 is grounded.} The current source CS ₄₁ becomes active in response to the assertion of the soft start start signal SS_START _{and charges the capacitor C 41} with a constant current. _{The slope voltage VC 41} generated in the capacitor C 41 increases with a constant slope with the passage of time.

The voltage divider circuit 244 including the resistors R ₄₁ and R _{42 divides the slope voltage VC 41} to generate the frequency soft start voltage V _SS1. The switch 246 is provided in series with the voltage divider circuit 244. The switch 246 is on during the soft start period. The switch 246 turns off after _{V SS1} > V _REF1. For example switch 246 can be controlled in response to the soft start completion signal SS_END for notifying the completion of the soft start period _{T SS.} As a result, it is possible to prevent wasteful power consumption by _{the resistors R 41} and R ₄₂ after the switching frequency is stabilized after the soft start is completed.

The slope voltage _VC41 may be used as the output soft start voltage _VSS2. Alternatively, the slope voltage _VC41 may be divided by another resistance voltage divider circuit to generate the _{output soft start voltage VSS2.} Regarding the generation of the two soft start voltages V _SS1 and V _{SS 2 , the capacitor C 41} and the current source CS ₄₁ can be shared, so that the circuit area can be reduced.

FIG. 8 is a circuit diagram showing a specific configuration example of the control circuit 200A. Current detecting circuit 270 during the on time of the switching transistor _{M 1,} detects the coil current flowing through the inductor _{L 1 I L} (the drain current _{I M1} of the switching transistor _{M 1} in other words), the current detection showing a drain current _{I M1} to generate a signal _{V CS.} Structure of the current detecting circuit 270 is not particularly limited, for example, the switching transistor to the drain current I _M1 by using the on-resistance of M ₁ may be detected, the drain current I _{M1 (or} coil current I _L) on the path of A sense resistor may be inserted into the sensor to detect the voltage drop of the sense resistor. Current detection circuit 270 may detect the coil current I _L on the basis of the voltage across the inductor L _1.

The pulse modulator 210 is a pulse width modulator in peak current mode. The pulse modulator 210 includes an error amplifier 212, a PWM comparator 214, a slope compensator 216, and a main logic 218. The error amplifier 212 amplifies the error between the output soft start voltage V _SS2 and the second reference voltage V _REF2 , whichever is lower, and the feedback voltage V _FB, and generates an error signal V _ERR. The error amplifier 212 may be composed of a three-input operational amplifier. Slope compensator 216, the current detection signal _{V CS} from the current detection circuit 270 superimposes the slope signal _{V SLOPE.}

PWM comparator 214, the error signal _{V ERR,} 'compares the current detection signal _{V CS'} current detection signal _{V CS} after the slope compensation when reaches the error signal _{V ERR,} asserts a reset signal _{S RESET} (e.g. high) To do. The main logic 218, in response to assertion of the reset signal _{S RESET,} the pulse signal _{S PWM,} to transition to a level corresponding to off of the switching transistor _{M 1} (off level, for example, low).

The oscillator 260 generates _{a set signal S SET} having a frequency corresponding to the _{current I OSC.} The main logic 218 is responsive to the edge of the set signal _{S SET,} the pulse signal _{S PWM,} to transition to a level corresponding to ON of the switching transistor _{M 1} (on-level, for example, high). During the soft start period, _{the frequency of the set signal SSET} generated by the oscillator 260 is low and then rises over time.

Subsequently, a modification related to the first embodiment will be described.
The soft start circuit 240 that generates the frequency soft start voltage V _SS1 and the soft start circuit 240 that generates the output soft start voltage V _SS2 may be independent and separate circuits.

Further, the method of generating the soft start voltage (slope voltage) is not limited to the method of charging the capacitor. For example, the soft start circuit may be composed of a digital circuit, and as an example, a digital counter whose count value increases with time and a D / A converter that converts the count value into a soft start voltage may be included.

(Second Embodiment)
FIG. 9 is a circuit diagram of the DC / DC converter 100B according to the second embodiment. The frequency setting circuit 220B in the embodiment applies a frequency setting voltage V _RT for periodically varying with time to the RT terminal.

The frequency setting circuit 220B includes a spread spectrum circuit 280 and a voltage selection circuit 250. The spread spectrum circuit 280 generates a _{spread spectrum voltage V SPS that fluctuates periodically with time.} The spread spectrum circuit 280 is inactive during the soft start period immediately after startup, and its output voltage V _SPS is maintained at a voltage level higher than the first reference voltage V _REF1. The frequency setting circuit 220B applies a frequency setting voltage V _{RT corresponding to the lower of the first reference voltage V REF1} and the spread spectrum voltage V _SPS to the RT terminal. For example the spectrum spreading circuit 280, SPSON signal asserted near the end timing of the soft-start period _{T SS} are input, the spectrum spreading circuit 280 in response to the assertion of SPSON signal becomes active.

The peak voltage V _PEAK of the spread spectrum voltage V _SPS is preferably lower than the first reference voltage V _REF1. More preferably, the spread spectrum voltage V _SPS fluctuates in a voltage range slightly lower than the first reference voltage V _REF1.

The spread spectrum voltage V _SPS may be a triangular wave, a ramp wave, a sine wave, or another periodic waveform. The configuration of the spread spectrum circuit 280 is not particularly limited, and a known circuit capable of generating a desired waveform can be used.

The spread spectrum circuit 280 can be switched between valid and invalid according to the enable signal SPS_EN. When disabled, the output voltage V _SPS of the spread spectrum circuit 280 is fixed at a level higher than _{the first reference voltage V REF1} even after the SS_END signal is asserted. As a result, the first reference voltage V _REF1 is always applied to the RT terminal, and the spread spectrum function is invalidated.

The above is the configuration of the DC / DC converter 100B. Next, the operation will be described. FIG. 10 is an operation waveform diagram of the DC / DC converter 100B of FIG. If the time _{t 0} the enable signal EN is asserted, the output soft-start voltage _{V SS2} begins to rise. Following the rise in the output soft start voltage V _SS2 , the output voltage V _OUT gradually rises. When the output soft-start voltage _{V SS2} at time _{t 1} reaches the second reference voltage _{V REF2,} thereafter, the output voltage _{V OUT} is stabilized at the target voltage _{V OUT (REF).}

In before time _{t 1,} the spectrum spreading circuit 280 is inactive, the output voltage _{V SPS} spectrum spreading circuit 280 is fixed at a higher level than the first reference voltage _{V REF1,} the RT terminal, first The reference voltage V _REF1 is applied. _{The switching frequency f SW} of the DC / DC converter 100B is fixed according to the first reference voltage V _REF1.

Starting of the DC / DC converter 100B at time _{t 1} is completed, the soft start completion signal SS_END is asserted, will spread spectrum circuit 280 active, the RT terminal spectrum spectrum spreading circuit 280 generates spreading voltage V _SPS is applied. Thus, the switching frequency _{f SW} of the DC / DC converter 100B periodically varies in accordance with the spread spectrum voltage _{V SPS.} Figure 11 is a diagram showing the voltage _{V RT} of the RT terminal in the control circuit 200B, an oscillation signal _{S OSC} generated by the oscillator 280 (clock signal).

The above is the operation of the control circuit 200B. FIG. 12 is a diagram showing a noise spectrum in the control circuit 200B of FIG. (I) shows the spectrum when the spread spectrum circuit 280 is enabled in the control circuit 200B of FIG. 9, and (ii) shows the spectrum when the spread spectrum circuit 280 is disabled.

As can be seen from FIG. 12, by enabling the spread spectrum circuit 280, the spectrum of switching noise can be diffused and the peak intensity can be suppressed.

FIG. 13 is a circuit diagram showing a configuration example of the spread spectrum circuit 280. This spread spectrum circuit 280 is a triangular wave generation circuit.

The voltage source 282 generates an _{upper threshold V PEAK} that defines the peak of the _{spread spectrum voltage V SPS} and a lower threshold V _{BOTTOM that defines the bottom.} The charge / discharge circuit 284 repeats charging and discharging of the _{capacitor C 51.} The comparator 286 compares the voltage V _{SPS of the capacitor C 51} with the threshold voltages V _PEAK and V _BOTTOM . The charge / discharge circuit 284 is in a discharged state when the output of the comparator 286 is high, and is in a charged state when the output of the comparator 286 is low. The voltage source 282 outputs the lower threshold value V _{BOTTOM when the output of the comparator 286 is high, and outputs the upper threshold value V PEAK} when the output of the comparator 286 is low.

The voltage source 282 includes a resistance voltage divider circuit _{including resistors R 51 to} R _{54. By dividing the} reference voltage V REF, a first reference voltage V _REF1 and two threshold values V _PEAK and V _BOTTOM are generated. This guarantees the relationship of _{V PEAK} <V _REF1. The switch SW _H and the switch SW _L are complementarily turned on and off according to the output of the comparator 286. _{V PEAK} is output when the switch SW _H is on, and _{V BOTTOM} is output when the _{switch SW L is on.}

The charge / discharge circuit 284 includes current mirror circuits CM ₅₁ , CM _52, and a constant current source CS ₅₁ . The constant current source CS ₅₁ is turned on when the SPS_ON signal is asserted, and generates a _{reference current I REF.} The current mirror circuit CM ₅₁ copies the reference current I _REF generated by the constant current source CS _{51 to generate the charging current IC HG} . The current mirror circuit CM ₅₂ copies the reference current I _REF generated by the constant current source CS _{51 and} generates the discharge current I _DIS . The current mirror circuit CM ₅₂ operates when the output of the comparator 286 is high, and stops when the output of the comparator 286 is low. When I _DIS > _{IC HG} holds and the output of the comparator 286 is high, the capacitor C ₅₁ is _{discharged by the I DIS-} I _CHG , and when the output of the comparator 286 is low, the capacitor C ₅₁ is charged by the _{IC HG.} To.

According to this configuration, the spread spectrum voltage _VSPS as shown in FIG. 11 can be generated.

14 (a) and 14 (b) are circuit diagrams showing a configuration example of the voltage selection circuit 250 of FIG. The voltage selection circuit 250 of FIGS. 14A and 14B can be configured in the same manner as the voltage selection circuit 250 of FIGS. 6A and 6B.

(Third Embodiment)
FIG. 15 is a circuit diagram of the DC / DC converter 100C according to the third embodiment. The DC / DC converter 100C can be grasped as a combination of the first embodiment and the second embodiment.

_{The frequency setting circuit 220C applies a frequency setting voltage VRT} to the RT terminal, which gradually rises with time when the DC / DC converter 100C is started, and then periodically fluctuates with time.

The frequency setting circuit 220C includes a soft start circuit 240, a spread spectrum circuit 280, and a voltage selection circuit 250C.

The soft start circuit 240 generates the _{frequency soft start voltage V SS1} and the output soft start voltage V _SS2 as described in the first embodiment. The voltage selection circuit 250C receives the first reference voltage V _REF1 , the spectrum diffusion voltage V _SPS , and the frequency soft start voltage V _SS1 , and applies the frequency setting voltage V _RT corresponding to one of them to the RT setting terminal. ..

The above is the configuration of the control circuit 200C. Next, the operation will be described. FIG. 16 is an operation waveform diagram of the DC / DC converter 100C of FIG.

When the enable signal EN is asserted at time _{t 0,} the frequency soft-start voltage _{V SS1} and outputs the soft-start voltage _{V SS2} begins to increase. Following the rise in the output soft start voltage V _SS2 , the output voltage V _OUT gradually rises.

Further, the switching frequency f _SW increases following the increase in the frequency soft start voltage _VSS1. In other words, since the switching frequency f _SW immediately after the start of operation becomes low, it is possible _{to suppress the pulse width of the pulse signal S PWM from} becoming too narrow and the occurrence of pulse skipping.

When the output soft-start voltage _{V SS2} at time _{t 1} reaches the second reference voltage _{V REF2,} thereafter, the output voltage _{V OUT} is stabilized at the target voltage _{V OUT (REF).} Then, the SS_END signal indicating the end of the soft start period is asserted. As a result, a spread spectrum voltage V _SPS is applied to the RT terminal and fluctuates periodically. The switching frequency f _SW fluctuates following the frequency set voltage _VRT.

The above is the operation of the control circuit 200C. According to this, both the advantages of the first embodiment and the second embodiment can be enjoyed. Further, since the voltage selection circuit 250 can be shared as hardware, an increase in the circuit area can be suppressed.

FIG. 17 is a circuit diagram showing a configuration example of the voltage selection circuit 250. The voltage selection circuit 250C includes the first transistor Q ₄₁ to the fourth transistor Q ₄₄ . The emitter of the first transistor Q ₄₁ is connected to the RT terminal. The emitters of the second transistor Q ₄₂ to the fourth transistor Q ₄₄ are connected in common with the base of the first transistor Q _{41, and their sources are grounded.} The first reference voltage V _REF1 is applied to the base of the second transistor Q ₄₂ , the spectrum diffusion voltage V _SPS is applied to the base of the third transistor Q ₄₃ , and the frequency soft start voltage is applied to the base of the fourth transistor Q _44. V _SS1 is applied.

According to this configuration, _{the lowest voltage among the three voltages V SS1} , V _SPS , and V _REF1 can be applied to the RT terminal.

(Use)
FIG. 18 is a block diagram of an in-vehicle electrical equipment 300 including a DC / DC converter 100. The in-vehicle electrical equipment 300 includes a battery 302, a microcomputer 304, and a load 306 in addition to the DC / DC converter 100. The battery 302 produces, for example, a battery voltage V _BAT of 12 V (or 24 V). The DC / DC converter 100 receives the battery voltage V _BAT as the input voltage V _IN and generates _{an output voltage V OUT} having an optimum voltage level for the load 306. The load 306 is not particularly limited, and various ECUs (Electronic Control Units), audio circuits, car navigation systems, and the like are exemplified. The microcomputer 304 is a host processor that integrally controls the in-vehicle electrical equipment 300, and outputs an EN signal to the control circuit 200. Further, when the FLG terminal of the control circuit 200 is monitored and an abnormality occurring in the control circuit 200 is detected, an appropriate protection process is executed.

Since many electronic components are mounted on vehicles such as automobiles, strict EMC is required for the in-vehicle electrical equipment 300. According to the DC / DC converter 100 according to the embodiment, it is possible to clear the standard required for the in-vehicle electrical equipment 300.

The present invention has been described above based on the embodiments. This embodiment is an example, and it is understood by those skilled in the art that various modifications are possible for each of these components and combinations of each processing process, and that such modifications are also within the scope of the present invention. is there. Hereinafter, such a modification will be described.

There are various variations in the configuration and topology of the output circuit 110. The high-side switching transistor of the DC / DC converter may be an N-channel MOSFET. Further, the switching transistor M ₁ and the synchronous rectifying transistor M ₂ may be externally attached to the control circuit 200. The present invention is also applicable to DC / DC diode rectification type including a rectifying diode in place of the synchronous rectification transistor M ₂ (Schottky diode) is applicable.

The DC / DC converter is not limited to the step-down type, and the present invention can be applied to the step-up type and the buck-boost type. The present invention can also be applied to a converter using a transformer such as a flyback converter.

In the embodiment, the case where the switching transistor M ₁ and the synchronous rectifier transistor M ₂ are MOSFETs has been described, but the present invention is not limited to this, and may be an IGBT (Insulated Gate Bipolar Transistor).

The resistors R ₁₁ and R ₁₂ may be externally attached to the control circuit 200.

The application of the DC / DC converter 100 is not limited to in-vehicle electrical equipment, but can also be used for small electronic equipment, computers, and the like.

Although the present invention has been described using specific terms and phrases based on the embodiments, the embodiments merely indicate the principles and applications of the present invention, and the embodiments are defined in the claims. Many modifications and arrangement changes are permitted without departing from the ideas of the present invention.

100 ... DC / DC converter, 102 ... input terminal, 104 ... output terminal, 110 ... output circuit, M ₁ ... switching transistor, M ₂ ... synchronous rectifying transistor, L ₁ ... inductor, C ₁ ... output capacitor, 200 ... control circuit , 210 ... Pulse modulator, 212 ... Error amplifier, 214 ... PWM comparator, 216 ... Slope compensator, 218 ... Main logic, 220 ... Frequency setting circuit, 230 ... Driver, 240 ... Soft start circuit, 242 ... Slope voltage generation circuit , 244 ... voltage dividing circuit, 246 ... switch, 250 ... voltage selection circuit, 260 ... oscillator, 270 ... current detection circuit, S _PWM ... pulse signal, 280 ... spectrum diffusion circuit, 300 ... in-vehicle electrical equipment, 302 ... battery, 304 ... microcomputer, 306 ... load.

Claims (8)

It is a control circuit of a DC / DC converter.
A frequency setting terminal to which an external resistor that defines the switching frequency should be connected, and
A soft-start circuit that generates a frequency soft-start voltage that gradually rises over time when the DC / DC converter is started.
A voltage selection circuit that applies a frequency setting voltage corresponding to the lower of the first reference voltage and the frequency soft start voltage to the frequency setting terminal, and
An oscillator that oscillates at a frequency corresponding to the current flowing through the external resistor,
A pulse modulator that has a frequency corresponding to a periodic signal generated by the oscillator and generates a pulse signal whose duty ratio is adjusted so that the output signal of the DC / DC converter approaches a target voltage.
With
The frequency soft start voltage takes a constant voltage for a predetermined time from the start of startup.
The voltage selection circuit
A first transistor whose one end is connected to the frequency setting terminal,
A second transistor in which one end is connected to the control terminal of the first transistor, the other end is grounded, and the first reference voltage is applied to the control terminal.
A third transistor in which one end is connected to the control terminal of the first transistor, the other end is grounded, and the frequency soft start voltage is applied to the control terminal.
A control circuit characterized by including. When the DC / DC converter is started, the target voltage corresponds to the lower of the output soft start voltage and the second reference voltage, which gradually increase with time.
The control circuit according to claim 1, wherein the frequency soft start voltage and the output soft start voltage are in a proportional relationship after a lapse of a predetermined time from the start of the start. 2. The time until the frequency soft start voltage reaches the first reference voltage and the time until the output soft start voltage reaches the second reference voltage are substantially equal. The control circuit described in. The soft start circuit
A slope voltage generation circuit that generates a slope voltage that increases over time,
A voltage divider circuit that divides the slope voltage to generate the frequency soft start voltage,
A switch provided in series with the voltage divider circuit,
The control circuit according to any one of claims 1 to 3, wherein the control circuit comprises. The control circuit according to any one of claims 1 to 4 , wherein the pulse modulator is a modulator in a peak current mode. The control circuit according to any one of claims 1 to 5 , wherein the control circuit is integrally integrated on one semiconductor substrate. A DC / DC converter comprising the control circuit according to any one of claims 1 to 6. An in-vehicle electrical device comprising the DC / DC converter according to claim 7.

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