JP2018129907A - Dc/dc converter and control circuit thereof, control method, and on-vehicle electrical apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To stabilize operation of a DC/DC converter during soft start period.SOLUTION: A frequency setting terminal RT is connected with an external resistor Rstipulating the switching frequency. At the time of start-up of a DC/DC converter 100, a soft start circuit 240 generates a frequency soft start voltage Vrising gently with time. A voltage selection circuit 250 applies a frequency setting voltage V, according to the lower one of the first reference voltage Vand the frequency soft start voltage V, to the frequency setting terminal RT. An oscillator 260 oscillates at a frequency according to a current Iflowing to the external resistor R. A pulse modulator 210 generates a pulse signal Shaving a frequency according to an oscillation signal Sgenerated by the oscillator 260, and a duty ratio adjusted so that the output signal from the DC/DC converter 100 approaches a target voltage.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a DC / DC converter.

In various electronic devices, vehicles, and industrial machines, a DC / DC converter that converts a DC voltage of one voltage value into a DC voltage of another voltage value is used. FIG. 1 is a circuit diagram of a synchronous rectification step-down (Buck) DC / DC converter 900. The DC / DC converter 900 receives a DC input voltage _VIN at an input terminal 902 and generates a stepped down output voltage _VOUT at an output terminal 904. At the output stage of the DC / DC converter 900, a switching transistor M ₁ , a synchronous rectification transistor M ₂ , an inductor L ₁ , and an output capacitor C ₁ are provided.

The pulse modulator 910 changes the duty ratio, frequency, or combination thereof so that the state of the DC / DC converter 900 or the state of the load (not shown) connected to the output terminal 904 approaches the target state. The pulse signal S _PWM to be generated is generated. Driver 912 switches the switching transistor _{M 1} and the synchronous rectification transistor _{M 2} on the basis of the pulse signal _{S PWM}

For example, in the DC / DC converter 900 with a constant voltage output, the pulse modulator 910 generates the pulse signal S _PWM so that the output voltage V _OUT approaches the target voltage V _{OUT (REF)} . In the DC / DC converter 900 with constant current output, the pulse signal S _PWM is generated so that the current I _OUT flowing through the load approaches the target value I _REF , but in the following description, the constant voltage output converter will be described. To do.

In DC / DC converter 900 immediately after the start the soft-start period _{T SS,} in order to prevent an inrush current to the output capacitor _{C 1,} the soft-start control is performed to raise gradually the output voltage _{V OUT.} FIG. 2A illustrates the soft start control.

The soft-start circuit 914 generates a soft start voltage V _SS to change slowly over time. The pulse modulator 910 receives a feedback signal V _FB obtained by dividing the output voltage _VOUT by the resistors R ₁₁ and R ₁₂ . The pulse modulator 910 generates the pulse signal S _PWM so that the feedback signal V _FB follows the soft start voltage V _SS in the soft start period immediately after the start, and after the soft start is completed, the feedback signal V _FB becomes the reference voltage. The pulse signal S _PWM is generated so as to coincide with V _REF .

The switching frequency of the DC / DC converter 900, that is, the frequency of the pulse signal _SPWM is selected so as not to adversely affect peripheral devices, and varies depending on the application. As an example, the switching frequency of a DC / DC converter used for an in-vehicle power supply is set above the radio frequency band (for example, 2 MHz or more).

JP 2011-83129 A JP 2011-78240 A

  As a result of studying a DC / DC converter having a high switching frequency, the present inventor has come to recognize the following problems.

FIG. 2B is a diagram illustrating a problem that occurs in a DC / DC converter having a high switching frequency. The duty ratio of the pulse signal S _PWM is determined according to the ratio between the input voltage V _IN and the output voltage V _OUT . Immediately after startup, since the ratio of the input voltage V _IN and the output voltage V _OUT is large, the duty ratio of the pulse signal S _PWM becomes very small. The pulse width of the pulse signal S _PWM is the product of the duty ratio and the switching cycle (PWM cycle). In a DC / DC converter having a high switching frequency, the pulse width of the pulse signal S _PWM is very short.

The pulse generator 910 and the driver 912 have a response delay. The pulse width can be effectively turned the switching transistors M _1, there is a lower limit due to the response delay. Also, the pulse width that can be generated by the pulse generator 910 itself has a lower limit due to the response delay. If the pulse width of the pulse signal S _PWM becomes shorter than these lower limits (minimum pulse width T _MIN ) during the soft start period, the switching transistor M ₁ cannot be switched on a cycle-by-cycle basis. (Referred to as pulse skip) occurs. The switching transistor _{cycle M 1} is not turned on, the output voltage _{V OUT} is not increased, therefore the error of the feedback signal _{V FB} and the soft-start voltage _{V SS} increases. Then, in the next cycle, the duty ratio of the pulse signal S _PWM is increased, and the fluctuation range of the output voltage _{VOUT in} one cycle is increased.

With such an operation, a DC / DC converter with a high switching frequency has a problem that the ripple width of the output voltage _VOUT during the soft start period becomes large or an overshoot occurs, resulting in unstable start-up. This problem is particularly noticeable in applications with a long soft start time.

  The present invention has been made in view of such a problem, and one of the exemplary purposes of an aspect thereof is to provide a DC / DC converter that stabilizes the operation in the soft start period.

  One embodiment of the present invention relates to a control circuit for a DC / DC converter. The control circuit includes a frequency setting terminal to which an external resistor defining a switching frequency is to be connected, a soft start circuit that generates a frequency soft start voltage that gradually increases with time when the DC / DC converter is started, and a first reference voltage The frequency setting voltage corresponding to the lower one of the frequency soft start voltages is applied to the voltage selection circuit that applies to the frequency setting terminal, the oscillator that oscillates at a frequency corresponding to the current flowing through the external resistor, and the periodic signal generated by the oscillator A pulse modulator that generates a pulse signal having a frequency according to which the duty ratio is adjusted so that the output signal of the DC / DC converter approaches the target voltage.

  In this aspect, in the soft start period, the switching frequency increases gradually, and the switching cycle, which is the reciprocal thereof, becomes shorter. That is, since the switching cycle becomes long in a state where the duty ratio is small immediately after startup, the pulse width corresponding to the product of the duty ratio and the switching cycle can be maintained in a state larger than the minimum pulse width. Thereby, pulse skip can be suppressed, and ripple and overshoot of the output signal can be suppressed.

At the time of starting the DC / DC converter, the target voltage may correspond to the lower one of the output soft start voltage that gradually increases with time and the second reference voltage. The frequency soft start voltage and the output soft start voltage may be in a proportional relationship.
The duty ratio of the pulse signal increases according to the output soft start voltage. On the other hand, the frequency of the pulse signal increases in proportion to the frequency soft start voltage, and the period decreases in inverse proportion to the frequency soft start voltage. Therefore, when the frequency soft start voltage and the output soft start voltage have a substantially proportional relationship, the product of the duty ratio of the pulse signal and the pulse period, that is, the fluctuation of the pulse width can be reduced. In addition, since part or all of the hardware that generates the two soft start voltages can be shared, an increase in circuit area can be suppressed.

  The output soft start voltage may take a constant voltage for a predetermined time from the start of activation. Thereby, the switching frequency can be fixed for a predetermined time from the start of activation.

The time until the frequency soft start voltage reaches the first reference voltage may be shorter than or substantially equal to the time until the output soft start voltage reaches the second reference voltage.
Thereby, the switching frequency can be stabilized after the soft start of the output signal is completed.

  The soft start circuit includes a slope voltage generation circuit that generates a slope voltage that increases with time, a voltage dividing circuit that divides the slope voltage to generate a frequency soft start voltage, and a switch provided in series with the voltage dividing circuit. May be included.

  The voltage selection circuit includes a first transistor having one end connected to the frequency setting terminal, one end connected to the control terminal of the first transistor, the other end grounded, and a second reference voltage applied to the control terminal. The transistor may include a third transistor having one end connected to the control terminal of the first transistor, the other end grounded, and a frequency soft start voltage applied to the control terminal. According to this configuration, the lower one of the first reference voltage and the frequency soft start voltage can be set as the frequency setting voltage.

  The voltage selection circuit includes a first transistor having one end connected to a frequency setting terminal, a frequency soft start voltage received at a first non-inverting input, a first reference voltage received at a second non-inverting input, and an inverting input A first error amplifier connected to the frequency setting terminal and having an output connected to the control terminal of the first transistor may be included. According to this configuration, the lower one of the first reference voltage and the frequency soft start voltage can be set as the frequency setting voltage.

  The pulse modulator receives the output soft start voltage at the first non-inverting input, the second reference voltage at the second non-inverting input, and the feedback voltage corresponding to the output signal of the DC / DC converter at the inverting input. A second error amplifier may be included.

  The pulse modulator may be a peak current mode modulator.

  In one embodiment, the control circuit may be integrated on a single semiconductor substrate. “Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate.

  Another aspect of the present invention relates to a DC / DC converter. The DC / DC converter includes any one of the control circuits described above.

  Another aspect of this invention is related with a vehicle-mounted electrical equipment. The in-vehicle electrical equipment includes the above-described DC / DC converter.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  Further, the description of this item (means for solving the problem) does not explain all the essential features of the present invention, and therefore a sub-combination of these described features can also be the present invention. .

  According to an aspect of the present invention, it is possible to suppress output signal ripple and overshoot during the soft start period.

It is a circuit diagram of a synchronous rectification step-down DC / DC converter. FIG. 2A is a diagram illustrating soft start control, and FIG. 2B is a diagram illustrating a problem that occurs in a DC / DC converter having a high switching frequency. 1 is a circuit diagram of a DC / DC converter according to a first embodiment. FIG. 4 is an operation waveform diagram of the DC / DC converter of FIG. 3. It is another wave form diagram of a frequency soft start voltage. 6A and 6B are circuit diagrams illustrating configuration examples of the voltage selection circuit. It is a circuit diagram which shows the structural example of a soft start circuit. It is a circuit diagram which shows the specific structural example of a control circuit. It is a circuit diagram of the DC / DC converter which concerns on 2nd Embodiment. FIG. 10 is an operation waveform diagram of the DC / DC converter of FIG. 9. FIG. 10 is a diagram illustrating a voltage V _{RT at} an RT terminal and an oscillation signal S _OSC generated by an oscillator in the control circuit of FIG. 9. It is a figure which shows the spectrum of the noise in the control circuit of FIG. It is a circuit diagram which shows the structural example of a spread spectrum circuit. 14A and 14B are circuit diagrams showing a configuration example of the voltage selection circuit of FIG. It is a circuit diagram of the DC / DC converter which concerns on 3rd Embodiment. FIG. 16 is an operation waveform diagram of the DC / DC converter of FIG. 15. It is a circuit diagram which shows the structural example of a voltage selection circuit. It is a block diagram of a vehicle-mounted electrical equipment provided with a DC / DC converter.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  The vertical and horizontal axes of the waveform diagrams and time charts referred to in this specification are enlarged or reduced as appropriate for easy understanding, and each waveform shown is also simplified for easy understanding. Or exaggerated or emphasized.

  “Signal A (voltage, current) is in response to signal B (voltage, current)” means that signal A has a correlation with signal B. Specifically, (i) signal A Is signal B, (ii) signal A is proportional to signal B, (iii) signal A is obtained by level shifting signal B, and (iv) signal A is obtained by amplifying signal B. If (v) signal A is obtained by inverting signal B, it means (vi) or any combination thereof. It will be understood by those skilled in the art that the “depending” range is determined depending on the type and application of the signals A and B.

(First embodiment)
FIG. 3 is a circuit diagram of the DC / DC converter 100A according to the first embodiment. The DC / DC converter 100A is a synchronous rectification step-down (Buck) converter, which receives a DC input voltage _VIN at an input terminal 102 and generates a stepped-down output voltage _VOUT at an output terminal 104. The DC / DC converter 100A includes an output circuit 110 and a control circuit 200A. In this embodiment, a DC / DC converter with a constant voltage output will be described as an example.

The output circuit 110 includes a switching transistor M ₁ , a synchronous rectification transistor M ₂ , an inductor L ₁ , an output capacitor C ₁ , and resistors R ₁₁ and R ₁₂ . Switching transistor _{M 1} in this embodiment is a P-channel MOSFET, and synchronous rectification transistor _{M 2} is an N-channel MOSFET, which are incorporated in the control circuit 200A.

The connection point of the switching transistor _{M 1} and the synchronous rectification transistor _{M 2} is referred to as a switching (SW) terminal. The terminal may be read as a pin. The inductor L ₁ is provided between the SW terminal and the output terminal 104. The output capacitor C ₁ is connected to the output terminal 104. The resistors R ₁₁ and R ₁₂ supply a detection voltage (feedback signal) V _FB obtained by dividing the output voltage _VOUT to be controlled to the feedback (FB) terminal of the control circuit 200A. The resistors R ₁₁ and R ₁₂ may be incorporated in the control circuit 200A.

The control circuit 200A includes a pulse modulator 210, a driver 230, a frequency setting circuit 220A, and an oscillator 260 in addition to the switching transistor M ₁ and the synchronous rectification transistor M ₂ . The control circuit 200A is preferably a functional IC (Integrated Circuit) integrated on a single semiconductor substrate. The source of the switching transistor _{M 1} is a VIN terminal, its drain is connected to the SW terminal. The drain of the synchronous rectification transistor M ₂ is connected to the SW terminal, its source connected to the GND terminal. An enable signal EN for instructing the operation and stop of the control circuit 200A (DC / DC converter 100A) is input to the enable (EN) terminal from the outside.

The pulse modulator 210 includes a main logic 218. When the enable signal EN is asserted (for example, high), an internal reference voltage source and a reference current source (not shown) are activated to make other circuit blocks operable, and the soft start circuit V _SS1 , the soft start voltage V _SS1 , Instructs generation start of V _SS2 . When receiving an instruction to start operation, the soft start circuit 240 generates soft start voltages V _SS1 and V _SS2 that gradually increase with time. A period during which the soft start voltage V _SS2 (V _SS1 ) increases (or before and after that) is referred to as a soft start period T _SS .

Pulse modulator 210, as state of the load (not shown) connected to the DC / DC converter 100A or the output terminal 104 approaches the target value, the pulse signal _{S PWM} (the high side for instructing on and off of the switching transistor _{M 1} pulse S _H) and to generate a low side pulse S _L for instructing the on-off of the synchronous rectifier transistor M _2.

As described above, the DC / DC converter 100A has a constant voltage output, and the pulse modulator 210 controls the output voltage _VOUT of the DC / DC converter 100A. Specifically, the pulse modulator 210 generates the pulse signal S _PWM (S _H and S _L ) so that the feedback voltage V _FB fed back to the FB terminal approaches the target value V _REF .

The pulse modulator 210 may use a known technique, and its control method and configuration are not particularly limited. As a control method, a voltage mode, a peak current mode, an average current mode, a hysteresis control (Bang-Bang control), a bottom detection on-time fixed (COT: Constant On Time) method, or the like can be adopted. The modulation method of the pulse signal S _PWM is not limited to this, but pulse width modulation (PWM) can be adopted. The configuration of the pulse modulator 210 may be configured by an analog circuit using an error amplifier or a comparator, may be configured by a processor that performs digital arithmetic processing, or may be configured by a combination of an analog circuit and a digital circuit. May be. Further, the pulse modulator 210 may switch the control method according to the load state.

The operation mode of the pulse modulator 210 may be variable depending on the load state. For example, the pulse modulator 210 may operate in a PWM mode in a heavy load state, and may operate in a PFM (Pulse Frequency Modulation) mode in a light load state. In PWM mode (especially continuous current mode), the high-side pulse S _H and the low-side pulse S _L becomes complementary signals.

The driver 230 drives the switching transistor _{M 1} based on the pulse signal _{S PWM} (the high-side pulse _{S H),} based on the low-side pulse _{S L} to drive the synchronous rectification transistor _{M 2.}

The frequency setting terminal (RT terminal), the external R _T resistor for defining the switching frequency f _SW is connected. The frequency setting circuit 220A gradually increases with time when the DC / DC converter 100A is activated, and then applies a frequency setting voltage _VRT that maintains a constant value to the RT terminal.
The frequency setting circuit 220 </ b> A includes a soft start circuit 240 and a voltage selection circuit 250. The soft start circuit 240 generates a frequency soft start voltage V _SS1 and an output soft start voltage V _SS2 that gradually increase with time when the DC / DC converter 100A is activated. The frequency soft start voltage V _SS1 and the output soft start voltage V _SS2 preferably have a proportional relationship, and one (for example, V _SS1 ) may be generated by dividing the other (for example, V _SS2 ).

The voltage selection circuit 250 applies a voltage (frequency setting voltage) V _RT corresponding to the lower one of the first reference voltage V _REF1 and the frequency soft start voltage V _SS1 to the RT terminal. As a result, a current flows _{I OSC} through the RT terminal to the external resistor _{R T.}
I _OSC = _V RT / _{R T}

The oscillator 260 oscillates at a frequency corresponding to the current I _OSC flowing through the external resistor _RT . The configuration of the oscillator 260 is not particularly limited. For example, the oscillator 260 includes a capacitor, a charging circuit that charges the capacitor with a current proportional to the current I _OSC , a comparator that compares the capacitor voltage with a threshold value, and the capacitor voltage is set to a threshold value according to the output of the comparator. And a discharge circuit that discharges the electric charge of the capacitor when the voltage reaches.

The pulse modulator 210 operates in synchronization with the oscillation signal S _OSC generated by the oscillator 260. Therefore, the pulse signal S _PWM has a frequency corresponding to the oscillation signal S _OSC .

When starting the DC / DC converter, the pulse modulator 210 makes the pulse signal S so that the feedback signal V _FB approaches the target voltage corresponding to the lower one of the output soft start voltage V _SS2 and the second reference voltage V _REF2. Adjust the _PWM duty ratio.

The time until the frequency soft start voltage V _SS1 reaches the first reference voltage V _REF1 and the time until the output soft start voltage V _SS2 reaches the second reference voltage V _REF2 are preferably substantially equal.

  The above is the configuration of the control circuit 200A and the DC / DC converter 100A. Next, the operation will be described.

FIG. 4 is an operation waveform diagram of the DC / DC converter 100A of FIG. When the enable signal EN is asserted at time t ₀ , the frequency soft start voltage V _SS1 and the output soft start voltage V _SS2 begin to rise. Following the increase of the output soft start voltage _VSS2 , the output voltage _VOUT gradually increases. When the output soft-start voltage _{V SS2} at time _{t 1} reaches the second reference voltage _{V REF2,} thereafter, the output voltage _{V OUT} is stabilized at the target voltage _{V OUT (REF).}

Immediately after start-up, since the frequency soft start voltage V _SS1 is low, the oscillation frequency of the oscillator 260, that is, the switching frequency f _SW of the DC / DC converter 100A is low, and the PWM cycle T _SW is long. As the frequency soft start voltage V _SS1 increases, the switching frequency f _SW increases and the PWM cycle T _SW decreases.

The output soft start voltage V _SS2 reaches the second reference voltage V _REF2 almost at the same time as the time t ₁ . After time _{t 1,} the switching frequency _{f SW} is _the are stabilized to a value corresponding to the first reference voltage _{V REF1.}

The above is the operation of the DC / DC converter 100A.
In the soft start period T _SS , the switching frequency f _SW gradually increases, and the switching period T _SW that is the reciprocal thereof becomes shorter. That is, immediately after startup, in a state duty ratio is small increases the pulse signal S _PWM ratio of input and output voltage, the switching cycle T _SW is longer. This makes it possible to maintain the (on-time switching transistors M ₁₎ T _ON pulse width corresponding to the product of the duty ratio and the switching period T _P, the minimum pulse width T _MIN is greater than the state. As a result, pulse skip can be suppressed, and ripple and overshoot of the output voltage _VOUT can be suppressed.

The frequency soft start voltage V _SS1 that defines the switching frequency f _SW is substantially the same as the output soft start voltage V _SS2 that defines the output voltage V _OUT reaches the second reference voltage V _REF2. The voltage V _REF1 is reached. When the output voltage V _OUT is stabilized at the target voltage V _{OUT (REF)} , the load starts to operate. According to the first embodiment, after the output voltage V _OUT is stabilized, the switching frequency f _SW Can be stabilized.

The time when the frequency soft start voltage V _SS1 reaches the first reference voltage V _REF1 may be before the time when the output soft start voltage V _SS2 reaches the second reference voltage V _REF2 .

Further, by generating the two soft start voltages V _SS1 and V _SS2 so as to have a proportional relationship, the following advantages can be obtained. The duty ratio of the pulse signal _{S PWM} is increased in accordance with the output soft-start voltage _{V SS2,} the frequency _{f SW} of the pulse signal _{S PWM} increases in proportion to the frequency soft-start voltage _{V SS1,} frequency software that cycle _{T SW} It decreases in inverse proportion to the start voltage _VSS1 . Accordingly, the product of the pulse signal _{S PWM} duty ratio and the pulse period _{T SW,} i.e. it is possible to reduce variation of the pulse width _{T ON.}

FIG. 5 is another waveform diagram of the frequency soft start voltage _VSS1 . Upon activation start, when 0V (zero volts) starting frequency soft start voltage V _SS, there is a case where the switching frequency just after the start is low, PWM cycle T _SW is too long. Therefore, as shown in FIG. 5, the frequency soft start voltage V _SS1 may be fixed to a certain lower limit voltage V _MIN for a predetermined time T _{FIX after} the start of the soft start. In this case, the lower limit of the switching frequency at startup, in other words, the upper limit of the PWM cycle _TSW can be defined according to the lower limit voltage V _MIN . Even in this case, after the predetermined time T _FIX ends, the proportional relationship between the frequency soft start voltage V _SS1 and the output soft start voltage V _SS2 is maintained.

  The present invention is understood as the block diagram and cross-sectional view of FIG. 3 or extends to various apparatuses and methods derived from the above description, and is not limited to a specific configuration. Hereinafter, more specific configuration examples and examples will be described in order not to narrow the scope of the present invention but to help understanding and clarify the essence and operation of the present invention.

6A and 6B are circuit diagrams showing a configuration example of the voltage selection circuit 250. FIG. The voltage selection circuit 250 in FIG. 6A includes a first transistor Q ₂₁ to a third transistor Q ₂₃ . The first transistor _{Q 21} is a NPN bipolar transistor, one end (emitter) is connected to the RT terminal. The second transistor _{Q 22} and the third transistor _{Q 23} is a PNP bipolar transistor, one end thereof (the emitter) is grounded, the other ends thereof (collector) connected to a control terminal of the first transistor _{Q 21} (base) Is done. To the control terminal of the second transistor _{Q 22} (base) the first reference voltage _{V REF1} is applied, the frequency soft-start voltage _{V SS1} is applied to the control terminal of the third transistor _{Q 23.} The base of the first transistor _{Q 21} is biased by the resistor _{R 21} (or current source).

The lower of V _SS1 + V _BE and V _REF1 + V _BE appears at the base of the first transistor Q ₂₁ . The first transistor _{Q 21} operates as an emitter follower, the RT terminal, _{V BE} voltage lower than the base potential of the first transistor _{Q 21, i.e.,} a low one _min of _{V SS1} and _{V REF1 (V SS1, V REF1} ) Is applied. As a result, I _OSC = min (V _SS1 , V _REF1 ) / _RT is supplied to the oscillator.

Voltage selection circuit 250 of FIG. 6 (b), includes a 3-input error amplifier (op amp) EA1, the transistor _{Q 31.} One end of the transistor _{Q 31} (emitter) is connected to the RT terminal. The error amplifier EA1 has two non-inverting input terminals (+) and one inverting input terminal (-), and the lower one of the voltages of the two non-inverting input terminals (+) and the inverting input terminal (- ) Voltage error. The _{R T} resistor voltage selection circuit 250 forms a constant current source, the RT _terminal, appear low voltage of _{V SS1} and _{V REF1, the oscillator, I OSC = min (V SS1} , V REF1) / _RT is supplied.

  In FIGS. 6A and 6B, the bipolar transistor may be replaced with an FET. In this case, the base, emitter, and collector may be read as the gate, source, and drain.

FIG. 7 is a circuit diagram showing a configuration example of the soft start circuit 240. Soft start circuit 240 includes a slope voltage generation circuit 242, a voltage dividing circuit 244, and a switch 246. The slope voltage generation circuit 242 generates a slope voltage V _C41 that increases with time. For example, the slope voltage generation circuit 242 includes a capacitor C ₄₁ and a current source CS ₄₁ . One end of the capacitor _{C 41} is grounded. The current source CS ₄₁ becomes active in response to the assertion of the soft start start signal SS_START, and charges the capacitor C ₄₁ with a constant current. The slope voltage V _C41 generated in the capacitor C ₄₁ increases with a certain slope with time.

A voltage dividing circuit 244 including resistors R ₄₁ and R _{42 divides} the slope voltage V _C41 to generate a frequency soft start voltage V _SS1 . The switch 246 is provided in series with the voltage dividing circuit 244. During the soft start period, the switch 246 is on. The switch 246 is turned off after V _SS1 > V _REF1 is _satisfied . For example, the switch 246 can be controlled according to a soft start completion signal SS_END that notifies the completion of the soft start period T _SS . Thereby, after the switching frequency is stabilized after the soft start is completed, it is possible to prevent useless power from being consumed by the resistors R ₄₁ and R ₄₂ .

The slope voltage V _C41 may be used as the output soft start voltage V _SS2 . Alternatively, the slope voltage V _C41 may be _divided by another resistance voltage dividing circuit to generate the output soft start voltage V _SS2 . Regarding the generation of the two soft start voltages V _SS1 and V _SS2 , since the capacitor C ₄₁ and the current source CS ₄₁ can be shared, the circuit area can be reduced.

FIG. 8 is a circuit diagram showing a specific configuration example of the control circuit 200A. Current detecting circuit 270 during the on time of the switching transistor _{M 1,} detects the coil current flowing through the inductor _{L 1 I L} (the drain current _{I M1} of the switching transistor _{M 1} in other words), the current detection showing a drain current _{I M1} A signal _VCS is generated. Structure of the current detecting circuit 270 is not particularly limited, for example, the switching transistor to the drain current I _M1 by using the on-resistance of M ₁ may be detected, the drain current I _{M1 (or} coil current I _L) on the path of Alternatively, a sense resistor may be inserted to detect a voltage drop of the sense resistor. Current detection circuit 270 may detect the coil current I _L on the basis of the voltage across the inductor L _1.

The pulse modulator 210 is a peak current mode pulse width modulator. The pulse modulator 210 includes an error amplifier 212, a PWM comparator 214, a slope compensator 216, and a main logic 218. The error amplifier 212 amplifies an error between the lower one of the output soft start voltage V _SS2 and the second reference voltage V _REF2 and the feedback voltage V _FB to generate an error signal V _ERR . The error amplifier 212 may be composed of a three-input operational amplifier. The slope compensator 216 superimposes the slope signal V _SLOPE on the current detection signal V _CS from the current detection circuit 270.

PWM comparator 214, the error signal _{V ERR,} 'compares the current detection signal _{V CS'} current detection signal _{V CS} after the slope compensation when reaches the error signal _{V ERR,} asserts a reset signal _{S RESET} (e.g. high) To do. In response to the assertion of the reset signal S _RESET , the main logic 218 transitions the pulse signal S _PWM to a level (off level, for example, low) corresponding to the switching transistor M ₁ being turned off.

The oscillator 260 generates a set signal S _SET having a frequency corresponding to the current I _OSC . In response to the edge of the set signal S _SET , the main logic 218 causes the pulse signal S _PWM to transition to a level (on level, eg, high) corresponding to the switching transistor M ₁ being on. In the soft start period, the frequency of the set signal S _SET generated by the oscillator 260 is low and then increases with time.

Subsequently, a modified example related to the first embodiment will be described.
The soft start circuit 240 that generates the frequency soft start voltage V _SS1 and the soft start circuit 240 that generates the output soft start voltage V _SS2 may be independent and separate circuits.

  Further, the method of generating the soft start voltage (slope voltage) is not limited to the method of charging the capacitor. For example, the soft start circuit may be configured by a digital circuit, and may include, for example, a digital counter whose count value increases with time and a D / A converter that converts the count value into a soft start voltage.

(Second Embodiment)
FIG. 9 is a circuit diagram of a DC / DC converter 100B according to the second embodiment. In this embodiment, the frequency setting circuit 220B applies a frequency setting voltage V _RT that periodically varies with time to the RT terminal.

Frequency setting circuit 220B includes a spread spectrum circuit 280 and a voltage selection circuit 250. The spread spectrum circuit 280 generates a spread spectrum voltage V _SPS that periodically varies with time. The spread spectrum circuit 280 is inactive during the soft start period immediately after startup, and its output voltage V _SPS is held at a voltage level higher than the first reference voltage V _REF1 . The frequency setting circuit 220B applies a frequency setting voltage V _RT corresponding to the lower one of the first reference voltage V _REF1 and the spread spectrum voltage V _SPS to the RT terminal. For example the spectrum spreading circuit 280, SPSON signal asserted near the end timing of the soft-start period _{T SS} are input, the spectrum spreading circuit 280 in response to the assertion of SPSON signal becomes active.

The peak voltage V _PEAK of the spread spectrum voltage V _SPS is preferably lower than the first reference voltage V _REF1 . More preferably, the spread spectrum voltage V _SPS varies in a voltage range slightly lower than the first reference voltage V _REF1 .

The spread spectrum voltage V _SPS may be a triangular wave, a ramp wave, a sine wave, or another periodic waveform. The configuration of the spread spectrum circuit 280 is not particularly limited, and a known circuit that can generate a desired waveform can be used.

The spread spectrum circuit 280 can be switched between valid and invalid according to the enable signal SPS_EN. When disabled, the output voltage V _SPS of the spread spectrum circuit 280 is fixed at a level higher than the first reference voltage V _REF1 even after the SS_END signal is asserted. Thus, the first reference voltage _VREF1 is always applied to the RT terminal, and the spread spectrum function is invalidated.

The above is the configuration of the DC / DC converter 100B. Next, the operation will be described. FIG. 10 is an operation waveform diagram of the DC / DC converter 100B of FIG. If the time _{t 0} the enable signal EN is asserted, the output soft-start voltage _{V SS2} begins to rise. Following the increase of the output soft start voltage _VSS2 , the output voltage _VOUT gradually increases. When the output soft-start voltage _{V SS2} at time _{t 1} reaches the second reference voltage _{V REF2,} thereafter, the output voltage _{V OUT} is stabilized at the target voltage _{V OUT (REF).}

Prior to time t ₁ , the spread spectrum circuit 280 is inactive, and the output voltage V _SPS of the spread spectrum circuit 280 is fixed at a level higher than the first reference voltage V _REF1 . A reference voltage V _REF1 is applied. The switching frequency f _SW of the DC / DC converter 100B is fixed according to the first reference voltage V _REF1 .

Starting of the DC / DC converter 100B at time _{t 1} is completed, the soft start completion signal SS_END is asserted, will spread spectrum circuit 280 active, the RT terminal spectrum spectrum spreading circuit 280 generates spreading voltage V _SPS is applied. As a result, the switching frequency f _SW of the DC / DC converter 100B periodically varies in accordance with the spread spectrum voltage _VSPS . FIG. 11 is a diagram showing a voltage V _{RT at the} RT terminal in the control circuit 200B and an oscillation signal S _OSC (clock signal) generated by the oscillator 280.

  The above is the operation of the control circuit 200B. FIG. 12 is a diagram showing a noise spectrum in the control circuit 200B of FIG. (I) shows the spectrum when the spread spectrum circuit 280 is validated in the control circuit 200B of FIG. 9, and (ii) shows the spectrum when the spread spectrum circuit 280 is invalidated.

  As can be seen from FIG. 12, by enabling the spread spectrum circuit 280, the spectrum of the switching noise can be spread and the peak intensity can be suppressed.

  FIG. 13 is a circuit diagram showing a configuration example of the spread spectrum circuit 280. The spread spectrum circuit 280 is a triangular wave generation circuit.

The voltage source 282 generates an upper threshold value V _PEAK that defines the peak of the spread spectrum voltage V _SPS and a lower threshold value V _BOTTOM that defines the bottom. Charging and discharging circuit 284, charging of the capacitor _{C 51,} repeated discharge. The comparator 286 compares the voltage V _SPS of the capacitor C ₅₁ with the threshold voltages V _PEAK and V _BOTTOM . The charge / discharge circuit 284 is in a discharging state when the output of the comparator 286 is high, and is in a charging state when the output is low. The voltage source 282 outputs the lower threshold value V _BOTTOM when the output of the comparator 286 is high, and outputs the upper threshold value V _PEAK when the output of the comparator 286 is low.

The voltage source 282 includes a resistance voltage dividing circuit composed of resistors R _{51 to} R ₅₄ . By _{dividing the} reference voltage V _REF , the first reference voltage V _REF1 and the two threshold values V _PEAK and V _BOTTOM are generated. Thereby, the relationship of V _PEAK <V _REF1 is guaranteed. The switches SW _H and SW _L are turned on and off in a complementary manner according to the output of the comparator 286. When the switch SW _H is on, V _PEAK is output, and when the switch SW _L is on, V _BOTTOM is output.

The charge / discharge circuit 284 includes current mirror circuits CM ₅₁ and CM ₅₂ and a constant current source CS ₅₁ . The constant current source CS ₅₁ is turned on when the SPS_ON signal is asserted, and generates the reference current I _REF . The current mirror circuit CM ₅₁ copies the reference current I _REF generated by the constant current source CS ₅₁ to generate the charging current I _CHG . The current mirror circuit CM ₅₂ copies the reference current I _REF generated by the constant current source CS _{51 and} generates the discharge current I _DIS . The current mirror circuit CM ₅₂ operates when the output of the comparator 286 is high and stops when the output is low. When I _DIS > I _CHG holds and the output of the comparator 286 is high, the capacitor C ₅₁ is discharged with I _DIS −I _CHG , and when the output of the comparator 286 is low, the capacitor C ₅₁ is charged with I _CHG. The

According to this configuration, a spread spectrum voltage V _SPS as shown in FIG. 11 can be generated.

  14A and 14B are circuit diagrams showing a configuration example of the voltage selection circuit 250 of FIG. The voltage selection circuit 250 shown in FIGS. 14A and 14B can be configured similarly to the voltage selection circuit 250 shown in FIGS. 6A and 6B.

(Third embodiment)
FIG. 15 is a circuit diagram of a DC / DC converter 100C according to the third embodiment. The DC / DC converter 100C can be grasped as a combination of the first embodiment and the second embodiment.

The frequency setting circuit 220C applies a frequency setting voltage _VRT, which gradually rises with time when the DC / DC converter 100C starts up, and then periodically changes with time to the RT terminal.

  The frequency setting circuit 220C includes a soft start circuit 240, a spread spectrum circuit 280, and a voltage selection circuit 250C.

The soft start circuit 240 generates the frequency soft start voltage V _SS1 and the output soft start voltage V _SS2 in the same manner as described in the first embodiment. The voltage selection circuit 250C receives the first reference voltage V _REF1 , the spread spectrum voltage V _SPS , and the frequency soft start voltage V _SS1 , and applies the frequency setting voltage V _RT corresponding to the lowest one of them to the RT setting terminal. .

  The above is the configuration of the control circuit 200C. Next, the operation will be described. FIG. 16 is an operation waveform diagram of the DC / DC converter 100C of FIG.

When the enable signal EN is asserted at time t ₀ , the frequency soft start voltage V _SS1 and the output soft start voltage V _SS2 begin to rise. Following the increase of the output soft start voltage _VSS2 , the output voltage _VOUT gradually increases.

Further, the switching frequency f _SW rises following the rise of the frequency soft start voltage V _SS1 . In other words, since the switching frequency f _SW immediately after the start of operation is lowered, it is possible to suppress the occurrence of pulse skip due to the pulse width of the pulse signal S _PWM becoming too narrow.

When the output soft-start voltage _{V SS2} at time _{t 1} reaches the second reference voltage _{V REF2,} thereafter, the output voltage _{V OUT} is stabilized at the target voltage _{V OUT (REF).} Then, the SS_END signal indicating the end of the soft start period is asserted. As a result, the spread spectrum voltage V _SPS is applied to the RT terminal and periodically fluctuates. The switching frequency f _SW varies following the frequency setting voltage V _RT .

  The above is the operation of the control circuit 200C. According to this, both of the advantages of the first embodiment and the second embodiment can be enjoyed. Further, since the voltage selection circuit 250 can be shared as hardware, an increase in circuit area can be suppressed.

FIG. 17 is a circuit diagram illustrating a configuration example of the voltage selection circuit 250. The voltage selection circuit 250C includes a first transistor Q ₄₁ to a fourth transistor Q ₄₄ . The emitter of the first transistor _{Q 41} is connected to the RT terminal. The emitters of the second transistor Q ₄₂ to the fourth transistor Q ₄₄ are connected in common with the base of the first transistor Q ₄₁ , and their sources are grounded. A first reference voltage V _REF1 is applied to the base of the second transistor Q _42, a spread spectrum voltage V _SPS is applied to the base of the third transistor Q ₄₃ , and a frequency soft start voltage is applied to the base of the fourth transistor Q _44. V _SS1 is applied.

According to this configuration, the lowest voltage among the three voltages V _SS1 , V _SPS , and V _REF1 can be applied to the RT terminal.

(Use)
FIG. 18 is a block diagram of the in-vehicle electrical equipment 300 including the DC / DC converter 100. In-vehicle electrical equipment 300 includes a battery 302, a microcomputer 304, and a load 306 in addition to the DC / DC converter 100. The battery 302 generates a battery voltage V _BAT of 12V (or 24V), for example. The DC / DC converter 100 receives the battery voltage V _BAT as the input voltage _VIN , and generates an output voltage _VOUT having an optimum voltage level for the load 306. The load 306 is not particularly limited, and various ECUs (Electronic Control Units), audio circuits, car navigation systems, and the like are exemplified. The microcomputer 304 is a host processor that controls the in-vehicle electrical equipment 300 in an integrated manner, and outputs an EN signal to the control circuit 200. When the FLG terminal of the control circuit 200 is monitored and an abnormality that occurs in the control circuit 200 is detected, an appropriate protection process is executed.

  Since many electronic components are mounted on a vehicle such as an automobile, strict EMC is required for the in-vehicle electrical equipment 300. According to DC / DC converter 100 according to the embodiment, it is possible to clear the standards required for in-vehicle electrical equipment 300.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

There are various variations in the configuration and topology of the output circuit 110. The high-side switching transistor of the DC / DC converter may be an N-channel MOSFET. Further, the switching transistor M ₁ and the synchronous rectification transistor M ₂ may be externally attached to the control circuit 200. The present invention is also applicable to DC / DC diode rectification type including a rectifying diode in place of the synchronous rectification transistor M ₂ (Schottky diode) is applicable.

  The DC / DC converter is not limited to a step-down type, and the present invention can be applied to a step-up type and a step-up / step-down type. The present invention can also be applied to a converter using a transformer such as a flyback converter.

Although the embodiment has been described when the switching transistor M ₁ and the synchronous rectification transistor M ₂ is an MOSFET, the present invention is not limited thereto, may be IGBT (Insulated Gate Bipolar Transistor).

The resistors R ₁₁ and R ₁₂ may be externally attached to the control circuit 200.

  The application of the DC / DC converter 100 is not limited to in-vehicle electrical equipment, but can also be used for small electronic equipment and computers.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

100 ... DC / DC converter, 102 ... input terminal, 104 ... output terminal, 110 ... output circuit, M 1 _... switching transistor, M 2 _... synchronous rectification transistor, L 1 _... inductor, C 1 _... output capacitor, 200 ... control circuit , 210 ... Pulse modulator, 212 ... Error amplifier, 214 ... PWM comparator, 216 ... Slope compensator, 218 ... Main logic, 220 ... Frequency setting circuit, 230 ... Driver, 240 ... Soft start circuit, 242 ... Slope voltage generation circuit 244 ... Voltage dividing circuit, 246 ... Switch, 250 ... Voltage selection circuit, 260 ... Oscillator, 270 ... Current detection circuit, _SPWM ... Pulse signal, 280 ... Spread spectrum circuit, 300 ... In-vehicle electrical equipment, 302 ... Battery, 304 ... microcomputer, 306 ... load.

Claims (13)

A control circuit for a DC / DC converter,
A frequency setting terminal to which an external resistor defining the switching frequency is to be connected;
A soft start circuit for generating a frequency soft start voltage that gradually increases with time when the DC / DC converter is activated;
A voltage selection circuit for applying a frequency setting voltage corresponding to a lower one of the first reference voltage and the frequency soft start voltage to the frequency setting terminal;
An oscillator that oscillates at a frequency corresponding to the current flowing through the external resistor;
A pulse modulator that generates a pulse signal having a frequency corresponding to a periodic signal generated by the oscillator and having a duty ratio adjusted so that an output signal of the DC / DC converter approaches a target voltage;
A control circuit comprising: At the start of the DC / DC converter, the target voltage depends on the lower one of the output soft start voltage and the second reference voltage that gradually increase with time,
The control circuit according to claim 1, wherein the frequency soft start voltage and the output soft start voltage are in a proportional relationship.   The control circuit according to claim 2, wherein the output soft start voltage is a constant voltage for a predetermined time from the start of startup.   3. The time until the frequency soft start voltage reaches the first reference voltage is substantially equal to the time until the output soft start voltage reaches the second reference voltage. Or the control circuit of 3. The soft start circuit
A slope voltage generation circuit for generating a slope voltage that increases with time;
A voltage dividing circuit for dividing the slope voltage to generate the frequency soft start voltage;
A switch provided in series with the voltage dividing circuit;
The control circuit according to claim 1, further comprising: The voltage selection circuit includes:
A first transistor having one end connected to the frequency setting terminal;
A second transistor having one end connected to the control terminal of the first transistor, the other end grounded, and the first reference voltage applied to the control terminal;
A third transistor having one end connected to the control terminal of the first transistor, the other end grounded, and the frequency soft start voltage applied to the control terminal;
The control circuit according to claim 1, comprising: The voltage selection circuit includes:
A first transistor having one end connected to the frequency setting terminal;
A first non-inverting input receives the frequency soft start voltage, a second non-inverting input receives the first reference voltage, an inverting input is connected to the frequency setting terminal, and an output is a control terminal of the first transistor. A first error amplifier connected to
The control circuit according to claim 1, comprising: A control circuit for a DC / DC converter,
A frequency setting terminal to which an external resistor defining the switching frequency is to be connected;
A frequency setting circuit that applies a frequency setting voltage that gradually increases with time and maintains a constant value to the frequency setting terminal at the time of starting the DC / DC converter;
An oscillator that oscillates at a frequency corresponding to the current flowing through the external resistor;
A pulse modulator that generates a pulse signal having a frequency corresponding to a periodic signal generated by the oscillator and having a duty ratio adjusted so that an output signal of the DC / DC converter approaches a target voltage;
A control circuit comprising:   9. The control circuit according to claim 1, wherein the pulse modulator is a peak current mode modulator.   10. The control circuit according to claim 1, wherein the control circuit is integrated on a single semiconductor substrate.   A DC / DC converter comprising the control circuit according to claim 1.   An in-vehicle electrical equipment comprising the DC / DC converter according to claim 11. A method for controlling a DC / DC converter, comprising:
Generating a frequency soft start voltage that gradually rises with time at the start of the DC / DC converter;
Applying a frequency setting voltage corresponding to a lower one of the first reference voltage and the frequency soft start voltage to a resistor defining a switching frequency;
Generating a periodic signal having a frequency corresponding to a current flowing through the resistor;
Generating a pulse signal having a frequency corresponding to the periodic signal and having a duty ratio adjusted so that an output signal of the DC / DC converter approaches a target voltage;
Driving a switching transistor of the DC / DC converter in response to the pulse signal;
A control method comprising:

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