JP2017093159A - Step-down dc/dc converter and control circuit, control method therefor, on-vehicle power supply device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress overshoot.SOLUTION: A pulse generator 202 generates a high side pulse S1 so that the output voltage Vapproaches a target value V. An error amplifier 400 amplifies the error of a voltage detection signal Vcorresponding to the output voltage Vand its target value V, and generates a feedback signal V. A pulse width modulator 402 outputs a high side pulse S1 having a duty ratio corresponding to the feedback signal V. When the output voltage Vexceeds a threshold voltage determined higher than its target value V, in the enable state, an overshoot suppression circuit 410 lowers the feedback signal Voutputted from the error amplifier 400, and sets the high side pulse S1 to off level.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a step-down DC / DC converter.

In various electronic devices, a DC / DC converter that converts a DC voltage of one voltage value into a DC voltage of another voltage value is used. FIG. 1 is a circuit diagram of a step-down (Buck) DC / DC converter. The DC / DC converter 100R receives the DC input voltage _VIN at the input terminal 102 and generates the output voltage _VOUT stepped down at the output terminal 104. The DC / DC converter 100R includes an output circuit 110 and a control circuit 200R. The output circuit 110R mainly includes a switching transistor M1, an inductor L1, a rectifier diode D1, and an output capacitor C1. The output capacitor C1 is connected to the output terminal 104. One end of the inductor L1 is connected to the switching (LX) terminal of the control circuit 200R, and the other end is connected to the output terminal 104. The anode of the rectifier diode D1 is grounded, and its cathode is connected to the LX terminal.

The switching transistor M1 is built in the control circuit 200R. The VCC terminal of the control circuit 200R is connected to the input terminal 102 and supplied with a DC input voltage _VIN . The switching transistor M1 is an N-channel MOSFET, its source is connected to the LX terminal, and its drain is connected to the VCC terminal.

A signal indicating the state (current, voltage, power, etc.) of a load (not shown) connected to the DC / DC converter 100R or the output terminal 104 is fed back to the detection terminal (VS). The pulse generator 202R generates a pulse signal (high-side pulse) S1 in which the duty ratio, the frequency, or a combination thereof changes so that the DC / DC converter 100R or the load state approaches the target state. For example, in the DC / DC converter 100R with constant voltage output, the pulse generator 202R generates the high side pulse S1 so that the voltage detection signal V _S corresponding to the output voltage V _OUT approaches the target value V _REF .

The driver 204 switches the switching transistor M1 based on the high side pulse S1. When an N-channel transistor is used as the switching transistor M1 as described above, in order to turn it on, it is necessary to apply a voltage higher than the drain and source voltages (that is, the input voltage V _IN ) to the gate of the switching transistor M1. For this purpose, a bootstrap circuit 210 is provided. The bootstrap circuit 210 includes a bootstrap capacitor C2, a rectifier element 212, a transistor 214, and a bootstrap power supply circuit 220. The bootstrap capacitor C2 is externally connected between the LX terminal and the bootstrap (BST) terminal. The bootstrap power supply circuit 220 generates a constant voltage V _CCBST . The rectifying element 212 is provided between the BST terminal and the output of the bootstrap power supply circuit 220. The transistor 214 is provided between the LX terminal and the ground. The BST terminal voltage V _BST is supplied to the upper power supply terminal of the driver 204.

While the switching transistor M1 is off, the transistor 214 is on and one end (LX side) of the bootstrap capacitor C2 is grounded. In this state, the other end of bootstrap capacitor C2 (BST side), the voltage _{V CCBST} applied through the rectifying element 212, across the bootstrap capacitor C2 _is charged with _{V CCBST} -V _F. V _F is a forward voltage of the rectifying element 212. Here, V _CCBST −V _F > V _{GS (TH)} is satisfied. V _{GS (TH)} is a gate-source threshold voltage of the switching transistor M1.

When the source voltage of the switching transistor M1 is V _LX during the turn-on period of the switching transistor M1, the voltage V _{BST at the} BST terminal is V _BST = V _LX + (V _CCBST −V _F ). The driver 204 applies this voltage V _BST as a high level voltage to the gate of the switching transistor M1. At this time, the gate-source voltage V _GS of the switching transistor M1 becomes V _GS = V _BST −V _LX = (V _CCBST −V _F ), and V _GS > V _{GS (TH)} , so that the switching transistor M1 is turned on. .

The pulse generator 202R includes an error amplifier 400 and a pulse width modulator 402. The error amplifier 400 amplifies an error between the voltage detection signal V _S and its target value V _REF to generate a feedback signal V _FB . For example, the error amplifier 400 may include a transconductance amplifier gm and a phase compensation resistor and capacitor. The pulse width modulator 402 generates a PWM signal having a duty ratio corresponding to the feedback signal _VFB , and outputs a high side pulse S1 corresponding to the PWM signal.

JP 2011-014738 A

As a result of studying the DC / DC converter 100R of FIG. 1, the present inventors have recognized the following problems. FIG. 2 is an operation waveform diagram of the DC / DC converter 100R of FIG. Prior to time t0, the DC / DC converter 100R is supplied with an input voltage V _IN (for example, 12V) that is sufficiently higher than the target value V _{OUT (REF)} (for example, 5V) of the output voltage V _OUT . The switching duty ratio D of the switching transistor M1 in the steady state is determined according to a target value V _{REF (REF)} ratio between the input voltage V _IN and the output voltage V _OUT . In a steady state, the feedback signal V _FB is stabilized at a voltage level V _{1 at} which this duty ratio D is obtained.
D = V _{OUT (REF)} / V _IN

At time t0, the input voltage _VIN changes and drops to 5 V (or lower) near the output voltage target value _{VOUT (REF)} (lower voltage state). In a general DC / DC converter control circuit, an upper limit (maximum duty ratio D _MAX ) of the duty ratio of the high side pulse S1 is set, and the duty ratio of the pulse signal S1 is within a range not exceeding the maximum duty ratio D _MAX. Be controlled. In particular, in the bootstrap type converter, since the off period of the high side pulse S1 is required to charge the voltage of the bootstrap capacitor C2, the maximum duty ratio D _MAX is important. For example, the maximum duty ratio D _MAX is defined to be about 90%.

In a state close to the input voltage V _IN and the target value V _{OUT (REF)} , the output voltage V _OUT is kept at V _IN × D _MAX (= 5 V × 0.9 = 0.45 V), and the target value V _{OUT (REF)} cannot be maintained. At this time, the feedback signal V _FB is stuck to the voltage level V ₂ that is the power supply voltage of the error amplifier 400, and is in a state where feedback is not substantially applied.

At time t1, the input voltage _VIN returns to the normal voltage level (12V). Then, the feedback signal V _FB starts to decrease toward the original voltage level V ₁ . Since the speed at which the feedback voltage V _FB changes is limited by the phase compensation capacity or the like, a delay time occurs until the feedback voltage V _FB reaches the original voltage level V ₁ . Due to this response delay, a PWM signal having a duty ratio larger than the duty ratio determined by V _{OUT (REF)} / V _IN is generated, and as a result, the output voltage _VOUT overshoots.

  Such a problem may occur not only in a DC / DC converter in which the switching transistor M1 is an N-channel MOSFET but also in a P-channel MOSFET converter.

  SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and one of exemplary purposes of an embodiment thereof is to provide a step-down DC / DC converter or a control circuit thereof capable of suppressing overshoot.

  One embodiment of the present invention relates to a control circuit for a step-down DC / DC converter having a switching transistor. The control circuit includes a pulse generator that generates a high-side pulse that instructs on / off of the switching transistor so that the output voltage of the DC / DC converter approaches a target value, a driver that drives the switching transistor based on the high-side pulse, Is provided. The pulse generator amplifies the error between the voltage detection signal corresponding to the output voltage and its target value, generates an error amplifier that generates a feedback signal, and generates a PWM (Pulse Width Modulation) signal having a duty ratio according to the feedback signal And a pulse width modulator that outputs a high-side pulse in accordance with the PWM signal, and a threshold voltage that can be switched between an enable state and a disable state, and in which the output voltage is higher than the target value in the enable state. Exceeding the above, a feedback signal output from the error amplifier is reduced, and an overshoot suppression circuit that turns off the high-side pulse is included.

  When an overshoot occurs in the enable state of the overshoot suppression circuit, the high side pulse is immediately turned off and further voltage increase is suppressed. Further, when overshoot occurs, the feedback signal is forcibly lowered, so that it can be brought close to an appropriate duty ratio in a short time, and overshoot can be suppressed.

  In one aspect, the pulse generator may further include a determination circuit that switches a state of the overshoot suppression circuit based on a state of the step-down DC / DC converter.

  The determination circuit may enable the overshoot suppression circuit when the PWM signal exceeds a predetermined maximum duty ratio. When the PWM signal exceeds a predetermined maximum duty ratio, it can be said that overshoot is likely to occur, which is suitable for operating the overshoot suppression circuit.

  The determination circuit may enable the overshoot suppression circuit in the reduced voltage state of the step-down DC / DC converter. The reduced voltage state includes a state where the difference between the target value of the input voltage and the output voltage is smaller than a predetermined value. Since it can be said that overshoot is likely to occur in the reduced voltage state, it is suitable as a situation where the overshoot suppression circuit is operated.

  Alternatively, the overshoot suppression circuit may be switched between the enable state and the disable state according to a control signal from the outside of the control circuit.

  The overshoot suppression circuit may include a switch provided between the output terminal of the error amplifier and the ground. By turning on the switch, the capacitor connected to the output of the error amplifier can be discharged, and the feedback signal can be lowered.

  The overshoot suppression circuit may include a comparator that compares a voltage corresponding to the output voltage with a predetermined threshold voltage.

  The pulse width modulator may include an off signal generation unit that generates an off signal serving as a trigger for transitioning the high side pulse to an off level. The overshoot suppression circuit may be enabled when a cycle in which the off signal is not asserted is detected.

  The overshoot suppression circuit may be enabled after a predetermined number of cycles in which the off signal is not asserted.

  The overshoot suppression circuit may be enabled when the duty ratio of the PWM signal or the high side pulse is larger than a predetermined maximum duty ratio.

  The pulse width modulator includes an oscillator that generates an ON signal that is asserted every predetermined period, a PWM comparator that generates an OFF signal that is asserted when a current detection signal indicating a current flowing through the switching transistor reaches a feedback signal, And a logic circuit that generates a PWM signal whose level changes in response to an on signal and an off signal. The overshoot suppression circuit may be enabled when a cycle in which the off signal is not asserted is detected.

  The pulse width modulator may include an oscillator that generates a periodic signal that is one of a triangular wave, a sawtooth wave, and a ramp wave, and a PWM comparator that compares the feedback signal with the periodic signal. The overshoot suppression circuit may be enabled when a cycle in which the output signal of the PWM comparator does not transition is detected.

  The switching transistor is an N-channel transistor, and the control circuit may further include a bootstrap circuit that charges the bootstrap capacitor. The pulse generator includes a mode controller that detects a state in which the high-side pulse does not transition to the off-level for one cycle. When the state is detected, the pulse generator shifts to the skip mode. The first period in which the high side pulse is maintained at the on level and the second period in which (ii) the high side pulse is forcibly shifted to the off level and the bootstrap capacitor is charged by the bootstrap circuit are repeated.

  The overshoot suppression circuit may become active when the skip mode is entered.

  The control circuit of a certain aspect may be integrated on a single semiconductor substrate. “Integrated integration” includes the case where all of the circuit components are formed on a semiconductor substrate and the case where the main components of the circuit are integrated. A resistor, a capacitor, or the like may be provided outside the semiconductor substrate.

  Another aspect of the present invention relates to a step-down DC / DC converter. The step-down DC / DC converter includes any of the control circuits described above.

  Yet another embodiment of the present invention relates to an in-vehicle power supply device. The in-vehicle power supply device includes the step-down DC / DC converter described above.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, overshoot can be suppressed in a step-down DC / DC converter.

It is a circuit diagram of a step-down DC / DC converter. FIG. 2 is an operation waveform diagram of the DC / DC converter of FIG. 1. 1 is a circuit diagram of a step-down DC / DC converter according to a first embodiment. FIG. 4 is an operation waveform diagram of the DC / DC converter of FIG. 3. It is a circuit diagram of the 1st example of composition of a pulse generator. It is a circuit diagram of the 2nd example of composition of a pulse generator. It is a circuit diagram of the 3rd example of composition of a pulse generator. It is a circuit diagram of a DC / DC converter provided with the control circuit which concerns on 2nd Embodiment. FIG. 9 is an operation waveform diagram of the DC / DC converter of FIG. 8. It is a circuit diagram of the 1st structural example of the control circuit of FIG. It is a circuit diagram of the 2nd example of composition of a control circuit. FIG. 12 is an operation waveform diagram of the control circuit of FIG. 11. It is a circuit diagram of the 3rd example of composition of a control circuit. FIGS. 14A and 14B are circuit diagrams of pulse modulators according to first and second modifications. It is a circuit diagram of a vehicle-mounted power supply device.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  “Signal A (voltage, current) is in response to signal B (voltage, current)” means that signal A has a correlation with signal B. Specifically, (i) signal A Is signal B, (ii) signal A is proportional to signal B, (iii) signal A is obtained by level shifting signal B, and (iv) signal A is obtained by amplifying signal B. If (v) signal A is obtained by inverting signal B, it means (vi) or any combination thereof. It will be understood by those skilled in the art that the “depending” range is determined depending on the type and application of the signals A and B.

(First embodiment)
FIG. 3 is a circuit diagram of the step-down DC / DC converter (simply DC / DC converter) 100 according to the first embodiment. As in FIG. 1, the DC / DC converter 100 receives the DC input voltage _VIN at the input terminal 102, and generates a stepped down output voltage _VOUT at the output terminal 104. The DC / DC converter 100 includes an output circuit 110 and a control circuit 200. In this embodiment, a DC / DC converter with a constant voltage output will be described as an example.

The output circuit 110 includes resistors R11 and R12 in addition to the output circuit 110R of FIG. Resistors R11, R12, the voltage detection (VS) supplied to the terminal of the control circuit 200 of the voltage detection signal _{V S} obtained an output voltage _{V OUT} to be controlled divide. The resistors R11 and R12 may be built in the control circuit 200.

  The control circuit 200 includes a pulse generator (also referred to as a pulse modulator) 202, a driver 204, and a bootstrap circuit 210 in addition to the switching transistor M1, which is an N-channel MOSFET, and is a function integrated on a single semiconductor substrate. IC (Integrated Circuit). The drain of the switching transistor M1 is connected to the VCC terminal, and the source is connected to the LX terminal.

Specifically, the pulse generator 202 generates a voltage detection signal V _S corresponding to the output voltage V _OUT so that the voltage V _{OUT at} the output terminal 104 of the DC / DC converter 100 approaches the target value V _{OUT (REF).} A pulse signal (also referred to as a high-side pulse) S1 whose duty ratio, frequency, or a combination thereof changes so as to approach the target value _VREF is generated. The pulse generator 202 generates a low-side pulse S2 for controlling the transistor 214. The low side pulse S2 may be a complementary signal of the high side pulse S1. Further, a dead time may be inserted so as to prevent the switching transistor M1 and the transistor 214 from being simultaneously turned on.

  A known technique may be used for the pulse generator 202, and its control method and configuration are not particularly limited. As a control method, a voltage mode, a peak current mode, an average current mode, a hysteresis control (Bang-Bang control), a bottom detection on-time fixed (COT: Constant On Time) method, or the like can be adopted. Further, as a modulation method of the high side pulse S1, pulse width modulation, pulse frequency modulation, or the like can be adopted.

The driver 204 switches the switching transistor M1 based on the high side pulse S1. When an N-channel transistor is used as the switching transistor M1 as described above, in order to turn it on, it is necessary to apply a voltage higher than the drain and source voltages (that is, the input voltage V _IN ) to the gate of the switching transistor M1. For this purpose, a bootstrap circuit 210 is provided. The configuration of the bootstrap circuit 210 is as described with reference to FIG. The bootstrap power supply circuit 220 generates a constant voltage V _CCBST . The rectifying element 212 is provided between the BST terminal and the output of the bootstrap power supply circuit 220. The transistor 214 is provided between the LX terminal and the ground. A voltage V _{BST of the} BST terminal is supplied to the upper power supply terminal of the driver 204, and the lower power supply terminal is connected to the LX terminal. The driver 216 turns on the transistor 214 in response to the low-side pulse S2 during the charging period of the bootstrap capacitor C2.

While the switching transistor M1 is off, the transistor 214 is on and one end (LX side) of the bootstrap capacitor C2 is grounded. In this state, the other end of bootstrap capacitor C2 (BST side), the voltage _{V CCBST} applied through the rectifying element 212, across the bootstrap capacitor C2 _is charged with _{V CCBST} -V _F. V _F is a forward voltage of the rectifying element 212. Here, V _CCBST −V _F > V _{GS (TH)} is satisfied. V _{GS (TH)} is a gate-source threshold voltage of the switching transistor M1. As the rectifying element 212, a switch that is switched on and off in synchronization with the switching transistor M1 may be used.

When the source voltage of the switching transistor M1 is V _LX during the turn-on period of the switching transistor M1, the voltage V _{BST at the} BST terminal is V _BST = V _LX + (V _CCBST −V _F ). The driver 204 applies this voltage V _BST as a high level voltage to the gate of the switching transistor M1. At this time, the gate-source voltage V _GS of the switching transistor M1 becomes V _GS = V _BST −V _LX = (V _CCBST −V _F ), and V _GS > V _{GS (TH)} , so that the switching transistor M1 is turned on. .

The pulse generator 202 includes an error amplifier 400, a pulse width modulator 402, and an overshoot suppression circuit 410. The error amplifier 400 amplifies an error between the voltage detection signal V _S and its target value V _REF to generate a feedback signal V _FB . For example, the error amplifier 400 may include a transconductance amplifier gm, a phase compensation resistor, and a capacitor, but the configuration is not particularly limited, and an error amplifier with another configuration may be used. The pulse width modulator 402 generates a PWM signal having a duty ratio corresponding to the feedback signal _VFB , and outputs a high side pulse S1 corresponding to the PWM signal.

  The overshoot suppression circuit 410 can switch between the enable state and the disable state in accordance with the enable signal S5. The enable signal S5 may be received from outside the control circuit 200 or may be generated inside the control circuit 200.

In the enable state, the overshoot suppression circuit 410 forcibly lowers the feedback signal _VFB when the output voltage _VOUT exceeds a threshold voltage V _OVP that is set higher than its target value V _{OUT (REF)} . The high side pulse S1 is turned off. For example, the threshold voltage V _OVP is desirably a voltage that is several percent (10% or less) higher than the target value V _{OUT (REF)} . It should be noted that the threshold value for general overvoltage protection is set to a level several tens of percent higher than the target value _{VOUT (REF)} .

The configuration of the overshoot suppression circuit 410 is not particularly limited. For example, the overshoot suppression circuit 410 includes a switch 412 and a comparator 414. The comparator 414, a signal (voltage detection signal _{V S)} corresponding to the output voltage _{V OUT,} compared to the threshold voltage _{V TH} corresponding to the threshold voltage _{V OVP,} output S6 when V _{S> V OVP} Assert (high level). The switch 412 is provided between the output terminal of the error amplifier 400 and the ground, and is turned on when the output S6 of the comparator 414 is asserted. The output S6 of the comparator 414 is input to the pulse width modulator 402, and the pulse width modulator 402 transitions the high side pulse S1 to the off level in response to the assertion of the signal S6.

A method for switching the enable state and the disable state of the overshoot suppression circuit 410 is not particularly limited. For example, in the overshoot suppression circuit 410 of FIG. 3, the output S6 of the comparator 414 may be fixed at a low level in order to realize the disabled state. Alternatively, the comparator 414 may be stopped. Alternatively, the threshold voltage V _TH input to the comparator 414 may be set to a very high value.

If the overshoot suppression circuit 410 is always enabled, even if the output voltage _VOUT increases due to factors such as load fluctuations, the feedback signal _VFB decreases and the switching transistor M1 is forced off, which is not preferable. Therefore, it is desirable that the overshoot suppression circuit 410 is enabled in a situation where overshoot is likely to occur.

  The pulse generator 202 may further include a determination circuit 420 that switches the state of the overshoot suppression circuit 410. The determination circuit 420 may determine a situation in which overshoot is likely to occur based on the state of the step-down DC / DC converter 100, and may switch the overshoot suppression circuit 410.

  For example, the determination circuit 420 may enable the overshoot suppression circuit 410 when the PWM signal exceeds a predetermined maximum duty ratio. When the PWM signal exceeds a predetermined maximum duty ratio, it can be said that overshoot is likely to occur, which is suitable for operating the overshoot suppression circuit.

Alternatively, the determination circuit 420 may enable the overshoot suppression circuit 410 in a reduced voltage state where the input voltage _VIN to the step-down DC / DC converter 100 is low. Since it can be said that an overshoot is likely to occur in the reduced voltage state, it is suitable as a situation where the overshoot suppression circuit 410 is operated.

In addition, even when the output voltage V _OUT (voltage detection signal V _S ) changes, the determination circuit 420 may enable the overshoot suppression circuit 410 in a situation where the change is not reflected in the duty ratio of the PWM signal.

  The above is the configuration of the control circuit 200 according to the first embodiment. Next, the operation will be described. FIG. 4 is an operation waveform diagram of the DC / DC converter 100 of FIG. The vertical axis and horizontal axis of the waveform diagrams and time charts in this specification are appropriately expanded and reduced for easy understanding, and each waveform shown is also simplified for easy understanding. Or it is exaggerated or emphasized.

Prior to time t0, the DC / DC converter 100 is supplied with an input voltage V _IN (eg, 12V) that is sufficiently higher than the target value V _{OUT (REF)} (eg, 5V) of the output voltage V _OUT . The switching duty ratio D of the switching transistor M1 at this time is determined according to the target value V _{REF (REF)} ratio between the input voltage V _IN and the output voltage V _OUT . The feedback signal V _FB is stabilized at a voltage level V _{1 at} which this duty ratio D is obtained.
D = V _{OUT (REF)} / V _IN

At time t0, the input voltage _VIN changes and drops to 5 V (or lower) near the output voltage target value _{VOUT (REF)} (lower voltage state). At this time, the output voltage V _OUT is maintained at V _IN × D _MAX (= 5 V × 0.9 = 0.45 V), and the target value V _{OUT (REF)} cannot be maintained. At this time, the feedback signal V _FB is stuck to the voltage level V ₂ that is the power supply voltage of the error amplifier 400, and is in a state where feedback is not substantially applied. In this state, the determination circuit 420 asserts the enable signal S5, enables the overshoot suppression circuit 410, and prepares for an overshoot that will eventually appear.

At time t1, the input voltage _VIN returns to the normal voltage level (12V). Then, the feedback signal V _FB starts to decrease toward the original voltage level V ₁ . Due to the response delay of the feedback system, a PWM signal having a duty ratio larger than the duty ratio determined by V _{OUT (REF)} / V _IN is generated, and as a result, the output voltage _VOUT overshoots. Whenever the output voltage V _OUT exceeds the threshold voltage V _OVP , the signal S6 is asserted and the switch 412 is turned on, so that the feedback signal V _FB quickly decreases. Further, the switching transistor M1 which is going to be turned on with the maximum duty ratio is immediately turned off.

The above is the operation of the control circuit 200. Thus, by providing the overshoot suppression circuit 410, the overshoot of the output voltage _VOUT can be suppressed more than the waveform diagram of FIG. Further, the time until the output voltage V _OUT is stabilized at the target value V _{OUT (REF)} can be shortened.

  The present invention is understood as the block diagram and circuit diagram of FIG. 3 or extends to various devices and circuits derived from the above description, and is not limited to a specific configuration. Hereinafter, more specific configuration examples will be described in order not to narrow the scope of the present invention but to help understanding and clarify the essence and circuit operation of the present invention.

FIG. 5 is a circuit diagram of a first configuration example 202 d of the pulse generator 202. In the pulse generator 202d, the pulse width modulator 402d includes an on signal generation unit 242, an off signal generation unit 244, a maximum duty ratio setting unit 245, and a logic circuit 246. ON signal generating unit 242 generates an on signal S _ON that trigger turn-on of the switching transistor M1. The off signal generation unit 244 generates an off signal S _OFF that serves as a trigger for turning off the switching transistor M1. The maximum duty ratio setting unit 245 generates a pulse signal S _MAXDUTY having an edge at a position corresponding to the maximum duty ratio D _MAX . The logic circuit 246 generates the high side pulse S1 based on the _ON signal S _ON and the OFF signal S _OFF . The logic circuit 246 may include an SR flip-flop (or latch) 260 that responds to the on signal S _ON and the off signal S _OFF . The OR gate 261 _calculates the logical sum of the off signal S _OFF , the pulse signal S _MAXDUTY , and the signal S 6 from the overshoot suppression circuit 410 and supplies it to the reset terminal of the flip-flop 260. As a result, during normal operation, the duty ratio of the PWM signal S _PMW is limited to the maximum duty ratio D _MAX or less. When the signal S6 is asserted, the PWM signal _SPWM immediately transitions to the off level.

Decision circuit 420d monitors the off signal _{S OFF,} detects a cycle off signal _{S OFF} is not asserted, the overshoot suppression circuit 410 and the enable state. As a result, it is possible to detect a state where the switching transistor M1 switches at the maximum duty ratio or a reduced voltage state. Preferably, the determination circuit 420d may assert the enable signal S5 when a predetermined number of cycles in which the off signal S _OFF is not asserted last.

FIG. 6 is a circuit diagram of a second configuration example 202 e of the pulse generator 202. The pulse generator 202e includes a peak current mode pulse width modulator 402e. Oscillator 258 generates a PWM (pulse width modulation) clock PWMCLK defining the PWM period (switching period) _{T P.} Oscillator 258, corresponding to the ON signal generating unit 242 of FIG. 5, PWM clock PWMCLK is grasped as on signal _{S ON.}

The current sense amplifier 252 generates a current detection signal V _IS indicating the current I _M1 flowing through the switching transistor M1. The slope compensator 254 superimposes the slope signal V _SLOPE on one of the feedback signal VF _B or the current detection signal V _IS . When the current detection signal V _IS reaches the feedback signal V _FB , the PWM comparator 256 generates an off signal S _OFF (also referred to as an ICMP signal) that is asserted. The error amplifier 250 to the PWM comparator 256 correspond to the off signal generation unit 244 in FIG.

The logic circuit 246 generates a PWM signal S _PWM that transitions to an on level in response to the assertion of the on signal S _ON and to an off level in response to the assertion of the off signal S _OFF . For example, the logic circuit 246 may include an SR flip-flop (or latch) 260 that responds to the on signals S _ON and S _OFF .

  Note that the structure of the logic circuit 246 is not particularly limited, and a person having ordinary skill in the art can configure a circuit having an equivalent function by a combinational circuit, a sequential circuit, or a combination thereof.

When the determination circuit 420e detects a cycle in which the off signal S _OFF (ICMP) is not asserted, the determination circuit 420e asserts the enable signal S5.

FIG. 7 is a circuit diagram of a third configuration example 202 f of the pulse generator 202. The pulse generator 202f includes a voltage mode pulse width modulator 402f. Oscillator 270 generates a PWM period (switching period) PWM (pulse width modulation) that defines a _{T P} clock PWMCLK and a triangular wave, sawtooth wave, the periodic signal _{V OSC} is either ramp. The PWM comparator 274 compares the feedback signal V _FB with the periodic signal V _OSC and generates a PWM signal S _PWM indicating the comparison result. Logic circuit 276 generates a high side pulse S1 and the low-side pulse S2, based on the PWM signal _{S PWM.} The maximum duty ratio setting unit 278 generates a pulse signal S _MAXDUTY having an edge at a position corresponding to the maximum duty ratio D _MAX .

Judging circuit 420f monitors the PWM signal _{S PWM} or high side pulse S1, when the duty ratio of the monitored signal is greater than a predetermined maximum duty ratio _{D MAX,} asserts the enable signal S5. For example judging circuit 420f detects a cycle PWM signal _{S PWM} is not transited to the off-level may assert the enable signal S5.

(Second Embodiment)
FIG. 8 is a circuit diagram of a DC / DC converter 100g including the control circuit 200g according to the second embodiment. The pulse generator 202g of the control circuit 200g further includes a mode controller 600.

When the mode controller 600 detects a state in which the high-side pulse S1 does not transition to the off level (referred to as a maximum duty state) for one cycle (one switching cycle of the switching transistor M1), the mode controller 600 asserts the mode control signal S3. The assertion of the mode control signal S3 is understood to indicate that the duty ratio of the switching transistor M1 has exceeded the maximum value, in other words, that the difference between the input voltage _VIN and the output voltage _VOUT has become smaller than a predetermined value. The

When the mode control signal S3 is asserted, the pulse generator 202 shifts from the normal mode to the skip mode. Force in the skip mode, the pulse generator 202 over (i) a plurality of cycles, (also referred to as on-fixed period) and the T ₁ first period to maintain a high-side pulse S1 to the on-level, the (ii) the high side pulse S1 manner causes transition to off level, (also referred to as the charging period) by the bootstrap circuit 210 short to charge the bootstrap capacitor C2 second period and T _2, repeated. That first during the period T _1, the high-side pulse S1 is on level, the low-side pulse S2 is fixed to the off level. During the second period T _2, the high-side pulse S1 is off level, the low-side pulse S2 is set to ON-level.

During the first period _{T 1,} bootstrap capacitor C2 is because they are not charged, the voltage _{V BST} of the BST pin gradually decreases with time. Thus the length of the first period T _1, the voltage V _BST of BST terminals may be defined so as to maintain a range capable of maintaining the ON state of the switching transistor M1.

The above is the configuration of the control circuit 200g. Next, the operation will be described. FIG. 9 is an operation waveform diagram of the DC / DC converter 100g of FIG. The vertical axis and horizontal axis of the waveform diagrams and time charts in this specification are appropriately expanded and reduced for easy understanding, and each waveform shown is also simplified for easy understanding. Or it is exaggerated or emphasized. In the waveform diagram of FIG. 9, the response delay of the control circuit 200 is ignored for easy understanding and simplification of description. Before time t0, the input voltage _VIN is in a steady state sufficiently higher than the output voltage _VOUT , and the duty ratio of the high-side pulse S1 is stabilized at D = V _OUT / V _IN. It is working.

At time t0, the input voltage _VIN decreases to near the output voltage _VOUT . As a result, the duty ratio of the high-side pulse S1 increases, and the duty ratio becomes 100%. As a result, in the cycle CYC1, the high side pulse S1 does not transition to the off level (maximum duty state). When the mode controller 600 detects this cycle CYC1, the mode controller 600 asserts the mode control signal S3 at time t1, and shifts the pulse generator 202 to the skip mode.

In skip mode, in the first period T ₁ over a plurality of cycles, the on of the switching transistor M1 is maintained. Then comes the second period T _2, the high-side pulse S1 is forced to the off level, the low-side pulse S2 is at a high level, is bootstrapped capacitor C2 charging voltage V _C2 of the bootstrap capacitor C2 is increased. In skip mode, the first period T ₁ and the second period T ₂ are alternately repeated. Thereafter, when the input voltage _VIN increases again, the high side pulse S1 transitions to a low level. Then, the skip mode is canceled and the normal mode is restored.

The above is the operation of the DC / DC converter 100. The DC / DC converter 100 shifts to the skip mode when the duty ratio of the high side pulse S1 increases. In this skip mode, the switching frequency of the switching transistor M1 decreases, and the effective maximum duty ratio D _MAX is:
D _MAX = T ₁ / (T ₁ + T ₂ )
It becomes. The maximum duty ratio of the conventional pulse-by-pulse (cycle-by-cycle) is at most about 90% due to restrictions such as circuit response delay. For example the PWM period of the pulse generator 202 and _{T P,} when the length of _{T 1} to 8 times the PWM period _{T P,} and the length of _{T 2} and 40% of the PWM period _{T P,} the effective maximum duty The ratio D _MAX is approximately 8 / (0.4 + 8) × 100≈95%.

As described above, according to the DC / DC converter 100 of FIG. 8, the maximum duty ratio D _MAX of the high side pulse S1 can be increased in a reduced voltage state or the like. As a result, the output voltage _VOUT can be maintained at the target value even in a reduced voltage state that is more severe than the conventional circuit.

If the input voltage _VIN rises after operating in the skip mode in the reduced voltage state, the output voltage _VOUT may overshoot as described in the first embodiment. Therefore, the overshoot suppression circuit 410 of the control circuit 200g becomes active when the control circuit 200g shifts to the skip mode, and prepares for overshoot. That is, the determination circuit 420 switches the enable / disable state of the overshoot suppression circuit 410 based on the operation mode of the control circuit 200g.

  According to the second embodiment, the combined use of the mode controller 600 and the overshoot suppression circuit 410 can suppress overshoot after the skip mode.

  Subsequently, a specific configuration example related to the second embodiment will be described in order not to narrow the scope of the present invention, but to help understanding and clarify the essence and circuit operation of the present invention.

FIG. 10 is a circuit diagram of a first configuration example 200h of the control circuit 200 of FIG. In FIG. 10, the overshoot suppression circuit 410 and the determination circuit 420 are omitted. The pulse generator 202h includes a pulse modulator 240 and a mode controller 600h. The pulse modulator 240 generates the high side pulse S1 and the low side pulse S2 so that the voltage detection signal V _{S at the} VS terminal approaches the target value V _REF . The pulse modulator 240 corresponds to the error amplifier 400 and the pulse width modulator 402 of FIG.

The pulse modulator 240 includes an on signal generator 242, an off signal generator 244, and a logic circuit 246. ON signal generating unit 242 generates an on signal S _ON that trigger turn-on of the switching transistor M1. The off signal generation unit 244 generates an off signal S _OFF that serves as a trigger for turning off the switching transistor M1. The logic circuit 246 generates the high side pulse S1 based on the _ON signal S _ON and the OFF signal S _OFF . The error amplifier 400 of FIG. 8 is included in the ON signal generator 242 and is not shown.

Mode controller 600h monitors the off signal _{S OFF,} the OFF signal _{S OFF} to detect the cycle (period) is not asserted, and asserts the mode control signal S3, and shifts the pulse modulator 240 in skip mode. The mode controller 600h may negate the mode control signal S3 and return the pulse modulator 240 to the normal mode when the off signal S _OFF is asserted in a certain cycle during the skip mode.

Alternatively, the mode controller 600h may monitor the high side pulse S1 as indicated by a broken line instead of or in addition to the off signal S _OFF . The mode controller 600h may assert the mode control signal S3 when detecting a cycle in which the high side pulse S1 does not transition to the off level. Alternatively, when the low side pulse S2 is a complementary signal of the pulse signal S1, the mode controller 600h may generate the mode control signal S3 based on the low side pulse S2. Alternatively, the mode controller 600h may monitor an internal signal of the logic circuit 246 related to the high side pulse S1 or the low side pulse S2.

According to the control circuit 200h of FIG. 10, the duty ratio of the switching transistor M1 is large by monitoring the off signal S _OFF or the high side pulse S1 (low side pulse S2), in other words, the input voltage _VIN and the output voltage V It can be detected that _OUT is close.

Pulse generator pulse modulator 240 of 202h after the transition to the first period _{T 1,} after a predetermined number of cycles (e.g. 8), may transition to the second period _{T 2.} The length of the first period T _1, by defining the period T _P of the PWM control as a unit, the management becomes easy and also the trigger from the first period T ₁ transition of the second period T _2, counter etc. It can be easily generated using

FIG. 11 is a circuit diagram of a second configuration example 200 i of the control circuit 200. The pulse generator 202i of the control circuit 200i includes a peak current mode pulse modulator 240i. Oscillator 258 generates a PWM (pulse width modulation) clock PWMCLK defining the PWM period (switching period) _{T P.} Oscillator 258, corresponding to the ON signal generating unit 242 of FIG. 10, PWM clock PWMCLK is grasped as on signal _{S ON.}

The error amplifier 250 amplifies an error between the voltage detection signal V _S and the target value V _REF and generates a feedback signal V _FB corresponding to the error. The current sense amplifier 252 generates a current detection signal V _IS indicating the current I _M1 flowing through the switching transistor M1. The slope compensator 254 superimposes the slope signal V _SLOPE on one of the feedback signal VF _B or the current detection signal V _IS . When the current detection signal V _IS reaches the feedback signal V _FB , the PWM comparator 256 generates an off signal S _OFF (also referred to as an ICMP signal) that is asserted. The error amplifier 250 to the PWM comparator 256 correspond to the off signal generation unit 244 in FIG.

Logic circuit 246, on-level in response to the assertion of the on signal S _ON, generates a pulse signal S1 transition to the OFF level in response to the assertion of the clear signal S _OFF. For example, the logic circuit 246 may include an SR flip-flop (or latch) 260 that responds to the on signal S _ON and the off signal S _OFF . The logic unit 262 generates a high side pulse S1 and a low side pulse S2 based on the output S _PWM of the flip-flop 260. Counter 264 is provided to determine the length of the first period T ₁ of the skip mode. Specifically, the counter 264 counts the PWM clock PWMCLK, and asserts the transition signal S4 when the count value reaches a predetermined number. The logic unit 262 (or flip-flop 260) changes the high side pulse S1 and the low side pulse S2 in response to the transition signal S4.

  Note that the structure of the logic circuit 246 is not particularly limited, and a person having ordinary skill in the art can configure a circuit having an equivalent function by a combinational circuit, a sequential circuit, or a combination thereof.

Mode controller 600i monitors the off signal _{S OFF} is the output of the PWM comparator 256, during the PWM period _{T P,} when the off signal _{S OFF} is not asserted, asserts the mode control signal S3.

FIG. 12 is an operation waveform diagram of the control circuit 200i of FIG. Before time t0, the input voltage _VIN is in a steady state sufficiently higher than the output voltage _VOUT , and the duty ratio of the high-side pulse S1 is stabilized at D = V _OUT / V _IN. It is working.

At time t0, the input voltage _VIN decreases to near the output voltage _VOUT . As a result, the duty ratio of the high-side pulse S1 increases, and the duty ratio becomes 100%. As a result, in the cycle CYC1, the high side pulse S1 does not transition to the off level (maximum duty state). When the mode controller 600 detects this cycle CYC1, the mode controller 600 asserts the mode control signal S3 at time t1, and shifts the pulse generator 202 to the skip mode.

When shifting to the skip mode, the counter 264 counts the PWM clock PWMCLK (ON signal S _ON ). When the count reaches a predetermined number (here, 8), the transition signal S4 is asserted at time t2. Becomes the second period T ₂ the assertion of transition signal S4 in response, the high-side pulse S1 is forced off level, and the low-side pulse S2 is at a high level. In skip mode, in this way the first period T ₁ and the second period T ₂ and are alternately repeated. According to this configuration, the skip mode can be suitably realized in the peak current mode.

FIG. 13 is a circuit diagram of a third configuration example 200j of the control circuit 200. The pulse generator 202j of the control circuit 200j includes a voltage mode pulse modulator 240j. Oscillator 270 generates a PWM period (switching period) PWM (pulse width modulation) that defines a _{T P} clock PWMCLK and a triangular wave, sawtooth wave, the periodic signal _{V OSC} is either ramp. The error amplifier 272 amplifies an error between the voltage detection signal V _S and its target value V _REF to generate a feedback signal V _FB . The PWM comparator 274 compares the feedback signal V _FB with the periodic signal V _OSC and generates a PWM signal S _PWM indicating the comparison result. Logic circuit 276 generates a high side pulse S1 and the low-side pulse S2, based on the PWM signal _{S PWM.}

The mode controller 600j may monitor the PWM signal S _PWM output from the PWM comparator 274, and may assert the mode control signal S3 when detecting a cycle in which the PWM signal S _PWM does not transition (a cycle in which no edge appears). The logic circuit 276, in skip mode, by counting the PWM clock PWMCLK, switching may be performed from the first period _{T 1} to the second time period _{T 2.}

Next, a modification of the second embodiment will be described.
(First modification)
In the embodiment, the pulse modulator 240 in the skip mode, for each predetermined cycle of the PWM period T _P, has been inserted a second time period T _2, the present invention is not limited thereto. FIG. 14A is a circuit diagram of a pulse modulator 240k according to the first modification. Pulse modulator 240, after the transition to the first period T _1, may transition to the second period T ₂ after a predetermined time. Logic unit 280 generates a high side pulse S1 and the low-side pulse S2, based on the PWM signal _{S PWM.} Pulse modulator 240k, instead of the counter, includes an analog or a digital timer circuit (or a delay circuit) 282, after the transition to the first period T _1, the timer circuit 282 measures a predetermined time, asserts a transition signal S4 and it may transition to the second period T _2.

In this case, the length of the first period T _1, can be set freely without being constrained to the PWM period T _P. For example, when switching noise in the skip mode becomes a problem related to EMI, it is advantageous from the viewpoint of EMI countermeasures to arbitrarily determine the switching frequency.

(Second modification)
FIG. 14B is a circuit diagram of a pulse modulator 240l according to the second modification. Pulse modulator 240, after the transition to the first period T _1, may transition to the second period T ₂ after a predetermined time. Pulse modulator 240l after transition to the first period _{T 1,} the voltage _{V C2} of the bootstrap capacitor C2 is reduced to the predetermined value _{V MIN,} it may transition to the second period _{T 2.} The comparator 284 compares the voltage V _C2 of the bootstrap capacitor C2 with a predetermined value V _MIN, and asserts the transition signal S4 when V _C2 <V _MIN .

Finally, an example of a suitable application of the DC / DC converter 100 will be described. FIG. 15 is a circuit diagram of the in-vehicle power supply device 300. The in-vehicle power supply device 300 includes a battery 302 and a DC / DC converter 100. The battery 302 generates a DC voltage (battery voltage) V _BAT of 12V or 24V. However, the battery voltage V _BAT does not always provide a rated voltage value, and varies in a wide range. The DC / DC converter 100 receives the battery voltage V _BAT as the input voltage _VIN , steps down the voltage, and supplies it to the microcomputer 304 or the like as a load. In the in-vehicle power supply device 300, there is a reduced voltage state called a cold crank, and the DC / DC converter 100 is required to operate normally even during a cold crank. As described above, since the control circuit 200 can obtain a large duty ratio in the skip mode, it can be said that the control circuit 200 is superior in voltage reduction characteristics than the conventional one. From this viewpoint, the DC / DC converter 100 according to the embodiment can be suitably used for the in-vehicle power supply device 300.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(Third Modification)
Although the diode rectification type DC / DC converter has been described in the first and second embodiments, the present invention can also be applied to a synchronous rectification type DC / DC converter. That is, the rectifier diode D1 in FIG. 2 is omitted, and the element size may be large so that the coil current of the inductor L1 can be supplied so that the transistor 214 functions as a synchronous rectifier transistor.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

L1 ... inductor, C1 ... output capacitor, D1 ... rectifier diode, C2 ... bootstrap capacitor, 100 ... DC / DC converter, 102 ... input terminal, 104 ... output terminal, 110 ... output circuit, M1 ... switching transistor, 200 ... control Circuit 202, pulse generator 204, driver 210, bootstrap circuit 212 ... rectifier element 214, transistor 220, power supply circuit for bootstrap 240, pulse modulator, 242 ... ON signal generator, 244 ... OFF signal generation unit, 246 ... logic circuit, 250 ... error amplifier, 252 ... current sense amplifier, 254 ... slope compensator, 256 ... PWM comparator, 258 ... oscillator, 260 ... flip-flop, 262 ... logic unit, 264 ... counter, 270 ... Oshire , 272 ... error amplifier, 274 ... PWM comparator, 276 ... logic circuit, 280 ... logic unit, 282 ... timer circuit, 284 ... comparator, 600 ... mode controller, 300 ... in-vehicle power supply device, 302 ... battery, S1 ... high Side pulse, S2 ... low side pulse, S3 ... mode control signal.

Claims (17)

A control circuit for a step-down DC / DC converter having a switching transistor,
A pulse generator that generates a high-side pulse that instructs on / off of the switching transistor so that an output voltage of the DC / DC converter approaches a target value;
A driver for driving the switching transistor based on the high-side pulse;
With
The pulse generator is
An error amplifier that amplifies the error of the voltage detection signal according to the output voltage and its target value, and generates a feedback signal;
A pulse width modulator that generates a PWM (Pulse Width Modulation) signal having a duty ratio according to the feedback signal, and outputs the high-side pulse according to the PWM signal;
The enable state and the disable state can be switched, and when the output voltage exceeds a predetermined threshold voltage higher than the target value in the enable state, the feedback signal output from the error amplifier is lowered. And an overshoot suppression circuit that turns off the high-side pulse,
A control circuit comprising:   The control circuit according to claim 1, wherein the pulse generator further includes a determination circuit that switches a state of the overshoot suppressing circuit based on a state of the step-down DC / DC converter.   3. The determination circuit according to claim 2, wherein the determination circuit sets the overshoot suppression circuit to the enable state when a duty ratio of the PWM signal or the high-side pulse exceeds a predetermined maximum duty ratio. Control circuit.   The determination circuit sets the overshoot suppression circuit to the enable state in a reduced voltage state where a difference between a target value of an input voltage and an output voltage to the step-down DC / DC converter is smaller than a predetermined value. The control circuit according to 2.   5. The control circuit according to claim 1, wherein the overshoot suppression circuit includes a switch provided between the output terminal of the error amplifier and the ground.   6. The control circuit according to claim 1, wherein the overshoot suppression circuit includes a comparator that compares a voltage corresponding to the output voltage with a predetermined threshold voltage. The pulse width modulator includes an off signal generation unit that generates an off signal serving as a trigger for transitioning the high side pulse to an off level,
The control circuit according to claim 1, wherein the overshoot suppression circuit is in the enable state when a cycle in which the off signal is not asserted is detected.   The control circuit according to claim 7, wherein the overshoot suppression circuit enters the enable state after a predetermined number of cycles in which the off signal is not asserted.   The overshoot suppressing circuit is in the enable state when a duty ratio of the PWM signal or the high-side pulse is larger than a predetermined maximum duty ratio. Control circuit. The pulse width modulator is
An oscillator that generates an on signal that is asserted every predetermined period;
A PWM comparator that generates an off signal that is asserted when a current detection signal indicating a current flowing through the switching transistor reaches the feedback signal;
A logic circuit that generates the PWM signal whose level changes in response to the ON signal and the OFF signal;
Including
The control circuit according to claim 1, wherein the overshoot suppression circuit is in the enable state when a cycle in which the off signal is not asserted is detected. The pulse width modulator is
An oscillator that generates a periodic signal that is either a triangular wave, a sawtooth wave, or a ramp wave;
A PWM comparator that compares the feedback signal with the periodic signal;
Including
The control circuit according to claim 1, wherein the overshoot suppression circuit enters the enable state when a cycle in which an output signal of the PWM comparator does not transition is detected. The switching transistor is an N-channel transistor;
The control circuit further comprises a bootstrap circuit that charges a bootstrap capacitor;
The pulse generator includes a mode controller that detects a state in which the high-side pulse does not transition to an off level for one cycle. When the state is detected, the pulse generator shifts to a skip mode, and in the skip mode (i) A first period in which the high side pulse is maintained at an on level over a plurality of cycles; and (ii) a first period in which the high side pulse is forcibly shifted to an off level and the bootstrap circuit is charged by the bootstrap circuit. The control circuit according to claim 1, wherein the control circuit repeats two periods.   The control circuit according to claim 12, wherein the overshoot suppression circuit becomes active when the skip mode is entered.   14. The control circuit according to claim 1, wherein the control circuit is integrated on a single semiconductor substrate.   A step-down DC / DC converter comprising the control circuit according to claim 1.   An in-vehicle power supply device comprising the step-down DC / DC converter according to claim 15. A method for controlling a step-down DC / DC converter having a switching transistor, comprising:
Amplifying an error between a voltage detection signal corresponding to the output voltage of the DC / DC converter and its target value, and generating a feedback signal;
Generating a PWM (Pulse Width Modulation) signal having a duty ratio according to the feedback signal;
Driving the switching transistor based on a high-side pulse corresponding to the PWM signal;
When the output voltage exceeds a threshold voltage set higher than its target value, the feedback signal is lowered and the high side pulse is set to an off level;
A control method comprising:

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