JP7327998B2 - DC/DC converter - Google Patents

Description

The invention disclosed herein relates to a bootstrap type DC/DC converter.

2. Description of the Related Art In recent years, bootstrap type DC/DC converters have been widely used as power supply means for various applications.

As an example of conventional technology related to the above, Patent Document 1 can be cited.

Japanese Patent Application Laid-Open No. 2018-57100

However, in conventional DC/DC converters, there is room for further improvement, as the overvoltage protection operation of the converter does not take into account both ensuring safety when an abnormality is detected and immediate recovery when the abnormality is resolved.

The invention disclosed in the present specification is a DC/DC converter capable of ensuring both safety when an abnormality is detected and immediate recovery when the abnormality is resolved, in view of the above problems found by the inventors of the present application. intended to provide

The DC/DC converter disclosed herein includes a driver for driving a bootstrap type switch output stage, and a driver for generating a desired output voltage from an input voltage at the switch output stage. and an overvoltage detection unit that detects whether or not the output voltage is in an overvoltage state, and the drive unit activates the upper transistor of the switch output stage when the overvoltage state is detected. When the first overvoltage protection operation of turning off and turning on/off only the lower transistor is started, and the first overvoltage protection operation continues for a predetermined period while the overvoltage state is not resolved, the upper transistor and the lower transistor It is configured to shift to the second overvoltage protection operation in which both side transistors are turned off (first configuration).

In addition, in the DC/DC converter having the first configuration, the drive unit may be configured to turn on/off the lower transistor at a minimum duty in the first overvoltage protection operation (second configuration). .

Further, in the DC/DC converter having the first or second configuration, the driving unit causes the first overvoltage protection operation to occur during the predetermined period when only the lower transistor is turned on/off a predetermined number of times. Assuming that the overvoltage protection operation continues over a period of time, a configuration (third configuration) that transitions to the second overvoltage protection operation may be employed.

Further, in the DC/DC converter having any one of the first to third configurations, when recovering from the second overvoltage protection operation, only the lower transistor is turned off while the upper transistor is turned off before the start of normal operation. It is preferable to use an on/off configuration (fourth configuration).

A system power supply disclosed herein also has a primary power supply that generates an output voltage from an input voltage and a secondary power supply that generates a second output voltage from the output voltage, the primary power supply comprising: A configuration (fifth configuration) that is a DC/DC converter composed of any one of the first to fourth configurations is employed.

The system power supply having the fifth configuration includes a first external terminal for feeding back the output voltage to the primary power supply, a second external terminal for supplying the output voltage to the secondary power supply, are individually provided (sixth configuration).

Further, in the system power supply having the sixth configuration, the overvoltage detector may be configured to monitor the second external terminal (seventh configuration).

Further, in the system power supply having any one of the fifth to seventh configurations, the secondary power supply may have a configuration including a second DC/DC converter and a linear regulator (eighth configuration).

Further, the system power supply having the above eighth configuration includes a first chip in which the primary power supply and the second DC/DC converter are integrated, and a second chip in which the linear regulator is integrated, in a single package. A sealed configuration (ninth configuration) is preferable.

Further, the vehicle disclosed in this specification includes a system power supply having any one of the fifth to ninth configurations, and a load that operates by being supplied with power from the system power supply (tenth configuration).

With the DC/DC converter disclosed in this specification, it is possible to ensure both safety when an abnormality is detected and immediate recovery when the abnormality is resolved.

Diagram showing the overall configuration of an electronic device Diagram showing the appearance of the system power supply IC package Diagram showing the pin arrangement of the system power supply IC A diagram showing a configuration example of a bootstrap type DC/DC converter The figure which shows the 1st example of overvoltage protection operation The figure which shows the 2nd example of overvoltage protection operation The figure which shows the 3rd example of overvoltage protection operation External view showing one configuration example of vehicle X

<Electronic equipment>
FIG. 1 is a diagram showing the overall configuration of an electronic device. The electronic device 1 of this configuration example has a system power supply IC 10 and various discrete components externally attached thereto (in this figure, inductors L1 and L2 and capacitors C1 to C4).

The system power supply IC 10 is a semiconductor integrated circuit device that receives an input voltage VI and generates a plurality of systems of output voltages (three systems of output voltages VO1 to VO3 in this figure). The system power supply IC 10 has a plurality of external terminals (in this figure, external terminals T11 to T15, external terminals T21 to T24, external terminals T31 to T34).

Outside the system power supply IC 10, the external terminal T11 is connected to the first end of the capacitor C2. The external terminal T12 is connected to the application end of the input voltage VI. A bypass capacitor may be connected between the external terminal T12 and the ground terminal. The external terminal T13 is connected to the first end of the inductor L1 and the second end of the capacitor C2. The external terminal T14 is connected to the application terminal of the output voltage VO1 together with the second terminal of the inductor L1 and the first terminal of the capacitor C1. The external terminal T15 and the second end of the capacitor C1 are both connected to the ground terminal.

The external terminal T21 is connected to the application end of the output voltage VO1. A bypass capacitor may be connected between the external terminal T21 and the ground terminal. The external terminal T22 is connected to the first end of the inductor L2. The external terminal T23 is connected to the application terminal of the output voltage VO2 together with the second terminal of the inductor L2 and the first terminal of the capacitor C3. Both the external terminal T24 and the second end of the capacitor C3 are connected to the ground terminal.

The external terminal T31 is connected to the application end of the output voltage VO1. A bypass capacitor may be connected between the external terminal T31 and the ground terminal. A filter FLT (see FIG. 3 described later) may be connected between the external terminal T31 and the terminal for applying the output voltage VO1. The external terminals T32 and T33 are connected together with the first end of the capacitor C4 to the application end of the output voltage VO3. Both the external terminal T34 and the second end of the capacitor C4 are connected to the ground terminal.

<System power supply IC (internal configuration)>
Next, the internal configuration of the system power supply IC 10 will be described with reference to FIG. The system power supply IC 10 is formed by integrating DC/DC converters 100 and 200 and a linear regulator 300 .

More specifically, the system power supply IC 10 integrates a semiconductor chip 10A (=first chip) in which DC/DC converters 100 and 200, a logic control clock (not shown), etc., and a linear regulator 300 are integrated. A semiconductor chip 10B (=second chip) is sealed in a single package.

By adopting such a multi-chip configuration, it is possible to separate the DC/DC converters 100 and 200, which can be noise sources, from the linear regulator 300, which requires low noise, in a single package. Become.

The DC/DC converter 100 is connected to the external terminals T11 to T15 inside the system power supply IC 10, and steps down the input voltage VI (4.5 to 36 V, for example) to produce a desired output voltage VO1 (4.0 V, for example). ) is the primary power source. It should be noted that the output voltage VO1 is used only for power supply to the secondary power supply (the DC/DC converter 200 and the linear regulator 300 in this figure) built in the system power supply IC10.

The DC/DC converter 200 is connected to external terminals T21 to T24 inside the system power supply IC 10, and is one of the secondary power supplies that steps down the output voltage VO1 to generate a desired output voltage VO2 (for example, 1.25 V). is one. Note that the output voltage VO2 is supplied to an MCU [micro controller unit] or the like.

The linear regulator 300 is connected to external terminals T31 to T34 inside the system power supply IC 10, and is one of secondary power supplies that steps down the output voltage VO1 to generate a desired output voltage VO3 (eg, 3.3 V). and, for example, an LDO [low drop-out] regulator can be preferably used. The output voltage VO3 is supplied to an MMIC [monolithic microwave integrated circuit] for millimeter wave radar or the like.

The above-mentioned millimeter-wave radar transmits a transmission wave whose frequency is swept, and then receives the transmission wave reflected by the obstacle as a reception wave. detect. If the power supply of the MMIC fluctuates when such an obstacle is detected (especially during transmission of transmission waves), there is a possibility that the frequency difference between the transmission waves and the reception waves cannot be correctly obtained. Therefore, the output voltage VO3 supplied to the MMIC (and the output voltage VO1 supplied to the linear regulator 300) is required to have low noise.

Note that the system power supply IC 10 may be provided with functional blocks other than those described above. For example, a step-up DC/DC converter may be provided as a secondary power supply, or the number of channels of a linear regulator may be increased. In that case, it is desirable to integrate the step-up DC/DC converter, which can become a noise source, together with the previously mentioned DC/DC converters 100 and 200 into the semiconductor chip 10A. On the other hand, the added linear regulator is preferably integrated on the semiconductor chip 10B together with the linear regulator 300 that requires low noise.

The system power supply IC 10 also includes a logic control circuit, a logic control clock, an internal reference voltage generation circuit, a communication interface (I/O), a microcomputer monitoring circuit (WDT [watch dog timer]), a self-diagnostic circuit (BIST [built-in in self test]), various abnormal protection circuits (UVLO [under voltage locked out], OCP [over current protection], OVD [over voltage detection], UVD [under voltage detection], SCP [short circuit protection], TSD [ thermal shutdown]) are also integrated.

<System power supply IC (package)>
FIG. 2 is a diagram showing the package appearance (top surface and bottom surface) of the system power supply IC 10. As shown in FIG. As shown in the figure, the package of the system power supply IC 10 may be, for example, a VQFN [very thin quad flat non-leaded] package.

More specifically, the system power supply IC 10 has a resin sealing body 11 that is rectangular in plan view, and on the bottom surface of which does not protrude from the resin sealing body 11, a total of 56 lines, 14 on each side. External terminals 12 are exposed. With such a leadless VQFN package, it is possible to reduce the mounting area compared to packages with leads (such as QFP [quad flat package]).

The resin sealing body 11 is tapered from the side surface to the bottom surface so that the bottom surface is slightly smaller than the top surface. Also, the external terminals 12 are exposed from the bottom surface to the side surface of the resin sealing body 11 . With such a configuration, mounting work on a printed wiring board (not shown) can be carried out easily and reliably.

Also, on the bottom surface of the resin sealing body 11, the rear surface of the island 13 on which a semiconductor chip (not shown) is mounted (=the rear surface of the chip mounting surface) is exposed as a heat radiation pad. With such a configuration, it is possible to improve the heat dissipation of the system power supply IC 10 .

At least one of the four corners of the island 13 is preferably provided with a notch portion 13a (=a thin portion recessed from the bottom surface side of the resin sealing body 11 toward the top surface side). Since the material of the resin sealing body 11 enters into the notch 13a, the island 13 is sandwiched by the resin sealing body 11 from both upper and lower sides in the formation region of the notch 13a. With such a configuration, it is possible to improve the adhesion with the resin sealing body 11 and prevent the island 13 from coming off.

<System power supply IC (pin arrangement)>
FIG. 3 is a diagram showing the pin arrangement of the system power supply IC 10 (when a 56-pin VQFN is used). It should be noted that, in this drawing, an arrangement example of each of the external terminals (T11 to T15, T21 to T24, and T31 to T34) shown in FIG. 1 is depicted.

14 external terminals (pins 1 to 14) are arranged in order from left to right in the figure on the first side (lower side in the figure) of the system power supply IC 10 . Pins 1 and 2 are power ground terminals (corresponding to the external terminal T24) for the DC/DC converter 200, and both are connected to the ground terminal. Pins 3 and 4 are power supply input terminals (corresponding to the external terminal T21) for the DC/DC converter 200, and both are connected to the application terminal of the output voltage VO1. A bypass capacitor (not shown) may be connected between the 3rd and 4th pins and the ground terminal. A 6th pin is a feedback terminal (corresponding to the external terminal T23) for the DC/DC converter 200, and is connected to the application terminal of the output voltage VO2 (=the second terminal of the inductor L2). An output smoothing capacitor C3 is connected between the terminal to which the output voltage VO2 is applied and the ground terminal.

On the second side (right side in the figure) of the system power supply IC 10, 14 external terminals (pins 15 to 28) are arranged in order from bottom to top in the figure. A 21st pin is a ground terminal (corresponding to the external terminal T34) for the linear regulator 300 and is connected to the ground terminal. A 25th pin is a feedback terminal (corresponding to the external terminal T33) for the linear regulator 300, and is connected to the application terminal of the output voltage VO3. Pins 26 and 27 are output terminals (corresponding to the external terminal T32) for the linear regulator 300, and both are connected to the application terminal of the output voltage VO3. A capacitor C4 for output smoothing is connected between the terminal to which the output voltage VO3 is applied and the ground terminal.

14 external terminals (pins 29 to 42) are arranged in order from right to left in the figure on the third side (upper side in the figure) of the system power supply IC 10 . Pins 29 and 30 are power input terminals (corresponding to the external terminal T31) for the linear regulator 300, and are connected to the application terminal of the filtered output voltage VO1FIL (=the output terminal of the filter FLT). A filter FLT (eg, an LC filter) produces a filtered output voltage VO1FIL by removing the noise component of the output voltage VO1. A bypass capacitor (not shown) may be connected between the 29th and 30th pins and the ground terminal. A 31st pin is a ground terminal (corresponding to the external terminal T34) for the linear regulator 300 and is connected to the ground terminal. Thus, the ground terminals for the linear regulator 300 are provided on two different sides (for example, the second side and the third side) of the system power supply IC 10 . Pins 37 to 39 are power supply input terminals (corresponding to the external terminal T12) for the DC/DC converter 100, and are all connected to the application terminal of the input voltage VI. A bypass capacitor (not shown) may be connected between the 37th to 39th pins and the ground terminal. Pins 41 and 42 are power ground terminals (corresponding to the external terminal T15) for the DC/DC converter 100 and are connected to the ground terminal. Between the 39th pin and the 41st pin, an unused terminal (40th pin) is provided to prevent a short circuit between the power supply input terminal and the power ground terminal.

On the fourth side (left side of the figure) of the system power supply IC 10, 14 external terminals (pins 43 to 56) are arranged in order from top to bottom of the figure. A 43rd pin is a boot terminal (corresponding to the external terminal T11) for the DC/DC converter 100, and is connected to the first end of the capacitor C2. Pins 45 to 47 are switching terminals (corresponding to the external terminal T13) for the DC/DC converter 100, and are connected to the first end of the inductor L1 and the second end of the capacitor C2. A 50th pin is a feedback terminal (corresponding to the external terminal T14) for the DC/DC converter 100, and is connected to the application terminal of the output voltage VO1 (=the second terminal of the inductor L1). A capacitor C1 for output smoothing is connected between the terminal to which the output voltage VO1 is applied and the ground terminal. Pins 55 and 56 are switching terminals (corresponding to external terminal T22) for DC/DC converter 200, and both are connected to the first end of inductor L2.

<DC/DC converter (primary power supply)>
FIG. 4 is a diagram showing a configuration example of a bootstrap-type DC/DC converter 100. As shown in FIG. The DC/DC converter 100 of this configuration example includes a drive section 110, a control section 120, an overvoltage detection section 130, N-channel MOS field effect transistors N1 and N2, and a P-channel MOS field effect transistor P1. have.

Among the above components, transistors N1, N2 and P1 form a bootstrap type switch output stage together with discrete components (inductor L1, capacitors C1 and C2) externally attached to system power supply IC 10. FIG. These connection relationships will be described in detail below.

The drain of the transistor N1 is connected to the external terminal T12 (=applying terminal of the input voltage VI). The source of the transistor N1 is connected to the external terminal T13 (=application terminal of the switch voltage Vsw). The gate of the transistor N1 is connected to the application terminal of the upper gate signal HG. The transistor N1 turns on when the upper gate signal HG is at high level (≈VB), and turns off when the upper gate signal HG is at low level (≈Vsw). The transistor N1 functions as an upper transistor (=output transistor) of the switch output stage.

A drain of the transistor N2 is connected to the external terminal T13. The source of the transistor N2 is connected to the external terminal T15 (=the terminal to which the ground voltage GND is applied). The gate of the transistor N2 is connected to the application terminal of the lower gate signal LG. The transistor N2 turns on when the lower gate signal LG is at high level (≈Vreg), and turns off when the lower gate signal LG is at low level (≈GND). Note that the transistor N2 functions as a lower transistor (=synchronous rectification transistor) of the switch output stage.

The drain of the transistor P1 is connected to the application end of the internal power supply voltage Vreg. The source of the transistor P1 is connected to the external terminal T11 (=application terminal of the boot voltage VB). Transistor P1 connected in this manner forms a bootstrap circuit together with capacitor C2 externally attached to system power supply IC10.

In the above bootstrap circuit, the voltage VC2 across the capacitor C2 (=when the capacitor C2 is fully charged, VC2≈Vreg-Vds(P1), where Vds(P1) is the drain voltage of the transistor P1, is always higher than the switch voltage Vsw. A boot voltage VB (≈Vsw+VC2) higher by the source-to-source voltage) is generated.

That is, the boot voltage VB becomes VB≈VI+VC2 during the high level period of the switch voltage Vsw (Vsw≈VI, N1=ON, N2=OFF), and becomes VB≈VI+VC2 during the low level period of the switch voltage Vsw (Vsw≈GND, N1=OFF, N2=ON), VB≈VC2.

The boot voltage VB generated in this way is supplied to the driving section 110 (in particular, the upper driver 111 described later), and is used as the high level of the upper gate voltage HG (=the gate voltage for turning on the transistor N1). Used. Therefore, during the ON period of the transistor N1, the high level (≈VB) of the upper gate voltage HG is pulled up to a voltage value (≈VI+VC2) higher than the high level (≈VI) of the switch voltage Vsw.・It becomes possible to reliably turn on the transistor N1 by increasing the source-to-source voltage.

As a component of the bootstrap circuit, instead of the transistor P1, a diode having an anode connected to the application terminal of the internal power supply voltage Vreg and a cathode connected to the external terminal T11 may be used. In this case, the voltage VC2 across the capacitor C2 becomes VC2≈Vreg−Vf (where Vf is the forward voltage drop of the diode) when fully charged.

The drive section 110 is a functional block that drives the bootstrap type switch output stage (particularly the transistors N1 and N2) and includes an upper driver 111, a lower driver 112 and a logic section 113. FIG.

The upper driver 111 operates by receiving the supply of the boot voltage VB and the switch voltage Vsw, and generates the upper gate signal HG based on the upper control signal HS input from the logic section 113 . For example, the upper driver 111 sets the upper gate signal HG to a high level (≈VB) when the upper control signal HS is at a high level, and sets the upper gate signal HG to a low level when the upper control signal HS is at a low level. Let the level be (≈Vsw).

The lower driver 112 operates by being supplied with the internal power supply voltage Vreg and the ground voltage GND, and generates the lower gate signal LG based on the lower control signal LS input from the logic section 113 . For example, the lower driver 112 sets the lower gate signal LG to high level (≈Vreg) when the lower control signal LS is at high level, and sets the lower gate signal LG to high level (≈Vreg) when the lower control signal LS is at low level. The gate signal LG is set to low level (≈GND).

The logic unit 113 generates the upper control signal HS and the lower control signal LS based on the ON signal Son pulse-driven at a predetermined switching frequency Fsw (eg, 475 kHz) and the OFF signal Soff input from the control unit 120. do.

For example, during normal operation of the switch output stage (=a state in which various abnormal protection operations are not applied), when a pulse edge is generated in the ON signal Son, the upper The control signal HS is set to high level and the lower control signal LS is set to low level. On the other hand, when a pulse edge is generated in the off signal Soff, the upper control signal HS is set to low level and the lower control signal LS is set to high level in order to turn off the transistor N1 and turn on the transistor N2.

Thus, by complementarily turning on/off the transistors N1 and N2 of the switch output stage, a switch voltage Vsw having a rectangular waveform (high level: VIN, low level: GND) is generated at the external terminal T13. . By rectifying and smoothing this switch voltage Vsw with an LC filter (=inductor L1 and capacitor C1), the on-period Ton of the transistor N1 occupied in the on-duty Don (=switching period Tsw (=1/Fsw) of the switch output stage An output voltage VO1 (=VI*Don) can be generated according to the ratio, Don=Ton/Tsw.

The logic unit 113 also has a function of providing a simultaneous off period (so-called dead time) for both transistors N1 and N2 when the transistors N1 and N2 are complementary turned on/off so that an excessive through current does not flow through the transistors N1 and N2. I have.

The logic unit 113 also includes a counter 114 that counts the high level period of the overvoltage detection signal OVP (=the period during which the overvoltage state of the output voltage VO1 is detected, hereinafter referred to as the OVP period), and the length of the OVP period. It also has a function to switch the overvoltage protection operation method according to the situation. This novel overvoltage protection operation will be described in detail later.

Control unit 120 outputs off signal Soff so that desired output voltage VO1 is generated from input voltage VI at the switch output stage. and controls the driving section 120, and includes an error amplifier 121, an off signal generating section 122, resistors 123 to 125, and a capacitor 126.

The resistors 123 and 124 are connected in series between the external terminal T14 (=applied terminal of the output voltage VO1) and the ground terminal, and the feedback voltage Vfb (=divided voltage of the output voltage VO1) is applied from the mutual connection node. to output If the output voltage VO1 is within the input dynamic range of the subsequent stage, the resistors 123 and 124 may be omitted and the output voltage VO1 passed through to the subsequent stage.

The error amplifier 121 has a voltage between the lower one of the reference voltage Vref and the soft start voltage Vss respectively input to the non-inverting input terminal (+) of two systems and the feedback voltage Vfb input to the inverting input terminal (-). An error current Ierr corresponding to the difference is output.

The direction in which the error current Ierr flows is the first direction (=the direction from the error amplifier 121 to the capacitor 126, that is, the direction in which the capacitor 126 is charged) when Vref (Vss)>Vfb. When Vref (Vss)<Vfb, the second direction (=the direction from the capacitor 126 to the error amplifier 121, that is, the direction to discharge the capacitor 126). The magnitude (absolute value) of the error current Ierr increases as the difference between the reference voltage Vref (or the soft start voltage Vss) and the feedback voltage Vfb increases, and conversely decreases as the difference between the two voltages decreases.

Further, the soft-start voltage Vss slowly rises from zero to exceed the reference voltage Vref over a predetermined soft-start period Tss (eg, 3 ms) when the DC/DC converter 100 is first started or restarted. . Therefore, before the soft-start period Tss expires, an error current Ierr corresponding to the difference between the soft-start voltage Vss and the feedback voltage Vfb is generated. An error current Ierr corresponding to the difference between is generated. Such a soft start operation can prevent rush current to the capacitor C1.

A resistor 125 and a capacitor 126 are connected in series between the output end of the error amplifier 121 and the ground end, and function as a current/voltage conversion circuit that converts the error current Ierr into the error voltage Verr. It also functions as a phase compensation circuit to prevent oscillation. The error voltage Verr increases when Vref(Vss)>Vfb, and conversely decreases when Vref(Vss)<Vfb.

The off-signal generator 122 generates the off-signal Soff based on the error voltage Verr. More specifically, the OFF signal generator 122 delays the pulse edge generation timing of the OFF signal Soff (corresponding to the OFF timing of the transistor N1) as the error voltage Verr is higher. To advance the pulse edge generation timing of the off signal Soff. Such an off signal Soff can be easily generated, for example, by using a comparator that compares the error voltage Verr and the triangular or sawtooth slope voltage Vslp.

Further, for example, the current flowing through the switch output stage (the upper switch current flowing through the transistor N1, the lower switch current flowing through the transistor N2, the inductor current flowing through the inductor L1, or the output current flowing through the load) is detected to generate an off signal. A current mode control system can also be realized by feeding back to the unit 122 .

Of course, the output feedback control method of the control section 120 is not limited to the voltage mode control method or the current mode control method, and a nonlinear hysteresis control method (ripple control method) or the like may be employed.

The overvoltage detector 130 is a functional block that detects whether the output voltage VO1 is in an overvoltage state. The overvoltage detection unit 130 includes, for example, an output voltage VO1 input from the external terminal T21 to the non-inverting input terminal (+) and a predetermined threshold voltage Vth (eg, 4.0 V) input to the inverting input terminal (-). 7V) can be used to generate an overvoltage detection signal OVP. In this case, the overvoltage detection signal OVP becomes low level (=normal logic level) when VO1<Vth, and becomes high level (=abnormal logic level) when VO1>Vth.

Here, the system power supply IC 10 has an external terminal T14 for feeding back the output voltage VO1 to the primary power supply (=DC/DC converter 100), and supplying the output voltage VO1 to the secondary power supply (=DC/DC converter 200). An external terminal T21 is separately provided for this purpose. Therefore, it is possible to detect the overvoltage of the output voltage VO1 regardless of which of the external terminals T14 and T21 is monitored.

However, in view of the safety of the secondary power supply (DC/DC converter 200 and linear regulator 300), it is desirable that the overvoltage detection unit 130 monitors the latter external terminal T21 to detect overvoltage of the output voltage VO1.

For example, if the external terminal T14 is disconnected from the terminal to which the output voltage VO1 is applied and is in a ground fault state (=short-circuited to the ground terminal or a similar low potential terminal), the DC/DC converter 100 will increase the output voltage VO1 endlessly. Consider the situation where In this case, if the overvoltage detection unit 130 were to monitor the grounded external terminal T14, the overvoltage state of the output voltage VO1 would not be detected, and the excessive output voltage VO1 would continue to be generated. As a result, the secondary power supply (or the load connected to it) may malfunction or be destroyed.

On the other hand, if the overvoltage detection unit 130 monitors the external terminal T21, even if the external terminal T14 is grounded, overvoltage detection of the output voltage VO1 can be performed. can be increased.

If the external terminal T21 deviates from the terminal to which the output voltage VO1 is applied and becomes grounded, the overvoltage detector 130 will not function properly. Voltage VO1 does not fall into an overvoltage condition.

Further, when a plurality of secondary power supplies that operate by receiving power from the primary power supply are provided, for example, the power supply input terminal of the secondary power supply closest to the primary power supply may be monitored by the overvoltage detector.

<Overvoltage protection operation>
Next, the new overvoltage protection operation in DC/DC converter 100 will be described in detail. As described above, the driving section 110 (especially the logic section 113) of the DC/DC converter 100 has a function of switching the overvoltage protection operation method according to the length of the OVP period.

More specifically, when the overvoltage state of the output voltage VO1 is detected, the drive unit 110 starts the first overvoltage protection operation to turn off the transistor N1 and turn on/off only the transistor N2, and the output voltage When the first overvoltage protection operation continues for a predetermined period of time Tx while the overvoltage state of VO1 is not cleared, the overvoltage protection operation is shifted to the second overvoltage protection operation in which both the transistors N1 and N2 are turned off. In the following, this new overvoltage protection operation will be described in detail for each case with reference to FIGS. 5 to 7. FIG.

FIG. 5 is a timing chart showing a first example of the overvoltage protection operation, depicting the output voltage VO1, the overvoltage detection signal OVP, the upper gate signal HG, and the lower gate signal LG in order from the top. The behavior shown in this figure can occur, for example, when a transient load change occurs.

Since the output voltage VO1 is lower than the threshold voltage Vth (=overvoltage detection value) before time t11, the overvoltage detection signal OVP is at low level (=normal logic level). At this time, the driving section 110 complementarily turns on/off the transistors N1 and N2 as a normal operation of the switch output stage. That is, when an overvoltage state of the output voltage VO1 is not detected, both the upper gate signal HG and the lower gate signal LG are switching-driven (pulse-driven) as usual.

At time t11, when the output voltage VO1 exceeds the threshold voltage Vth, the overvoltage detection signal OVP rises to high level (=abnormal logic level). At this time, the driving unit 110 starts the first overvoltage protection operation in which the transistor N1 is turned off and only the transistor N2 is periodically turned on/off at a minimum duty. That is, in the first overvoltage protection operation, while the upper gate signal HG is fixed at low level, only the lower gate signal LG is cyclically switching driven with the minimum duty (minimum high level width).

During the ON period of the transistor N2, a current path from the terminal to which the internal power supply voltage Vreg is applied to the ground terminal through the transistor P1, the capacitor C2, and the transistor N2 is conducted, and the capacitor C2 is charged by the current flowing therethrough. be done.

Therefore, in the above-described first overvoltage protection operation, the transistor N1 is turned off to stop the operation of generating the output voltage VO1, while the transistor N2 is turned on/off to periodically charge the capacitor C2, thereby increasing the voltage VC2 across the capacitor C2. (Furthermore, the boot voltage VB) can be maintained at an appropriate voltage value (=voltage value at which the transistor N1 can be reliably turned on).

Further, the drive unit 110 (especially the counter 114) starts timing the predetermined period Tx when the overvoltage detection signal OVP rises to high level. As a method for timing the predetermined period Tx, for example, it is sufficient to count the number m of ON times of the transistor N2 that is turned ON/OFF in the switching period Tsw. In this case, the predetermined period Tx is represented by Tx=m×Tsw. So, for example, if Tsw≈2 μs (Fsw=475 kHz), m=256 is equivalent to Tx≈0.5 ms.

After that, at time t12, when the output voltage VO1 falls below the threshold voltage Vth and the overvoltage detection signal OVP falls to the low level before the predetermined period Tx expires, the drive unit 110 switches from the first overvoltage protection operation to the normal operation. return. At this time, the voltage VC2 across the capacitor C2 is maintained at an appropriate voltage value by periodic charging of the capacitor C2 in the first overvoltage protection operation. Therefore, when the overvoltage state of the output voltage VO1 is resolved, the drive unit 110 can quickly resume the complementary on/off of the transistors N1 and N2, so that the normal operation can be resumed without delay. becomes.

FIG. 6 is a timing chart showing a second example of the overvoltage protection operation, depicting the output voltage VO1, the overvoltage detection signal OVP, the upper gate signal HG, and the lower gate signal LG in order from the top. The behavior shown in this figure can occur, for example, when the external terminal T14 (=feedback terminal for the DC/DC converter 100) is disconnected from the terminal to which the output voltage VO1 is applied and becomes grounded.

For example, due to a ground fault at the external terminal T14, the DC/DC converter 100 falls into an abnormal state in which the output voltage VO1 is endlessly increased. At time t21, when the output voltage VO1 exceeds the threshold voltage Vth, the overvoltage detection signal OVP rises to a high level, and the above-described first overvoltage protection operation is started. That is, the transistor N1 is turned off and only the transistor N2 is periodically turned on/off with the minimum duty. As a result, the output voltage VO1 changes from increasing to decreasing.

After that, at time t22, when the output voltage VO1 falls below the threshold voltage Vth before the predetermined period Tx expires, the overvoltage detection signal OVP falls to the low level, so the first overvoltage protection operation is returned to the normal operation.

However, if the ground fault state of the external terminal T14 is not resolved, the output voltage VO1 rises again after returning to normal operation. Therefore, as shown after time t22 in the figure, transition to the first overvoltage protection operation (time t22, t24, t26) and return to normal operation (time t23, t25, t27) are alternately repeated. state. Of course, even in such a state, each first overvoltage protection operation maintains the voltage VC2 across the capacitor C2 at an appropriate voltage value. An immediate return to normal operation is possible.

FIG. 7 is a timing chart showing a third example of the overvoltage protection operation, depicting the output voltage VO1, the overvoltage detection signal OVP, the upper gate signal HG, and the lower gate signal LG in order from the top. The behavior shown in this figure can occur, for example, when the external terminal T21 is shorted to power supply (for example, short-circuited to the application end of the input voltage VI or a corresponding high potential end).

When the output voltage VO1 exceeds the threshold voltage Vth at time t31 due to the short-circuit of the external terminal T21, the overvoltage detection signal OVP rises to high level, and the above-described first overvoltage protection operation is started. That is, the transistor N1 is turned off and only the transistor N2 is periodically turned on/off with the minimum duty. However, if the external terminal T21 is short-circuited to the power supply, even if the first overvoltage protection operation is performed, the output voltage VO1 will not fall below the threshold voltage Vth, and the overvoltage detection signal OVP will be maintained at a high level. be done.

After that, at time t32, when the first overvoltage protection operation continues for the predetermined period Tx while the overvoltage state of the output voltage VO1 is not resolved, the driving unit 110 performs the second overvoltage protection operation to turn off both the transistors N1 and N2. transition to As a method for determining the elapse of the predetermined period of time Tx, for example, it may be determined whether or not the number m of ON times of the transistor N2 has reached a predetermined value (for example, m=256).

In the second overvoltage protection operation described above, not only the transistor N1 but also the transistor N2 are turned off. Therefore, unlike the first overvoltage protection operation in which the transistor N2 is periodically turned on and off in order to charge the capacitor C2, no overcurrent flows through the transistor N2, so that the risk of destruction of the transistor N2 can be reduced. It becomes possible.

Note that the length of the predetermined period Tx (=the duration of the first overvoltage protection operation) is determined so that the transistor N2 will not be destroyed by the overcurrent that intermittently flows through the transistor N2 during the first overvoltage protection operation. , it is desirable to have a sufficient safety margin.

After that, the short-to-power state of the external terminal T21 is eliminated, and at time t33, when the output voltage VO1 falls below the threshold voltage Vth and the overvoltage detection signal OVP falls to low level, the second overvoltage protection operation returns to normal operation. is done.

However, in the above-described second overvoltage protection operation, since both the transistors N1 and N2 are turned off, the voltage VC2 across the capacitor C2 is discharged via the upper driver 111 and the like, and is not maintained at an appropriate voltage value. There is a risk.

Therefore, when recovering from the second overvoltage protection operation, as indicated by times t33 to t34, the transistor N1 is turned off and only the transistor N2 is turned on a predetermined number of times n (for example, n=32) before the start of the normal operation. It is desirable to turn on only periodically. According to such an operation, the capacitor C2 can be precharged, so that the transistor N1 can be reliably turned on/off prior to normal operation.

It should be noted that DC/DC converter 100 shifts to normal operation through soft start operation after precharging of capacitor C2 is completed (see time t24 and later). Such an operation is the same as when the DC/DC converter 100 is started for the first time. That is, recovery from the second overvoltage protection operation can also be understood as restarting the DC/DC converter 100 .

As described above, when the OVP period is short, the first overvoltage protection operation is performed to turn off the transistor N1 and turn on/off only the transistor N2. If the period becomes longer, the operation shifts to the second overvoltage protection operation in which both the transistors N1 and N2 are turned off, and priority is given to preventing the destruction of the transistor N2.

With this new overvoltage protection operation, it is possible to achieve both safety assurance when an abnormality is detected and immediate recovery when the abnormality is resolved.

<Application to vehicles>
FIG. 8 is an external view showing one configuration example of the vehicle X. As shown in FIG. The vehicle X of this configuration example is equipped with various electronic devices (in-vehicle devices) X11 to X18 that operate by being supplied with power from a battery. Note that the mounting positions of the electronic devices X11 to X18 in this figure may differ from the actual ones for convenience of illustration.

The electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).

The electronic device X12 is a lamp control unit that controls lighting and extinguishing of HID [high intensity discharged lamps] and DRL [daytime running lamps].

The electronic device X13 is a transmission control unit that performs control related to the transmission.

The electronic device X14 is a braking unit that performs control related to the motion of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

The electronic device X15 is a security control unit that drives and controls door locks, security alarms, and the like.

The electronic device X16 includes wipers, electric door mirrors, power windows, dampers (shock absorbers), electric sunroofs, electric seats, millimeter wave radars, etc., and is incorporated into vehicle X at the factory shipment stage as standard equipment or manufacturer options. It is an electronic device that is

The electronic device X17 is an electronic device arbitrarily mounted on the vehicle X as a user option, such as an in-vehicle A/V [audio/visual] device, a car navigation system, and an ETC [electronic toll collection system].

The electronic device X18 is an electronic device having a high withstand voltage motor, such as an in-vehicle blower, an oil pump, a water pump, and a battery cooling fan.

Note that the system power supply 10 described above can be incorporated in any of the electronic devices X11 to X18. That is, each of the electronic devices X11 to X18 can be understood as a specific example of the electronic device 1 described above.

<Other Modifications>
In addition to the above embodiments, the various technical features disclosed in this specification can be modified in various ways without departing from the gist of the technical creation. That is, the above-described embodiments should be considered as examples and not restrictive in all respects, and the technical scope of the present invention is not limited to the above-described embodiments. It is to be understood that a range and equivalents are meant to include all changes that fall within the range.

INDUSTRIAL APPLICABILITY The invention disclosed in this specification can be used, for example, as an in-vehicle system power supply for millimeter wave radar.

1 electronic device 10 system power supply IC
10A, 10B semiconductor chip 11 resin sealing body 12 external terminal 13 island (radiating pad)
13a Notch 100 DC/DC converter (primary power supply)
110 drive unit 111 upper driver 112 lower driver 113 logic unit 114 counter 120 control unit 121 error amplifier 122 off signal generator 123 to 125 resistor 126 capacitor 130 overvoltage detector 200 DC/DC converter (secondary power supply)
300 Linear regulator (secondary power supply)
C1~C4 Capacitor FLT Filter L1, L2 Inductor N1 N-channel MOS field effect transistor (upper transistor)
N2 N-channel MOS field effect transistor (lower transistor)
P1 P-channel MOS field effect transistor T11-T15, T21-T24, T31-T34 External terminal X Vehicle X11-X18 Electronic equipment

Claims (10)

a driver for driving a bootstrapped switch output stage;
a control unit for controlling the driving unit so that a desired output voltage is generated from the input voltage in the switch output stage;
an overvoltage detection unit that detects whether the output voltage is in an overvoltage state;
has
The switch output stage includes an upper transistor connected between the input voltage application terminal and the switch voltage application terminal, and a lower transistor connected between the switch voltage application terminal and the ground voltage application terminal. a transistor for rectifying and smoothing the switch voltage to produce the output voltage;
When the overvoltage state is detected, the driving section turns off the upper transistor of the switch output stage and starts a first overvoltage protection operation to turn on/off only the lower transistor, thereby canceling the overvoltage state. a DC/DC converter, wherein when the first overvoltage protection operation continues for a predetermined period without overvoltage protection, the DC/DC converter shifts to a second overvoltage protection operation in which both the upper transistor and the lower transistor are turned off. 2. The DC/DC converter according to claim 1, wherein said driving section turns on/off said lower transistor with a minimum duty in said first overvoltage protection operation. 3. The driving unit, when only the lower transistor is turned on/off a predetermined number of times, shifts to the second overvoltage protection operation assuming that the first overvoltage protection operation continues over the predetermined period . A DC/DC converter according to claim 1 or claim 2. 4. The driving unit according to any one of claims 1 to 3, wherein, when recovering from the second overvoltage protection operation, the drive unit turns on/off only the lower transistor while keeping the upper transistor off before starting normal operation. A DC/DC converter according to claim 1. a primary power supply that generates the output voltage from the input voltage;
at least one secondary power source supplied with the output voltage;
has
A system power supply, wherein the primary power supply is the DC/DC converter according to any one of claims 1 to 4. a first external terminal for feeding back the output voltage to the primary power supply;
a second external terminal for supplying the output voltage to the secondary power supply;
6. The system power supply of claim 5 , having individually a . 7. The system power supply according to claim 6 , wherein said overvoltage detector monitors said second external terminal. The system power supply according to any one of claims 5 to 7 , wherein said secondary power supply includes a second DC/DC converter and a linear regulator. a first chip integrating the primary power supply and the second DC/DC converter;
a second chip integrated with the linear regulator;
in a single package. a system power supply according to any one of claims 5 to 9;
a load that operates by being supplied with power from the system power supply;
a vehicle .

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