JP2019009548A - Operational amplifier and dc/dc converter using the same - Google Patents

Abstract

To provide an operational amplifier having an input/output characteristic of transconductance with a slope of 2 or more.SOLUTION: An operational amplifier 3A adds output of a first operational amplifier OP1 having first transconductance gm1 and output of a second operational amplifier OP2 having second transconductance gm2 by an adder. The transconductance when a differential voltage between a feedback voltage VFB applied to a first input terminal IN1 and a reference voltage VREF applied to a second input terminal IN2 is relatively small is set smaller than transconductance when the differential voltage is relatively large.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an operational amplifier and a DC / DC converter using the operational amplifier.

  Recently, operational amplifiers that can be used for various purposes have been developed. There are various types of operational amplifiers, including general-purpose operational amplifiers, low-noise operational amplifiers, high-speed operational amplifiers, and power operational amplifiers. Such an operational amplifier may be incorporated into various semiconductor devices. For example, it is used as an error amplifier in a DC / DC converter.

  The operational amplifier described in Patent Document 1 is described with respect to a slew rate increasing circuit. The input terminals 1 and 2 are connected to two input terminals of the operational amplifier, and the output terminal 3 is connected in parallel to the first stage bias current source of the operational amplifier. Two differential pairs T1 and T2 constituted by transistors Q1, Q2, diode D1, and transistors Q3, Q4, and diode D2 have a differential input signal voltage of the operational amplifier larger than a certain threshold value (about 0.5 V). Only when the current is supplied to the first stage of the operational amplifier, the phase compensation capacitor is rapidly charged to increase the slew rate.

  The operational amplifier described in Patent Document 2 will be described with respect to a bias current variable circuit. A non-inverting amplifier circuit including an operational amplifier OP and a feedback circuit composed of resistance elements Rf and Ri. A bias current IB to a differential pair composed of PMOS transistors P1 and P2 of the operational amplifier OP is converted into resistance elements Rf, By adjusting according to the gain set by Ri, it is possible to amplify to a predetermined amplitude level regardless of the amplitude range of the input signal. In this case, the frequency band can be kept constant and amplified through the same low-pass filter characteristics without switching the capacitance value of the feedback capacitor.

  The operational amplifier described in FIG. 7 of Patent Document 3 will be described with respect to a bias current variable circuit. When the input voltage difference is within a predetermined range, it operates with one current source, and when it is outside the predetermined range, it operates with two current sources. As a result, the characteristic shown in FIG. 4C of Patent Document 3 is realized.

  FIG. 6 shows a circuit diagram of a DC / DC converter examined in advance by the present inventors.

  The DC / DC converter 600 includes IN, SW, PGND, AGND, FB, and COMP as external terminals, and steps down the input voltage VIN supplied to the input terminal IN, which is one of the external terminals, to a desired output voltage VOUT. Is a well-known step-down switching regulator that outputs the signal to the output terminal OUT.

  The DC / DC converter 600 includes a switching transistor 1, a synchronous rectifying element 2, an error amplifier 3, an oscillation circuit device 4, a summing unit 5, a PWM comparator 6, and a drive control circuit 7.

  Further, the input voltage VIN, the inductor L41, the capacitors C41 to C42, the resistors R41 to R43, and the ground potential GND are connected via external terminals provided outside the DC / DC converter 600. The DC / DC converter 600 performs a step-down operation by the action of passive elements such as an inductor, a capacitor, and a resistor connected to an external terminal attached thereto.

  The input voltage VIN is a DC voltage selected from 10 V to 15 V, for example, and is applied to the input terminal IN. The output voltage VOUT is set to about 5V, for example. The source of the switching transistor 1 is connected to the input terminal IN. The drain of the switching transistor 1 is connected to the switching terminal SW and the drain of the synchronous rectifier element 2. The source of the synchronous rectifying element 2 is connected to the ground potential GND through the ground terminal PGND. The ground terminal AGND is connected to the ground potential GND similarly to the ground terminal PGND, but is prepared separately from the ground terminal PGND. This is because the circuit operation of the error amplifier 3, the oscillation circuit device 4, the PWM comparator 6, the drive control circuit 7, etc., through which a relatively small current flows and is connected to the ground terminal AGND, This is in order not to be affected by potential fluctuations.

  The switching transistor 1 is a p-channel MOS transistor and the synchronous rectifier element 2 is an n-channel MOS transistor, but is not limited to these combinations. For example, the switching transistor 1 may be an nMOS transistor, and the synchronous rectifying element 2 may be replaced with a diode.

  One end of the inductor L41 is connected to the switching terminal SW. The other end of the inductor L41 is connected to the output terminal OUT and one end of the capacitor C41, and the other end of the capacitor C41 is connected to the ground potential GND.

  Resistors R41 and R42 connected in series between the output terminal OUT and the ground potential GND operate as a feedback voltage generation circuit. The resistors R41 and R42 output the feedback voltage VFB to the common connection node. The feedback voltage VFB is input to the inverting input terminal (−) of the error amplifier 3 through the first input terminal IN1 (feedback terminal FB).

  The reference voltage VREF is input to the non-inverting input terminal (+) of the error amplifier 3, and the feedback voltage VFB is input to the inverting input terminal (−). The error amplifier 3 outputs an error signal Verr corresponding to the voltage accepted by the input terminal to the inverting input terminal (−) of the PWM comparator 6. The output terminal of the error amplifier 3 is connected to a resistor R43 and a capacitor C42 via a phase compensation terminal COMP.

  The clock signal CLK generated by the oscillation circuit device 4 is input to the drive control circuit 7. Further, the oscillation circuit 4 outputs a slope signal SLOPE to the summing means 5 at the subsequent stage. The slope signal SLOPE is, for example, a triangular waveform or a sawtooth waveform whose period changes following the clock signal CLK.

  The summing means 5 sums the voltage components corresponding to the slope signal SLOPE and the switching current ISW and outputs the sum to the non-inverting input terminal (+) of the PWM comparator 6. Since the summing means 5 is prepared to configure the DC / DC converter 600 as a current feedback type, it is not necessary when the voltage feedback type is used.

  The PWM comparator 6 outputs a reset signal RESET to the drive control circuit 7. The drive control circuit 7 is connected to the gates of the switching transistor 1 and the synchronous rectifier element 2.

  The operation of the step-down DC / DC converter 600 having such a configuration will be briefly described. In the DC / DC converter 600 in the step-down mode, when the switching transistor 1 is on and the synchronous rectifier 2 is off, the switching current ISW flows from the input terminal IN to the capacitor C41 via the inductor L41, and magnetic energy is stored. It is done. Conversely, when the switching transistor 1 is off and the synchronous rectifier 2 is on, current flows from the synchronous rectifier 2 to the capacitor C41 via the inductor L41, so that the magnetic energy stored in the inductor L41 is reduced. Released. By such an operation, the input voltage VIN is stepped down and the output voltage VOUT is output from the output terminal OUT. The resistors R41 and R42 divide the output voltage VOUT output from the output terminal OUT to generate a feedback voltage VFB and send it to the first input terminal IN1 (feedback terminal FB).

  The error amplifier 3 compares the reference voltage VREF and the feedback voltage VFB, and outputs an error signal Verr corresponding to the comparison result. The feedback voltage VFB is, for example, 0.6V to 5V.

  A resistor R43 and a capacitor C42 connected in series between the phase compensation terminal COMP and the ground potential GND set the gain and frequency characteristics of the error amplifier 3 as a phase compensation circuit. The frequency characteristics of the DC / DC converter 600 are corrected by the phase compensation. Note that the phase compensation circuit is not a series circuit of the resistor R43 and the capacitor C42, but another capacitor may be connected to the phase compensation circuit in parallel, for example, so as to have a so-called secondary characteristic.

  The oscillation circuit device 4 outputs a clock signal CLK, and the frequency is selected from 200 kHz to 5 MHz, for example. Usually, the switching transistor 1 and the synchronous rectifying element 2 are on / off controlled at one frequency within these ranges. For example, when the frequency is set to 1 MHz, it is 0.9 μs when the on-duty ratio is 90%, and 0.1 μs when the on-duty ratio is 10%.

  The drive control circuit 7 receives the clock signal CLK output from the oscillation circuit device 4 and the reset signal RESET output from the PWM comparator 6, and outputs a gate signal GP and a gate signal GN. The switching transistor 1 and the synchronous rectifier element 2 are turned on / off in a complementary manner by the gate signal GP and the gate signal GN. An RS flip-flop (not shown), for example, is prepared inside the drive control circuit 7. The clock signal CLK generated by the oscillation circuit device 4 is provided at the set terminal of the RS flip-flop, and the PWM comparator 6 is provided at the reset terminal. The reset signal RESET output from is applied respectively.

  Although not shown, the drive control circuit 7 is provided with a dead time in order to prevent an excessive through current flowing from the switching transistor 1 toward the synchronous rectifier element 2. During the dead time period, both the switching transistor 1 and the synchronous rectifier element 2 are placed in the off state to block the current path of the through current.

  FIG. 7 shows the output current characteristics of the error amplifier 3 (operational amplifier). In FIG. 7, the horizontal axis represents the feedback voltage VFB, and the vertical axis represents the error amplifier output current Ierr. Regardless of the feedback voltage VFB, the slope gm of the error amplifier output current Ierr is constant.

  FIG. 8 is a waveform diagram showing the clock signal CLK, the slope signal SLOPE, the reset signal RESET, and the switching voltage Vsw in order to explain a problem caused by the undulation of the error signal Verr.

  It has been found that the on-time y7, y8, y9 of the switching voltage, which should be constant, varies as a result of occurrence of temporal fluctuation in the reset signal RESET, which is the output of the PWM comparator 6. This variation affects the fluctuation of the output voltage VOUT.

JP-A-6-112737 JP 2015-119304 A JP 2011-72102 A

  When the operational amplifier (error amplifier 3) examined in advance by the present inventor is adopted for the DC / DC converter, the transconductance of the operational amplifier is set high to improve the response, and the transconductance is constant regardless of the voltage. For this reason, the reference voltage VREF may repeatedly go back and forth, and the waveform of the error signal Verr may undulate.

  In the method of increasing the slew rate of the operational amplifier described in Patent Document 1, it is very difficult to adjust the threshold value, and a problem that fine adjustment cannot be performed may occur.

  In the operational amplifier bias current variable circuit described in Patent Document 2, a determination circuit is required to increase or decrease the bias current, which may increase the circuit area.

  In the operational amplifier bias current variable circuit described in Patent Document 3, a determination circuit is required to increase or decrease the bias current, which may increase the circuit area.

  The present invention has been made to overcome the above-described problems, and its object is to suppress the swell of the error signal Verr in the vicinity of the reference voltage VREF and control the on / off time of the switching voltage Vsw in the control of the error amplifier. It is to suppress the variation of.

  In this document, the first main electrode corresponds to the source in the MOS transistor and the emitter in the bipolar transistor. The second main electrode corresponds to the drain in the MOS transistor and to the collector in the bipolar transistor. The control electrode corresponds to the gate in the MOS transistor and the base in the bipolar transistor. Also, in this document, the same physical size means that the MOS transistor has the same gate channel length and channel width, and the bipolar transistor has the same emitter area.

  One aspect of the operational amplifier according to the present invention includes a first transistor having a first main electrode, a second main electrode, and a control electrode, a second transistor, a third transistor, and a fourth transistor, and the first transistor and the second transistor. The first main electrodes of the third transistor and the fourth transistor are connected in common to form a first differential pair transistor and connected to a first current source, and the first main electrode of the third transistor and the fourth transistor are connected in common and second. A differential pair transistor is formed and connected to a second current source; the control electrodes of the first transistor and the fourth transistor are connected in common and connected to a first input terminal to which a first input signal is applied; The control electrodes of the second transistor and the third transistor are connected in common and connected to a second input terminal to which a second input signal is applied. The second main electrode and the second main electrode of the third transistor are connected in common and connected to the first circuit point, and the second main electrode of the second transistor and the second main electrode of the fourth transistor are connected. The electrodes are connected in common and connected to a second circuit point, and a first difference signal and a second difference signal between the first input signal and the second input signal are connected to the first circuit point and the second circuit point, respectively. Take out.

  According to another aspect of the operational amplifier of the present invention, the first transistor and the second transistor have the same physical size, and the third transistor and the fourth transistor have the same physical size. There is also a second size different from the first size.

  According to another aspect of the operational amplifier of the present invention, the first transistor, the second transistor, the third transistor, and the fourth transistor are composed of MOS transistors, and the gate channel length and gate channel width of the MOS transistor are The first size and the second size are configured with at least one different.

  According to another aspect of the operational amplifier of the present invention, the magnitudes of currents generated by the first current source and the second current source are different.

  According to another aspect of the operational amplifier of the present invention, the first differential signal and the second differential signal are converted into currents at the first circuit point and the second circuit point, respectively, and are extracted.

  According to another aspect of the operational amplifier of the present invention, the first differential signal and the second differential signal are added by an adder and taken out from the output terminal as a combined differential signal.

  According to another aspect of the operational amplifier of the present invention, the transconductance when the difference between the first input signal and the second input signal is relatively small is compared with the difference between the first input signal and the second input signal. It is smaller than the transconductance when it is large.

  According to another aspect of the present invention, there is provided a DC / DC converter according to a switching means that is turned on / off to generate an output voltage from an input voltage and a difference between a feedback voltage corresponding to the output voltage and a reference voltage. An error amplifier that generates an error signal, an oscillation circuit device that generates a slope signal of a clock signal and a triangular wave or a sawtooth wave, and a PWM signal whose pulse width is modulated by comparing the slope signal and the error signal A PWM comparator for outputting; a drive control circuit for receiving the clock signal and an output signal from the PWM comparator and controlling the switching means; and the error amplifier using any one of the operational amplifiers .

  According to the present invention, it is possible to suppress the undulation of the error signal Verr near the reference voltage of the error amplifier.

An example of the configuration of the error amplifier 3A of the present invention is shown. The conceptual diagram of 1st operational amplifier OP1 and 2nd operational amplifier OP2 which comprise error amplifier 3A is shown. The output current characteristics of the first operational amplifier OP1 and the second operational amplifier OP2 constituting the error amplifier 3A are shown. The output current characteristic of the error amplifier 3A of the present invention is shown. The switching voltage Vsw of this invention is shown. A block diagram of a DC / DC converter 600 examined in advance by the inventors is shown. FIG. 6 shows the output current characteristics of the error amplifier 3 used. The switching voltage Vsw examined in advance by the inventors is shown.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows an example of the configuration of an error amplifier 3A according to the present invention. A DC / DC converter according to the present invention is obtained by replacing the error amplifier 3 in FIG. 6 with an error amplifier 3A, and other circuits are the same as those in FIG.

  In FIG. 1, one end of the current source ISET is connected to the ground potential GND, the other end is connected to the drain of the MOS transistor M1, and its source is connected to the power supply potential VCC. The gates of the MOS transistors M1 to M3 are commonly connected to the drain of the MOS transistor M1. The sources of the MOS transistors M2 and M3 are connected to the power supply potential VCC similarly to the source of the MOS transistor M1. That is, a well-known current mirror circuit is formed by the MOS transistors M1 to M3 and the current source ISET.

  The drain of the MOS transistor M2 is connected to the sources (first main electrodes) of the MOS transistors M4 and M5, and the gate (control electrode) of the MOS transistor M4 is connected to the first input terminal IN1 (feedback terminal FB). The gate (control electrode) of the MOS transistor M5 is connected to the second input terminal IN2 (reference terminal REF).

The physical sizes of the MOS transistors M4 and M5 are the same, and the first differential pair transistor DFA1 is formed by both MOS transistors.
The drain (second main electrode) of the MOS transistor M4 is connected to one end of the resistor R1 and the drain of the MOS transistor M6 to form the first circuit point CP1, and the drain (second main electrode) of the MOS transistor M5 is the resistor R2. Is connected to the drain of the MOS transistor M7 to form a second circuit point CP2, and the other end of the resistor R1 is commonly connected to the other end of the resistor R2, the gate of the MOS transistor M6, and the gate of the MOS transistor M7. Yes.

  At the first circuit point CP1, the first difference signal between the first input terminal IN1 (feedback terminal FB) and the second input terminal IN2 (reference terminal REF) is converted into a current and taken out, and the second circuit point CP2 A second differential signal between the first input terminal IN1 (feedback terminal FB) and the second input terminal IN2 (reference terminal REF) is converted into a current and extracted.

  The sources of the MOS transistors M6 and M7 are connected to the ground potential GND.

  The drain of the MOS transistor M3 is connected to the sources (first main electrodes) of the MOS transistors M8 and M9, and the gate (control electrode) of the MOS transistor M9 is connected to the first input terminal IN1 (feedback terminal FB). The gate (control electrode) of the MOS transistor M8 is connected to the second input terminal IN2 (reference terminal REF).

  The physical sizes of the MOS transistors M8 and M9 are the same, and the second differential pair transistor DFA2 is formed by both MOS transistors.

  The drain (second main electrode) of the MOS transistor M8 is connected to one end of the resistor R3 and the drain of the MOS transistor M10 to form the first circuit point CP1, and the drain (second main electrode) of the MOS transistor M9 is the resistor R4. Is connected to the drain of the MOS transistor M11 to form a second circuit point CP2, and the other end of the resistor R3 is commonly connected to the other end of the resistor R4, the gate of the MOS transistor M10, and the gate of the MOS transistor M11. Yes.

  The sources of the MOS transistors M10 and M11 are connected to the ground potential GND.

  The drain of the MOS transistor M6 is connected to the drain of the MOS transistor M10 and the gate of the MOS transistor M12, and the drain of the MOS transistor M7 is connected to the drain of the MOS transistor M11 and the gate of the MOS transistor M13.

  The source of the MOS transistor M13 is connected to one end of the resistor R5, and the other end of the resistor R5 is connected to the ground potential GND. The drain of the MOS transistor M13 is connected to the drain and gate of the MOS transistor M14, the source of the MOS transistor M14 is connected to one end of the resistor R6, and the other end of the resistor R6 is connected to the power supply potential VCC. .

  The source of the MOS transistor M12 is connected to one end of the resistor R7, and the other end of the resistor R7 is connected to the ground potential GND. The drain of the MOS transistor M12 is connected to the drain of the MOS transistor M15 and the current output terminal OUT1. The source of the MOS transistor M15 is connected to one end of the resistor R8, and the other end of the resistor R8 is connected to the power supply potential VCC. The gate of the MOS transistor M15 is connected to the gate of the MOS transistor M14.

  In short, the error amplifier 3A has a configuration in which two operational amplifiers having different transconductances are combined. Here, the two operational amplifiers are a first operational amplifier OP1 composed of MOS transistors M2, M4, M5, M6 and M7 and a second operational amplifier OP2 composed of MOS transistors M3, M8, M9, M10 and M11.

  The MOS transistor M2 is, for example, five times as large as the MOS transistor M1, which serves as a reference for the current mirror, whereas the MOS transistor M3 is, for example, twice as large. Due to this difference, there is a difference in the current supplied to the first operational amplifier OP1 and the second operational amplifier OP2. MOS transistor M2 and MOS transistor M3 correspond to a first current source and a second current source, respectively, in this document. The first current source generates a current I2, and the second current source generates a current I3.

  The physical sizes of the MOS transistors M4 and M5 and the MOS transistors M8 and M9 are different. For example, the gate channel width W of the MOS transistors M4 and M5 is 10 μm and the gate channel length L is 3 μm, whereas the gate channel width W of the MOS transistors M8 and M9 is 5 μm and the gate channel length L is 1 μm, for example. The difference in transconductance gm is caused by the difference in physical size.

  In the present invention, both the gate channel width W and the gate channel length L are made different, but at least one of them may be made different depending on the transconductance to be set.

  The MOS transistors M12 to M15 and R5 to R8 constitute an adder Adder. The adder Adder adds the first differential signal output from the first circuit point CP1 and the second differential signal output from the second circuit point CP2, and outputs the result to the current output terminal OUT1 as a combined differential signal.

  FIG. 2 shows a connection conceptual diagram of the first operational amplifier OP1 and the second operational amplifier OP2. The first transconductance gm1 of the first operational amplifier OP1 and the second transconductance gm2 of the second operational amplifier OP2 are added by the adder Adder and output.

  The output currents of the first operational amplifier OP1 and the second operational amplifier OP2 are not the same. The difference is constituted by the difference in current mirror current depending on the ratio of the MOS transistors M2 and M3, and the difference in gate channel length L and gate channel width W between the MOS transistors M4 and M5 and the MOS transistors M8 and M9.

  FIG. 3 shows the transconductance characteristics of the error amplifier 3A shown in FIG. The vertical axis indicates the output currents Igm1 and Igm2 of the first operational amplifier OP1 and the second operational amplifier OP2. Here, the output current Igm1 is output from the drain of the MOS transistor M5. The output current Igm2 is output from the drain of the MOS transistor M9. Note that output currents are also output from the drain of the MOS transistor M4 of the first operational amplifier OP1 and the drain of the MOS transistor M8 of the second operational amplifier OP2, respectively, but these output currents are for convenience of explanation and avoid the complexity of the drawings. I am omitted.

  The horizontal axis shows the case where the feedback voltage VFB applied to the first input terminal IN1 is changed and the reference voltage VREF applied to the second input terminal IN2 is fixed.

  The output current Igm1 of the first operational amplifier OP1 is set larger than the output current Igm2 of the second operational amplifier OP2. The slopes of the current characteristics of the output current Igm1 and the output current Igm2 are set to be opposite to each other.

  The output current Igm1 of the first operational amplifier OP1 is mainly set by the MOS transistors M2, M4, and M5. The MOS transistor M2 determines the maximum current, and the MOS transistors M4 and M5 determine the maximum current, that is, the first transconductance gm1. The first transconductance gm1 is expressed by the following equation.

  gm1 = ΔIgm1 / Δ (VFB−VREF)

  Similarly, the output current Igm2 of the second operational amplifier OP2 is mainly set by the MOS transistors M3, M8, and M9. The MOS transistor M3 determines the maximum current, and the MOS transistors M8 and M9 determine the maximum current, that is, the second transconductance gm2. The second transconductance gm2 is expressed by the following equation.

  gm2 = ΔIgm2 / Δ (VFB−VREF)

  By adding the transconductance characteristics of the first operational amplifier OP1 and the second operational amplifier OP2, the combined characteristic of FIG. 4 is realized.

FIG. 4 shows the output current Ierr of the error amplifier 3A. The horizontal axis represents the feedback voltage VFB, and the vertical axis represents the output current Ierr.
The transconductance increases when the feedback voltage VFB is away from the reference voltage VREF, and the transconductance decreases near the reference voltage VREF. When the output voltage of the error amplifier 3A is close to the set voltage, the transconductance is lowered to ensure stability, and when the output voltage is away from the set voltage, the transconductance is increased to increase the feedback speed of the error amplifier 3A.
That is, the voltage is controlled rapidly when the voltage is far from the reference voltage VREF and gently when the voltage is close. As a result, the waveform undulation near the reference voltage VREF is reduced.

  The transconductances gm3 and gm4 of the entire error amplifier 3A in FIG. 4 can be freely designed by combining the transconductances of the first operational amplifier OP1 and the second operational amplifier OP2. The magnitude of the transconductance of the first differential pair transistor DFA1 and the second differential pair transistor DFA2 in FIG. 1 may be set in accordance with the required input / output characteristics of the error amplifier 3A. The transconductance of the first differential pair transistor DFA1 appropriately sets the product (W / L) I2 of the ratio W / L of the gate channel length L to the gate channel width W of the MOS transistors M4 and M5 and the current I2, and The transconductance of the two differential pair transistors DFA2 is set by appropriately setting the product (W / L) I3 of the ratio W / L of the gate channel length L to the gate channel width W of the MOS transistors M8 and M9 and the current I3, respectively. Just decide.

  When the variation of the output voltage VOUT generated at the output terminal OUT is ± several%, it is preferable to set the reference voltage VREF ± several% even in a section where the transconductance is small. By doing so, the section in which the output voltage VOUT is stable coincides with the section in which the waveform undulation near the reference voltage VREF is reduced.

The maximum value and the minimum value of the output current are determined by the magnitudes of the resistors R1, R2, R3, and R4 in FIG. The resistors R1 and R2 are inserted so that the MOS transistor M4 and the MOS transistor M5 of the first operational amplifier OP1 are not short-circuited. The output current can be reduced by reducing the resistance value. Conversely, the output current can be maximized by increasing the resistance value.
The same applies to the second operational amplifier OP2, and the resistors R3 and R4 are inserted so that the MOS transistor M8 and the MOS transistor M9 are not short-circuited.

  Further, the maximum value and the minimum value of the output current are also determined by the magnitudes of the resistors R5, R6, R7, and R8 in FIG. Since this output current leads to generation of an overshoot current at the time of return after the output terminal OUT is grounded, for example, it needs to be adjusted appropriately. For example, the output current is set to ± 20 μA.

  FIG. 5 shows waveforms of the error signal Verr, the clock signal CLK, the slope signal SLOPE, the reset signal RESET, and the switching voltage Vsw in the present invention.

  The undulation of the error signal Verr is smaller than that in FIG. 8, and it can be seen that the reset signal RESET is equally spaced. As a result, the temporal fluctuation of the switching voltage Vsw is also eliminated, and the on time y4 = y5 = y6 is established. As a result, the fluctuation of the output voltage is suppressed.

The present invention does not stick to the operational amplifier composed of the MOS transistors shown in this example. The same can be done with an operational amplifier composed of bipolar transistors. Similarly, in the case of an operational amplifier of a bipolar transistor, it can be realized by changing the current value flowing through the differential input stage and the emitter area of the differential input stage.
Further, in the present invention, the configuration in which two operational amplifiers are added has been described, but any number of operational amplifiers to be added may be used as long as they are two or more. What is necessary is just to combine according to the required transconductance.

  The present invention prevents undulation in the vicinity of a reference potential due to an operational amplifier. Therefore, the present invention has very high industrial applicability.

DESCRIPTION OF SYMBOLS 1 Switching transistor 2 Synchronous rectifier 3 Error amplifier 3A Error amplifier 4 Oscillation circuit device 5 Summing means 6 PWM comparator 7 Drive control circuit 600 DC / DC converter Adder Adder AGND Ground terminal C41, C42 Capacitor CLK Clock signal CP1 1st circuit point CP2 Second circuit point DFA1 First differential pair transistor DFA2 Second differential pair transistor FB Feedback terminal gm1 First transconductance gm2 Second transconductance gm3 Transconductance gm4 Transconductance GN Gate signal GND Ground potential GP Gate signal I2 Current I3 Current Ierr Output current Igm1 Output current Igm2 Output current IN Input terminal IN1 First input terminal IN2 Second input terminal ISE Current source ISW Switching current L Gate channel length L41 Inductor M1 to M15 MOS transistor OP1 First operational amplifier OP2 Second operational amplifier OUT Output terminal OUT1 Current output terminal PGND Ground terminals R1 to R8, R41 to R43 Resistor REF Reference terminal RESET Reset signal SLOPE Slope Signal VCC Power supply potential Verr Error signal VFB Feedback voltage VOUT Output voltage VREF Reference voltage Vsw Switching voltage W Gate channel width

Claims (8)

  A first transistor having a first main electrode, a second main electrode, and a control electrode, a second transistor, a third transistor, and a fourth transistor, wherein the first main electrode of the first transistor and the second transistor is shared Connected to form a first differential pair transistor and connected to a first current source, and the first main electrodes of the third transistor and the fourth transistor are connected in common to form a second differential pair transistor. Connected to a current source, the control electrodes of the first transistor and the fourth transistor are connected in common and connected to a first input terminal to which a first input signal is applied, and the second transistor and the third transistor The control electrodes are connected in common and connected to a second input terminal to which a second input signal is applied, and the second main electrode and the third transistor of the first transistor are connected. The second main electrode of the transistor is connected in common and connected to the first circuit point, and the second main electrode of the second transistor and the second main electrode of the fourth transistor are connected in common and connected to the second circuit point. An operational amplifier connected to a circuit point and extracting a first difference signal and a second difference signal between the first input signal and the second input signal to the first circuit point and the second circuit point, respectively.   The physical size of the first transistor and the second transistor is the same first size, and the physical size of the third transistor and the fourth transistor is the same but is different from the first size. The operational amplifier according to claim 1 which is a size.   The first transistor, the second transistor, the third transistor, and the fourth transistor are composed of MOS transistors, and at least one of a gate channel length and a gate channel width of the MOS transistor is different from the first size. The operational amplifier according to claim 1, wherein the second size is configured.   The operational amplifier according to claim 1, wherein magnitudes of currents generated by the first current source and the second current source are different.   2. The operational amplifier according to claim 1, wherein the first differential signal and the second differential signal are converted into currents and extracted from the first circuit point and the second circuit point, respectively.   The operational amplifier according to claim 5, wherein the first difference signal and the second difference signal are added by an adder and taken out from an output terminal as a combined difference signal.   The transconductance when the difference between the first input signal and the second input signal is relatively small is smaller than the transconductance when the difference between the first input signal and the second input signal is relatively large. The operational amplifier according to any one of claims 1 to 6. Switching means that is turned on / off to generate an output voltage from the input voltage;
An error amplifier that generates an error signal according to a difference between a feedback voltage according to the output voltage and a reference voltage;
An oscillation circuit device for generating a clock signal and a triangular or sawtooth slope signal;
A PWM comparator that compares the slope signal with the error signal and outputs a PWM signal with a modulated pulse width;
A DC / DC converter comprising a drive control circuit that receives the clock signal and an output signal from the PWM comparator and controls the switching means,
The DC / DC converter, wherein the error amplifier includes the operational amplifier according to any one of claims 1 to 7.

Images