JP5926559B2 - 同一の能動領域内に形成されるトランジスタにおいて能動領域内に局所的に埋め込み歪誘起半導体材質を設けることによる駆動電流調節 - Google Patents
同一の能動領域内に形成されるトランジスタにおいて能動領域内に局所的に埋め込み歪誘起半導体材質を設けることによる駆動電流調節 Download PDFInfo
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Description
Claims (15)
- 半導体デバイスの基板の上方に形成される能動領域の内部及び上方に第1の伝導性タイプを有する第1のトランジスタを形成することと、
前記能動領域の内部及び上方に前記第1の伝導性タイプを有する第2のトランジスタを形成することと、
前記第1のトランジスタの第1のチャネル領域及び前記第2のトランジスタの第2のチャネル領域に異なる歪レベルを誘起するように、前記第1の埋め込み半導体合金を前記第1のトランジスタ内に設けることと、前記第2のトランジスタ内に第2の埋め込み半導体合金を設けることとによって前記第1及び第2のトランジスタの駆動電流能力の比を調節することとを備え、
前記第1及び第2のトランジスタは実質的に同一のチャネル幅を有しており、
前記第1の埋め込み半導体合金は前記第1のチャネル領域における電荷キャリア移動度を減少させ、前記第2の埋め込み半導体合金は前記第2のトランジスタの前記第2のチャネル領域内の電荷キャリア移動度を増大させる方法。 - 前記第1の埋め込み半導体合金はシリコン、ゲルマニウム及び錫の少なくとも1つを備えている、請求項1の方法。
- 前記第2の埋め込み半導体合金は炭素を備えている、請求項1の方法。
- 前記第1のトランジスタの第1のチャネル領域及び前記第2のトランジスタの第2のチャネル領域に異なる歪レベルを誘起するように、前記第1の埋め込み半導体合金を前記第1のトランジスタ内に設けることと、前記第2のトランジスタ内に第2の埋め込み半導体合金を設けることとによって前記第1及び第2のトランジスタの駆動電流能力の比を調節することは、前記第1及び第2のトランジスタの少なくとも一方のドレイン及びソース区域内にキャビティを形成することと、前記キャビティを前記第1及び第2の埋め込み半導体合金の少なくとも一方で充填することとを備えている、請求項1の方法。
- 前記第1及び第2のトランジスタの駆動電流能力の比を調節することは、前記キャビティのサイズ、前記第1及び第2のチャネル領域に対する前記キャビティの距離、並びに第1の埋め込み半導体合金及び第2の埋め込み半導体合金の前記少なくとも一方の組成の少なくとも1つを調節することを備えている、請求項4の方法。
- 半導体デバイスの基板の上方に形成される能動領域の内部及び上方に第1の伝導性タイプを有する第1のトランジスタを形成することと、
前記能動領域の内部及び上方に前記第1の伝導性タイプを有する第2のトランジスタを形成することと、
前記第1のトランジスタの第1のチャネル領域及び前記第2のトランジスタの第2のチャネル領域に異なる歪レベルを誘起するように前記第1及び第2のトランジスタの少なくとも一方の内部に第1の埋め込み半導体合金及び第2の埋め込み半導体合金の少なくとも一方を設け、前記第1及び第2のトランジスタの一方における前記第1及び第2の埋め込み半導体合金の前記一方を緩和させることによって前記第1及び第2のトランジスタの駆動電流能力の比を調節することとを備え、
前記第1及び第2のトランジスタは実質的に同一のチャネル幅を有している方法。 - 前記第1及び第2のトランジスタの少なくとも一方の上方に歪誘起誘電体層を形成することを更に備えた、請求項6の方法。
- 圧縮歪誘起誘電体層が前記第1のトランジスタの上方に選択的に形成され且つ前記第1の埋め込み半導体合金は圧縮歪を誘起するように前記第1のトランジスタ内に形成される、請求項7の方法。
- 引張り歪誘起誘電体層が前記第2のトランジスタの上方に選択的に形成される、請求項8の方法。
- 半導体デバイスの半導体層内に実質的に一定の幅を有する能動領域を形成することと、
第1のチャネル領域を画定するように前記能動領域の上方に第1のゲート電極構造を形成することと、
前記第1のチャネル領域に隣接する第2のチャネル領域であって、その伝導性タイプが前記第1のチャネル領域の伝導性タイプと同じである第2のチャネル領域を画定するように前記能動領域の上方に前記第1のゲート電極構造に隣接する第2のゲート電極構造を形成することと、
前記第1及び第2のチャネル領域内に異なる歪レベルを誘起するように前記能動領域内に埋め込み半導体合金を形成することとを備え、
前記埋め込み半導体合金を形成することは、前記第1のチャネル領域内に圧縮歪を誘起するように前記第1のゲート電極構造に隣接して圧縮歪誘起半導体合金を選択的に形成することと、前記第2のチャネル領域内に引張り歪を誘起するように前記第2のゲート電極構造に隣接して引張り歪誘起半導体合金を選択的に形成することとを備えており、
前記第1及び第2のチャネル領域は実質的に同一のチャネル幅を有している方法。 - 前記能動領域の上方に1つ以上の更なる隣接するゲート電極構造を形成することを更に備えている、請求項10の方法。
- 基板の上方に形成される能動半導体領域と、
前記能動半導体領域の内部及び上方に形成される第1のトランジスタと、
前記能動半導体領域の内部及び上方に形成される第2のトランジスタと、
前記能動半導体領域内に局所的に埋め込まれる歪誘起半導体合金とを備えた半導体デバイスであって、
前記第1のトランジスタは第1の歪レベルを有する第1のチャネル領域と第1のゲート電極構造とを備えており、
前記第2のトランジスタは前記第1の歪レベルとは異なる第2の歪レベルを有する第2のチャネル領域と第2のゲート電極構造とを備えており、
前記第1のトランジスタの伝導性タイプと前記第2のトランジスタの伝導性タイプとが同じであり、
前記歪誘起半導体合金は、第1のチャネル領域内に圧縮歪を誘起するように前記第1のゲート電極構造に隣接して形成された圧縮歪誘起半導体合金と前記第2のチャネル領域内に引張り歪を誘起するように前記第2のゲート電極構造に隣接して形成された引張り歪誘起半導体合金とを備えており、
前記第1及び第2のトランジスタは実質的に同一のチャネル幅を有している半導体デバイス。 - 前記半導体デバイスがメモリデバイスであり、前記第1及び第2のトランジスタは前記メモリデバイスのメモリセルのトランジスタであり、前記第1のトランジスタは前記第2のトランジスタの第2の駆動電流能力より小さい第1の駆動電流能力を有している、請求項12の半導体デバイス。
- 前記能動領域は1つ以上の更なるトランジスタを備えている、請求項13の半導体デバイス。
- 前記1つ以上の更なるトランジスタの1つ目は前記第1のトランジスタと同一の構造を有しており、前記1つ以上の更なるトランジスタの2つ目は前記第2のトランジスタと同一の構造を有している、請求項14の半導体デバイス。
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US12/507,544 | 2009-07-22 | ||
US12/507,544 US8034669B2 (en) | 2008-08-29 | 2009-07-22 | Drive current adjustment for transistors formed in the same active region by locally providing embedded strain-inducing semiconductor material in the active region |
PCT/EP2009/006259 WO2010022971A1 (en) | 2008-08-29 | 2009-08-28 | Drive current adjustment for transistors formed in the same active region by locally providing embedded strain inducing semiconductor material in the active region |
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US8466018B2 (en) | 2011-07-26 | 2013-06-18 | Globalfoundries Inc. | Methods of forming a PMOS device with in situ doped epitaxial source/drain regions |
CN102280379B (zh) * | 2011-09-05 | 2016-06-01 | 上海集成电路研发中心有限公司 | 一种应变硅nmos器件的制造方法 |
CN102683288B (zh) * | 2012-05-04 | 2014-08-20 | 上海华力微电子有限公司 | 一种提高静态随机存储器读出冗余度的方法 |
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US20190259618A1 (en) * | 2018-02-19 | 2019-08-22 | Stmicroelectronics (Crolles 2) Sas | Process for forming a layer of a work function metal for a mosfet gate having a uniaxial grain orientation |
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