CN102203937A - 在工作区中局部提供嵌埋应变诱导半导体材料以调整形成于同一工作区中的晶体管的驱动电流 - Google Patents
在工作区中局部提供嵌埋应变诱导半导体材料以调整形成于同一工作区中的晶体管的驱动电流 Download PDFInfo
- Publication number
- CN102203937A CN102203937A CN2009801419630A CN200980141963A CN102203937A CN 102203937 A CN102203937 A CN 102203937A CN 2009801419630 A CN2009801419630 A CN 2009801419630A CN 200980141963 A CN200980141963 A CN 200980141963A CN 102203937 A CN102203937 A CN 102203937A
- Authority
- CN
- China
- Prior art keywords
- transistor
- strain
- channel region
- alloy
- service area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 147
- 230000001939 inductive effect Effects 0.000 title claims description 15
- 239000000463 material Substances 0.000 title description 20
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 91
- 239000000956 alloy Substances 0.000 claims abstract description 91
- 238000000034 method Methods 0.000 claims description 81
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 22
- 239000010703 silicon Substances 0.000 claims description 21
- 229910052710 silicon Inorganic materials 0.000 claims description 19
- 238000007906 compression Methods 0.000 claims description 15
- 230000006835 compression Effects 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 15
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 229910052732 germanium Inorganic materials 0.000 claims description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 8
- 229910052718 tin Inorganic materials 0.000 claims description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 1
- 230000003068 static effect Effects 0.000 abstract description 20
- 230000000875 corresponding effect Effects 0.000 description 25
- 230000008569 process Effects 0.000 description 20
- 238000004519 manufacturing process Methods 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 238000005530 etching Methods 0.000 description 11
- 238000003860 storage Methods 0.000 description 11
- 238000002955 isolation Methods 0.000 description 10
- 238000000151 deposition Methods 0.000 description 9
- 239000012212 insulator Substances 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- 230000007246 mechanism Effects 0.000 description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 7
- 230000004888 barrier function Effects 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 6
- 230000009467 reduction Effects 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 230000001936 parietal effect Effects 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 230000006399 behavior Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 239000003989 dielectric material Substances 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910000676 Si alloy Inorganic materials 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000002425 crystallisation Methods 0.000 description 2
- 230000008025 crystallization Effects 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000000737 periodic effect Effects 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000004576 sand Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- 238000012876 topography Methods 0.000 description 2
- 229910052724 xenon Inorganic materials 0.000 description 2
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 2
- 229910001339 C alloy Inorganic materials 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000001994 activation Methods 0.000 description 1
- 230000006978 adaptation Effects 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000009472 formulation Methods 0.000 description 1
- 230000003902 lesion Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007725 thermal activation Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823412—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
- H01L21/823425—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66636—Lateral single gate silicon transistors with source or drain recessed by etching or first recessed by etching and then refilled
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
- H01L29/7848—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
形成于同一工作区中的下拉晶体管和通道晶体管的驱动电流能力可基于不同的应变水平进行调整,该不同的应变水平通过在该工作区中提供至少一嵌埋半导体合金实现,以使该工作区具有简化的总体几何组态。因此,可基于最小沟道长度以及具有简化组态的该工作区形成静态RAM单元,从而避免传统上通过显着变更晶体管宽度调整该下拉晶体管和通道晶体管之驱动电流比例的复杂器件中常见的严重产量损失。
Description
技术领域
本发明涉及集成电路,尤其涉及复杂电路中的场效应晶体管的制造,该复杂电路包括存储器区,例如CPU的高速缓冲存储器(cache memory)。
背景技术
集成电路包括依据特定的电路布局形成于给定芯片面积上的大量电路元件,其中,晶体管元件是该集成电路中的主要半导体元件的其中之一。因此,各晶体管的特性显着影响该完整集成电路的总体性能。一般而言,目前可实施多种制程技术,其中,对于例如微处理器、储存芯片、ASIC(application specific IC;专用集成电路)等复杂电路,MOS技术因其在运行速度和/或功耗和/或成本效益方面的优越特性而成为当前最有前景的技术之一。在使用MOS技术制造复杂集成电路期间,可在包括结晶半导体层的基板上形成数百万个晶体管,亦即n沟道晶体管和/或p沟道晶体管。MOS晶体管,不论是n沟道晶体管还是p沟道晶体管,都包括所谓的pn结(pn-junction),其由高掺杂的源漏区与位于该源漏区之间经反向掺杂或弱掺杂(inversely or weakly doped)的沟道区之间的介面形成。该沟道区的电导率,亦即导电沟道的驱动电流能力,由形成于该沟道区上方并通过薄绝缘层与该沟道区隔离的栅极电极控制。因在该栅极电极施加适当的控制电压而形成导电沟道时,该沟道区的电导率取决于掺杂浓度、多数载流子的迁移率以及-朝该沟道区沿晶体管宽度方向的给定延伸程度-源漏区之间的距离,亦称为沟道长度。因此,结合在该栅极电极上施加该控制电压而在该绝缘层下方快速形成导电沟道的能力,该沟道区的电导率实质上决定该MOS晶体管的性能。因此,后者使得沟道长度缩减-以及因此而产生沟道电阻率的降低-从而成为增加集成电路运行速度的主要设计标准。
另一方面,MOS晶体管的驱动电流能力还取决于晶体管宽度,亦即晶体管垂直于电流流动方向的延伸程度,因此,栅极长度和沟道长度以及晶体管宽度是主要的几何参数,其实质上决定总体的晶体管特性以及“晶体管内部的”参数例如总体载流子迁移率、阈值电压,亦即在对栅极电极施加控制信号时在栅极绝缘层下方形成导电沟道的电压等。基于场效应晶体管,例如n沟道晶体管和/或p沟道晶体管,可创建更多的复杂电路元件,这取决于总体的电路布局。例如,寄存器、静态RAM(random access memory;随机存取存储器)形式的储存元件是复杂逻辑电路的重要组成部分。例如,在复杂CPU内核运行期间需要临时储存和检索大量的数据,其中,储存元件的运行速度和容量显着影响CPU的总体性能。依据复杂集成电路中使用的存储器阶层架构,可使用不同类型的存储器元件。例如,寄存器和静态RAM单元因其优越的访问时间而通常用于CPU内核中,而与寄存器或静态RAM单元相比,动态RAM元件因增加了位密度而优先用作工作存储器。通常,动态RAM单元包括储存电容和单个晶体管,不过,其中需要复杂存储器管理系统以周期性刷新该储存电容中储存的电荷,否则该电荷可因不可避免的漏电流而丢失。尽管动态RAM器件可具有很高的位密度,但必须结合周期性的刷新脉冲向储存电容充放电荷,从而使该些器件在速度和功耗方面的效率低于静态RAM单元。因此,静态RAM单元适合用作具有较高功耗的高速存储器,但因此需要多个晶体管元件以便能够可靠地储存信息位。
图1a显示静态RAM单元150的电路示意图,该单元150的组态是当今集成电路中常用的组态。单元150包括储存元件151,其包括两个反向耦接的反相器152a、152b,每个反相器包括一对晶体管100b、100c。例如,在CMOS器件中,晶体管100b、100c分别代表n沟道晶体管和p沟道晶体管,而在其他情况下,晶体管100b和100c可使用相同导电类型的晶体管,例如n沟道晶体管。图1a的右侧显示上半部分晶体管100c为n沟道晶体管时的相应布置。而且,通常可提供通道晶体管(pass transistor)或通栅晶体管(pass gate transistor)100a,以连接位单元151进行读写操作,在此期间通道晶体管(pass transistor)100a可将位单元151与相应的位线(未图示)连接,而通道晶体管100b的栅极电极代表存储器单元150的字线。因此,如图1a所示,需要六个晶体管储存一位信息,从而提供降低的位密度以利于存储器单元150较高的运行速度,如前所述。依据总体的设计方案,存储器单元150可要求各晶体管元件100a...100d在驱动电流能力方面具有不同的特性,以在读写操作期间提供可靠的操作行为。例如,在许多设计方案中,该些晶体管元件具有最小晶体管长度,其中,可选择使晶体管100b(亦即下拉晶体管(pull-down transistor))的驱动电流能力显着高于通道晶体管100a的驱动电流能力。在该些晶体管元件具有特定的最小晶体管长度的情况下,可通过适当调整各晶体管的宽度尺寸而使该些晶体管具有显著较高的驱动电流能力。
图1b显示呈半导体器件形式的硬件组态的一部分存储器单元150的顶视图。如图所示,器件150包括硅基半导体层102,其中定义工作区103,例如通过提供横向封闭工作区103的隔离结构104定义,从而定义晶体管100a、100b的几何形状和尺寸。如图所示,由于晶体管100a、100b具有相同的导电类型并经由同一节点,例如图1a中所示的节点153a、153b,而连接,因此晶体管100a、100b可形成于同一工作区103之中及上方。如前所述,晶体管100a、100b,亦即通道晶体管和下拉晶体管,可具有大体相同的长度,以使各栅极电极106具有大体相同的长度106l,而下拉晶体管100b的晶体管宽度103b可大于通道晶体管100a的晶体管宽度103a,以使该些晶体管具有不同的电流能力。
图1c显示沿图1b的线C的剖视图。如图所示,器件150包括基板101,其通常可为硅基板,如考虑SOI(silicon on insulator;绝缘体上硅)的话还可结合嵌埋绝缘层(未图示)。在基板101以及可能具有的嵌埋绝缘层上方可提供硅层形式的半导体层102,其中,可依据期望的形状形成隔离结构104,以便依据图1b所示的组态定义工作区103。亦即,工作区103在晶体管100b中的宽度为103b,在晶体管100a中的宽度为103a。在此方面,将半导体工作区理解为具有适当掺杂浓度和分布的半导体区,以在该工作区之中及上方形成一个或多个具有相同导电类型的晶体管元件。例如,当晶体管100a、100b代表n沟道晶体管时,若半导体层102向下延伸达到的深度显着大于晶体管100a、100b的深度尺寸,则工作区103可由p型轻掺杂半导体材料(例如p阱)构成。类似地,当晶体管100a、100b代表p沟道晶体管时,工作区103基本为n掺杂区。另外,在图1c所示的制造阶段中,晶体管100a、100b可包括栅极电极106,其例如由多晶硅材料构成,通过栅极绝缘层108与沟道区109隔离。而且,依据总体制程方案,可在栅极电极106的侧壁上形成侧间隙壁结构107。另外,源漏区110可形成于工作区103中并连接晶体管100a、100b。通常,可在栅极电极106以及源漏区110的上半部分中提供金属硅化物区111,以降低该些区域的接触电阻。
器件150通常基于下述制程形成。首先,蚀刻形成深入至半导体层102内一定深度的开孔,如提供嵌埋绝缘层的话,该开孔甚至可延伸至该嵌埋绝缘层,从而形成隔离结构104,例如浅沟槽隔离。随后,执行沉积和氧化制程以及随后的平坦化制程例如CMP(chemical mechanical polishing;化学机械抛光)制程等,以使用绝缘材料填充该相应开孔。在隔离结构104的制程序列期间,须使用先进的光刻技术以形成相应的蚀刻掩膜,其大致对应工作区103的形状,工作区103的形状要求定义较浅的沟槽,以获得期望的具有降低宽度103a的晶体管100a。随后,执行各注入序列以在工作区103中提供基本掺杂,该注入序列还可包括复杂注入技术以引入掺杂从而定义沟道掺杂等。接着,沉积、氧化适当的栅极绝缘层材料,随后沉积适当的栅极电极材料(例如多晶硅),从而形成栅极绝缘层108和栅极电极106。随后,使用先进的光刻技术和蚀刻技术图案化材料层,在该过程中可调整栅极电极106的实际长度106l,从而以极先进的制程技术形成约50纳米及以下的栅极长度。接着,注入适当的掺杂种类以形成源漏区110的一部分,随后形成间隙壁结构107或至少其中一部分,接着执行注入制程以定义深层源漏区,其中,如源漏区110中需要复杂的横向浓度分布,则可基于额外的间隙壁结构重复相应的注入序列。接着,可执行适当的退火制程,以便重新结晶工作区103中由注入引起的损伤,并激活源漏区110中的掺杂种类。应当了解,对于在上述定义范围内缩减的栅极长度,工作区103的复杂几何组态可导致例如沉积和蚀刻间隙壁材料以形成侧间隙壁107期间的制程不均匀性。通常,为形成侧间隙壁结构107,可先沉积适当的材料例如二氧化硅衬里(未图示),接着沉积氮化硅材料,随后基于广为接受的非等向性蚀刻配方相对该二氧化硅衬里选择性蚀刻该氮化硅材料。不过,在图1b所示的区域112中可观察到不规则性,由于前面执行的光刻制程(例如图案化栅极电极106等的光刻制程)期间形成的不均匀性,该不规则性进一步增加。因此,区域112显着影响器件150的后续制程,其可最终导致晶体管100b以及总体存储器单元150发生不可预期的行为。例如,在进一步的处理期间,为形成金属硅化物区111,可沉积例如镍、钴等难熔金属,接着对其处理以与下方的硅材料反应,其中,隔离结构103和间隙壁结构107通常可大致阻止高导电金属硅化物的形成。但是,由于前面产生的不规则性,可能形成漏电路径甚至短路,从而对晶体管100b的最终驱动电流能力带来负面影响,导致存储器单元150运行的稳定性和可靠性降低,从而对包括静态RAM区的复杂半导体器件造成严重的产量损失。
鉴于上述情况,本发明涉及方法及半导体器件,其中可避免或至少减轻上述一个或多个问题。
发明内容
一般而言,本发明涉及方法及半导体器件,其中,形成于同一工作区中及上方的晶体管元件的驱动电流能力可基于形成于各该晶体管的沟道区中的不同应变水平进行调整,其中,该不同的应变水平通过局部嵌埋半导体合金实现,从而简化该工作区的总体几何。在某些实施例中,该工作区大致呈矩形组态,以使各晶体管元件具有大致相同的晶体管宽度,同时提供显着不同的驱动电流能力。例如,在某些实施方式中,可调整存储器单元中晶体管元件的驱动电流能力,以获得存储器单元稳定运行所需的不同晶体管特性,同时保证总体晶体管几何较传统静态RAM单元简单。为使同一工作区内的晶体管具有不同的应变水平以及驱动电流,可在该工作区内以局部限制的方式提供嵌埋半导体合金,例如硅/锗、硅/锗/锡、硅/锡、硅/碳等,以使该些晶体管的各沟道区中获得不同的应变水平。例如,提供硅/锗材料,使其空间上限于需要较低驱动电流能力的n沟道晶体管元件可增加压缩应变水平,而另一方面,在该工作区中及上方形成的另一n沟道晶体管受到的影响很小,从而得以保持较高的载流子迁移率及驱动电流。在其他情况下,可以空间上限制的方式提供适当的嵌埋半导体合金以增强一个或多个晶体管的驱动电流,而在需要较低驱动电流的其他晶体管附近则不形成该相应半导体合金,或者形成半导体合金以进一步降低该些晶体管的驱动电流能力。因此,基于空间上限制的嵌埋半导体合金,可在硅基工作区中生成适当的应变水平,从而降低产量损失,该产量损失常见于由复杂半导体器件构成的静态RAM单元中,该复杂半导体器件所包括的晶体管具有约50纳米及以下的栅极长度。
这里所揭露的一种方法包括在形成于半导体器件之基板上方的工作区中及上方形成第一晶体管,其中该第一晶体管具有第一导电类型。该方法还包括在该工作区之中及上方形成第二晶体管,其中,该第二晶体管具有该第一导电类型。最后,该方法包括在该第一晶体管和/或该第二晶体管中提供第一嵌埋半导体合金和/或第二嵌埋半导体合金,以调整该第一晶体管和该第二晶体管之驱动电流能力的比例,从而在该第一晶体管的第一沟道区和该第二晶体管的第二沟道区中诱发不同的应变水平。
这里所揭露的另一实施例包括在半导体器件的半导体层中形成工作区,其中,该工作区具有基本恒定的宽度。该方法还包括在该工作区上方形成第一栅极电极结构,以定义第一沟道区。而且,在该工作区上方形成第二栅极电极结构,以定义第二沟道区。最后,该方法包括在该工作区中形成嵌埋半导体合金,以在该第一沟道区和该第二沟道区中诱发不同的应变水平。
这里所揭露的一种半导体器件包括形成于基板上方的半导体工作区以及形成于该半导体工作区中及上方的第一晶体管,其中,该第一晶体管包括具有第一应变水平的第一沟道区。该半导体器件还包括形成于该半导体工作区中及上方的第二晶体管,其中,该第二晶体管包括具有第二应变水平的第二沟道区,该第二应变水平不同于该第一应变水平,其中该第一应变水平和/或该第二应变水平受局部嵌埋于该半导体工作区中的应变诱导半导体合金的影响。
附图说明
本发明的其他实施例由所附的权利要求书定义,并藉由下面参照附图所作的详细说明变得更加清楚。
图1a显示传统静态RAM单元的电路示意图,该静态RAM单元包括两个反相器以及各自的通道晶体管。
图1b显示图1a的存储器单元的顶视图,其中,依据现有技术提供不同宽度的下拉晶体管和通道晶体管以调整驱动电流能力的比例。
图1c显示依据现有技术在图1b中所示的晶体管的剖视图。
图2a显示依据本发明实施例的部分工作区的顶视图,在该部分工作区中及上方形成具有相同导电类型和基本相同的晶体管长度的晶体管,通过嵌埋半导体合金形成不同的应变水平,可基于基本相同的晶体管宽度获得不同的驱动电流能力。
图2b至2e显示依据本发明实施例各制造阶段中包括具有不同驱动电流之两晶体管的部分工作区的剖视图,在各该制造阶段中局部提供嵌埋半导体合金以使该些晶体管获得不同的应变水平以及驱动电流。
图2f至2h显示依据本发明另一些实施例在同一工作区中通过一种或多种嵌埋半导体合金产生不同应变水平的半导体器件之各种变化的顶视图。
图2i显示依据本发明另一些实施例的半导体器件的剖视图,其中,通过嵌埋的半导体合金及相关的局部性应变松弛实现不同的应变水平。
图2j显示依据本发明另一些实施例的半导体器件的顶视图,其中,可在同一工作区中及上方提供两个以上的晶体管,以基于局部提供的嵌埋半导体合金为至少两个不同的晶体管类型提供不同的应变水平。
图2k显示依据本发明另一些实施例包括额外应变诱导机制的半导体器件,该应变诱导机制由形成于晶体管上方的应力介电材料构成,该些晶体管位于同一工作区中及上方。
具体实施方式
尽管本发明藉由参照下面的详细说明以及附图所描述之实施例来说明,但应当理解,该详细说明及附图并非意图将发明限于这里所揭露的特定实施例。相反,所述实施例仅示例本发明的各种实施方式,本发明的范围由所附权利要求书定义。
一般而言,本发明涉及方法及半导体器件,其中,基于局部限制的嵌埋半导体合金在半导体工作区中形成不同的应变水平,可对形成于同一工作区中的晶体管元件的驱动电流能力进行选择性调整,其中,在某些实施方式中,该工作区中晶体管宽度基本相同,以提供简化的总体几何,从而降低例如由复杂半导体器件构成的静态RAM单元中的产量损失,该复杂半导体器件所包括的晶体管具有约50纳米及以下的栅极长度。众所周知,半导体材料中的应变可显着影响载流子迁移率,其适合针对相同的晶体管组态设计晶体管的总体驱动电流能力。例如,在具有标准晶体组态的硅基结晶工作区中,亦即晶体管长度方向沿<110>晶轴或等效轴的<100>表面晶向,沿该晶体管长度方向的单轴拉伸应变分量的形成可导致电子迁移率的显着增加,从而能够增强n沟道晶体管的驱动电流。另一方面,沿该晶体管长度方向的单轴压缩应变分量可增加空穴的迁移率并降低电子迁移率,从而能够降低n沟道晶体管的驱动电流能力或增加p沟道晶体管的驱动电流。因此,籍由在相应晶体管元件的沟道区中局部提供各应变条件,可针对类似或基本相同的晶体管组态,例如类似或基本相同的晶体管宽度和长度,实现驱动电流能力的显着调整。因此,如前所述,可在例如静态RAM单元中使用复杂度降低的工作区的总体几何组态,同时提供有效的方案以基于嵌埋半导体合金调整驱动电流能力的比例,其中,可在该工作区中以局部限制的方式基于广为接受的选择性外延生长技术形成该嵌埋半导体合金,从而降低产量损失概率,该产量损失常见于相应晶体管宽度尺寸具有显着变化的传统RAM单元中。
应当了解,这里所揭露的原理适合应用于晶体管元件的栅极长度为50纳米及以下的半导体器件,因为在该些情况下,对于形成于工作区中具有不同宽度尺寸的晶体管元件可观察到严重产量损失。不过,本揭露还可应用于任意器件架构,而不论相应的关键尺寸,因此本揭露不限于特定的晶体管尺寸,除非在所附权利要求书或说明书中特别指出这样的限制。
下面参照图2a至2k详细描述实施例,其中还可适当参照图1a至1c。
图2a显示半导体器件250的顶视图,在一实施例中,半导体器件250可代表部分集成电路,其中,至少在一些器件区中,将在单个半导体工作区之中及上方形成具有相同导电类型的晶体管元件。在一实施例中,半导体器件250可代表具有参照图1a所述电性组态的静态RAM单元的其中一部分。半导体器件250可包括基板(未图示),在该基板上方形成半导体层(未图示),其中,由例如二氧化硅、氮化硅等适当绝缘材料组成的隔离结构204可定义半导体区203。如前所述,工作区可理解为没有中间隔离结构的连续半导体区,在其中及上方将形成具有相同导电类型的两个或更多晶体管元件。如图所示,工作区203可包括第一晶体管200a和第二晶体管200b,该两晶体管代表具有相同导电类型的晶体管,例如n沟道晶体管或p沟道晶体管。不过,器件250的总体组态要求该两晶体管具有不同的驱动电流能力。在一实施例中,第一晶体管200a可代表静态RAM单元的通道晶体管,而第二晶体管200b可代表下拉晶体管,其经由同一工作区203与通道晶体管200a连接。在一实施例中,工作区203具有宽度尺寸203a,对于第一晶体管200a和第二晶体管200b,该宽度尺寸基本一致。亦即,除任意制程变更外,第一晶体管和第二晶体管200a、200b可具有相同的宽度203a。在其他实施例中,第一晶体管和第二晶体管200a、200b的宽度203a可稍有不同,然而,在较不显着的程度下,如图1b的传统静态RAM单元所示,但该传统RAM单元中为下拉晶体管和通道晶体管提供明显不同的晶体管宽度以实现显着不同的驱动电流能力。依据这里所揭露的原理,如需要,晶体管宽度203a可具有程度不太显着的相应变化,因为如前所述,可基于嵌埋半导体合金在工作区203中形成不同的应变水平,以使晶体管200a、200b之间具有显着不同的驱动电流能力,从而使具有不太复杂的几何的工作区203与局部设置的嵌埋半导体合金联合提供期望的不同驱动电流能力。
在图2a所示的实施例中,容纳第一晶体管和第二晶体管200a、200b的部分工作区203大致呈矩形组态,以在光刻、蚀刻及其他制程期间提供有效的制程条件,从而增强总体制程的均匀性,这样即使半导体器件的关键尺寸为50纳米及以下仍可减少产量损失。在所示实施例中,晶体管200a、200b分别包括栅极电极206,在一些实施例中,该栅极的长度206l为50纳米或以下,其中,除制程变化外,各晶体管的长度206l可大致相等。另外,对应第一晶体管200a的部分工作区203可具有第一内部应变水平220a,而对应第二晶体管200b的部分工作区203可具有第二内部应变水平220b,其应变类型和/或大小不同于应变200a,其中,可在工作区203内以局部限制的方式提供至少一嵌埋半导体合金,例如硅/锗、硅/碳、硅/锗/锡、硅/锡等,以诱发应变水平220a、220b。亦即,应变水平220a、220b可代表相同类型的应变,例如拉伸应变或压缩应变,但其应变量不同。在其他情况下,第一晶体管和第二晶体管200a、200b可具有不同的应变类型,亦即压缩应变或拉伸应变,同时,如必要的话,该相应不同类型的应变也可具有不同的应变量。因此,如前所述,基于至少一嵌埋半导体合金在工作区203中局部形成的不同应变水平220a、220b可使相应沟道区中形成不同的载流子迁移率,从而使晶体管200a、200b具有不同的驱动电流能力。
图2b显示器件250沿图2a的线B的剖视图。如图所示,器件250可包括基板201,在该基板201上方形成半导体层202,在该半导体层202中藉由隔离结构(图2b未图示)例如隔离结构204(参照图2a)定义工作区203。基板201与半导体层202联合定义块状组态(bulk configuration),亦即半导体层202可代表基板201的结晶半导体材料的上半部分。在其他情况下,若在基板201与半导体层202之间提供嵌埋绝缘层(未图示),则可提供SOI组态。应当了解,如需要,通常可在器件250的不同器件区中提供块状组态和SOI组态。另外,在所示的制造阶段中,晶体管200a、200b可包括栅极电极206,其通过栅极绝缘层208与沟道区209隔离。另外,可使用例如氮化硅、二氧化硅等介电材料包覆栅极电极206,以在例如邻近第一晶体管200a的栅极电极206形成开口203c之蚀刻制程期间保护栅极电极206。为此目的,第一晶体管200a可包括间隙壁元件207以及覆盖层205。另一方面,第二晶体管200b和相应的部分工作区203可由间隙壁层207a覆盖。因此,通过间隙壁层207a,可调整工作区203的覆盖程度以及形成开口203c的相应蚀刻制程期间所保护的区域。类似地,通过选择间隙壁207的适当宽度207w,可调整开口203c与相邻的第一晶体管200a的沟道区209的横向距离,其中,还可考虑相应的蚀刻特性,例如各向同性蚀刻行为的程度等。类似地,可依据第一晶体管200a的期望应变水平选择深度203d。
形成半导体器件250的典型制程流程可包括下述制程。首先,与前面参照器件150所述类似,基于光刻、蚀刻、沉积和平坦化技术形成隔离结构204(参照图2a)以定义工作区203,其中,与传统器件相比,工作区203的几何组态具有较低的复杂性,从而抑制后续制造阶段中与制程相关的不均匀性。随后,如前所述,可形成适当的基本掺杂浓度,并依据广为接受的制程技术形成栅极绝缘层208和栅极电极206。在形成栅极电极206期间,还可提供例如由氮化硅材料构成的覆盖层205。随后,可籍由热活化式CVD(chemical vapour deposition;化学气相沉积)沉积具有期望厚度的间隙壁层207a,该厚度可大致对应间隙壁207的宽度207w。接着,使用光刻和非等向性蚀刻技术图案化间隙壁层207a,以提供如图所示的层207a和间隙壁元件207。随后,当执行后续蚀刻制程以形成开口203c时,可移除或不移除图案化层207a所使用的相应抗蚀剂掩模,其中,可针对由凹槽203c内的半导体合金诱发的特定期望应变水平调整参数207w和203d。应当了解,如果还将在其他器件区例如速度临界器件区中形成相应的开口203,则可使用同一制造序列,其中,可适当设定相应的参数207w和203d,以满足晶体管200a和相应速度临界器件的要求。
图2c显示下一制造阶段中的半导体器件250,其中,可基于广为接受的沉积配方执行选择性外延生长制程210,以在凹槽203c内形成半导体合金211。例如,若晶体管200a代表通道晶体管,其要求驱动电流能力低于晶体管200b,如前所述,晶体管200b代表存储器单元的下拉晶体管,则可提供由任意适当材料组成的嵌埋半导体合金211,以在沟道区209中诱发应变分量,从而降低该沟道区中的载流子迁移率。例如,如果晶体管200a、200b代表n沟道晶体管,则可提供硅/锗合金、硅/锡合金、硅/锗/锡合金等形式的半导体合金211,与硅相比,其具有较大的自然晶格常数,因而以压缩应变状态生长,从而在晶体管200a中提供单轴压缩应变分量。在其他情况下,当晶体管200a、200b代表n沟道晶体管时,若晶体管200a要求驱动能力高于晶体管200b,则可提供例如硅/碳形式的材料211,以提供拉伸应变分量。另一方面,若考虑p沟道晶体管,则可针对上述情形提供相反的材料组成。
图2d显示依据另一些实施例的半导体器件250,其中,可在第二晶体管200b附近以空间上限制的方式设置第二嵌埋半导体合金211b,以在相邻的晶体管200b的沟道区209中诱发适当类型的应变。为此目的,适当的掩膜或间隙壁层212a可覆盖第一晶体管200a和相应的部分工作区203,同时间隙壁元件212可结合覆盖层205保护第二晶体管200b的栅极电极206。因此,可针对第二晶体管200b在工作区203中蚀刻相应的开口,随后可基于广为接受的沉积技术执行选择性外延生长制程以形成嵌埋半导体合金211b。例如,合金211b可在晶体管200b中诱发应变以增强载流子迁移率。当晶体管200b为n沟道晶体管时,合金211b可基于硅/碳合金实现。因此,可基于两种不同的嵌埋半导体合金211a、211b进一步增强第一晶体管200a和第二晶体管200b的应变水平的不同。
图2e显示依据另一些实施例的半导体器件250,其中,可在第二晶体管200b附近以空间上限制的方式形成嵌埋半导体合金,例如半导体合金211b,而第一晶体管200a可不接受任何嵌埋半导体合金,从而将应变诱导机制大致限制于第二晶体管200b。
图2f显示器件250的顶视图,其中,第一晶体管200a可包括嵌埋半导体合金211a(参照图2c),以提供大致限制于晶体管200a的压缩应变水平,其对第二晶体管200b有极小的影响。出于方便,可将对应第二晶体管200b的工作区203中的局部应变水平标示为“中性”,其中,应当了解,嵌埋半导体合金211仍可对第二晶体管200b造成一定程度的影响。因此,对于n沟道晶体管,材料211a的压缩应变分量可降低第一晶体管200a的驱动电流能力,同时使第二晶体管200b大致保持期望的较高驱动电流能力,如静态RAM单元所需者,此时晶体管200a、200b分别代表通道晶体管和下拉晶体管时。
图2g显示依据本发明另一些实施例的半导体器件250,该实施例类似参照图2d所述的实施例。亦即,第一晶体管200a可包括局部限制的嵌埋半导体材料200a以提供压缩应变,同时第二晶体管200b可包括空间上限制的半导体合金211b以提供拉伸应变分量。因此,对于n沟道晶体管,晶体管200a可具有降低的驱动电流,而拉伸应变可增加第二晶体管200b的驱动电流,从而使晶体管200a、200b的总体驱动电流能力显着不同。
图2h显示依据图2e所示的实施例的半导体器件250的顶视图。因此,第二晶体管200b可包括嵌埋半导体合金211b,而第一晶体管200a大致为如前面所定义的“中性”。
因此,以局部限制的方式提供至少一嵌埋半导体合金可在连续工作区(例如工作区203)内实现有效“图案化”的驱动电路能力,从而有可能在静态RAM单元中使用简化几何组态的工作区。应当了解,对于p沟道晶体管,为实现工作区203内驱动电流能力的相应调整,可在需要增加驱动电流能力的晶体管中提供压缩应变诱导半导体合金和/或在需要降低驱动电流能力的晶体管中提供拉伸应变诱导半导体合金。
图2i显示依据本发明另一些实施例的半导体器件250,其中,可在两个或更多晶体管例如晶体管200a、200b附近形成局部限制而程度不太显着的嵌埋半导体合金例如合金211a,其中,通过松弛注入制程213实现各应变水平的局部图案化。为此目的,可使用如前面参照图2b和2c所述的制程序列,不过,其中,可针对两晶体管200a、200b形成相应的开口。随后,可针对两晶体管执行选择性外延生长制程,以提供半导体合金211a。应当了解,工作区203内较一致的表面形貌(topography)可增强蚀刻制程及随后的选择性外延生长制程期间的制程均匀性。接着,可基于广为接受的光刻技术形成抗蚀剂掩膜214,其中,掩膜214可暴露第二晶体管200b附近的期望部分,该第二晶体管200b中可能不需要半导体合金211a诱发的应变水平。随后,基于例如氙、硅等惰性种类执行注入制程213,以形成严重的晶体损伤,其可导致内在应变水平的相应降低。因此,第二晶体管200b的沟道区209内的载流子迁移率大致不受半导体合金211a的影响,其中,位于晶体管200b的源漏区中的合金211a的修改后的电子特性可增强驱动电流能力,其还可促进相应驱动电流的显着不同。因此,移除抗蚀剂掩膜214后,可形成源漏区,如参照半导体器件150所述,以继续后续处理。
应当了解,在其他情况下,例如提供半导体合金211b时,可使用其他掩膜方案,以籍由掩膜214暴露第一晶体管200a,从而获得邻近第一晶体管200a的松弛半导体合金211b。对于P沟道晶体管可使用前述的相同标准。亦即,提供单个嵌埋半导体合金并进行后续局部松弛的概念可应用于p沟道晶体管和n沟道晶体管,取决于总体的制程和器件要求。
图2j显示半导体器件250的顶视图,半导体器件250可代表典型存储器单元的其中一部分,其中可在工作区203附近、之中及上方形成两个通道晶体管200a以及两个下拉晶体管200b,该下拉晶体管横向封闭通道晶体管200a。在该组态中,可基于上述原理有效调整驱动电流能力。例如,如图所示,如晶体管为n沟道晶体管,对于需要较低驱动电流能力的通道晶体管200a,可在其中形成例如硅/锗形成的嵌埋半导体合金211a,以降低载流子迁移率。另一方面,下拉晶体管200b基本不受材料211a的影响,从而提供较高驱动电流。不过,应当了解,用以局部图案化工作区203中的应变水平的上述任何方案都可应用于如图2j所示的器件250中。
图2k显示依据本发明另一些实施例的半导体器件250,其中,除上述应变诱导机制外,还可提供至少另一应变诱导机制。在所示实施例中,在晶体管200a、200b的至少其中一者上方形成例如氮化硅材料、含氮碳化硅等形式的应力诱导介电材料。例如,除嵌埋半导体合金211a外,晶体管200a还可包括压缩应力介电层203a,其可增强晶体管200a中的总体应变诱导机制。在其他实施例中,晶体管200b可包括相应的应力诱导层230b,其可代表基本上为应力中性的层,其与层230b相比具有不同类型或大小的应力水平。因此,层230a、230b可提供范围宽广的制程边界,以使电流驱动能力具有期望的差值。例如,如果必须选择应变诱导参数,例如应变诱导材料211a的深度、组成,亦即与周围材料的晶格失配程度,与相应沟道区的横向距离等,以符合其他器件区中晶体管元件的要求,则层230a、230b可提供另一参数以调整驱动电流能力的总体差别。
可基于广为接受的制程技术,包括等离子辅助CVD技术,形成介电层230a、230b,其中,可选择适当的沉积参数以沉积具有不同应力水平和应变类型的材料,例如氮化硅、含氮碳化硅等。另外,如果必须使层230a、230b的其中一者或二者的相应内部应力条件独立于其他器件区中的这些层的应力特性而专门适应晶体管200a、200b,则可执行一个或多个应力松弛注入,其可基于具有与掩膜方案相关的氙注入实现。
因此,本发明提供方法及半导体器件,其中,形成于同一工作区之中及上方的晶体管的驱动电流能力可基于局部变更的应变水平进行调整,该应变水平基于至少一嵌埋半导体合金获得,从而使总体晶体管组态的复杂度降低,同时提供显着不同的驱动电流能力。在一些实施例中,静态RAM单元的下拉晶体管和通道晶体管可形成于同一工作区中而无需显着变更该些晶体管元件的晶体管宽度,因为可基于至少一嵌埋半导体合金提供的应变诱导机制有效调整驱动电流能力。例如,一个或多个通道晶体管和一个或多个下拉晶体管所在的同一工作区大致呈矩形组态,以改善光刻制程和蚀刻制程期间的状况。
在阅读说明书后,本领域的技术人员可容易地对本发明作进一步的修改和变更。因此,说明书仅为说明性质,目的在于教导本领域的技术人员执行本发明的一般方式。应当理解,所示方式应当被视作当前的优选实施例。
Claims (27)
1.一种方法,包括:
在形成于半导体器件的基板上方的工作区中及上方形成第一晶体管,该第一晶体管具有第一导电类型;
在该工作区中及上方形成第二晶体管,该第二晶体管具有该第一导电类型;以及
在该第一晶体管和该第二晶体管的至少其中一者中提供第一嵌埋半导体合金和第二嵌埋半导体合金的至少其中一者,以调整该第一晶体管和该第二晶体管的驱动电流能力的比例,从而在该第一晶体管的第一沟道区和该第二晶体管的第二沟道区中诱发不同的应变水平。
2.如权利要求1所述的方法,其中,调整该第一晶体管和该第二晶体管的驱动电流能力的比例包括在该第一晶体管中提供该第一嵌埋半导体合金,其中,该第一嵌埋半导体合金降低该第一沟道区中的载流子迁移率。
3.如权利要求2所述的方法,其中,该第一嵌埋半导体合金包括硅、锗、锡的至少其中一者。
4.如权利要求1所述的方法,其中,该第一晶体管和该第二晶体管具有基本相同的晶体管宽度。
5.如权利要求2所述的方法,还包括在该第二晶体管中提供第二嵌埋半导体合金,其中,该第二嵌埋半导体合金增加该第二晶体管的该第二沟道区中的载流子迁移率。
6.如权利要求5所述的方法,其中,该第二半导体合金包括碳。
7.如权利要求1所述的方法,其中,调整驱动电流能力的比例包括在该第二沟道区中提供该第二半导体合金,其中,该第二嵌埋半导体合金增加该第二沟道区中的载流子迁移率。
8.如权利要求7所述的方法,其中,该第二嵌埋半导体合金是该工作区中唯一的嵌埋半导体合金。
9.如权利要求2所述的方法,其中,该第一嵌埋半导体合金是该工作区中唯一的嵌埋半导体合金。
10.如权利要求1所述的方法,其中,提供第一嵌埋半导体合金和第二嵌埋半导体合金的至少其中一者包括在该第一晶体管和该第二晶体管的至少其中一者的源漏区中形成开口,并使用该第一嵌埋半导体合金和该第二嵌埋半导体合金的至少其中一者填充该开口。
11.如权利要求10所述的方法,其中,调整该第一沟道区和该第二沟道区中的不同应变水平包括调整该开口的尺寸、该开口相对该第一沟道区和该第二沟道区的距离,以及该第一嵌埋半导体合金和该第二嵌埋半导体合金的该至少其中一者的组成的其中一者。
12.如权利要求1所述的方法,其中,该第一嵌埋半导体合金和该第二嵌埋半导体合金的其中一者形成于该第一晶体管和该第二晶体管中,并且该方法还包括松弛该第一晶体管和该第二晶体管的其中一者中的该第一嵌埋半导体合金和该第二嵌埋半导体合金的该其中一者。
13.如权利要求1所述的方法,其中,还包括在该第一晶体管和该第二晶体管的至少其中一者上方形成应变诱导介电层。
14.如权利要求13所述的方法,其中,在该第一晶体管上方选择性形成压缩应变诱导介电层以及在该第一晶体管中形成该第一嵌埋半导体合金以诱发压缩应变。
15.如权利要求14所述的方法,其中,在该第二晶体管上方选择性形成拉伸应变诱导介电层。
16.一种方法,包括:
在半导体器件的半导体层中形成工作区,该工作区具有基本恒定的宽度;
在该工作区上方形成第一栅极电极结构以定义第一沟道区;
在该工作区上方形成第二栅极电极结构以定义第二沟道区;以及
在该工作区中形成嵌埋半导体合金以在该第一沟道区和该第二沟道区中诱发不同的应变水平。
17.如权利要求16所述的方法,其中,形成该嵌埋半导体合金包括邻近该第一栅极电极结构选择性形成压缩应变诱导半导体合金,以在该第一沟道区中诱发压缩应变,同时在该第二沟道区中保持较低的压缩应变水平。
18.如权利要求16所述的方法,其中,形成该嵌埋半导体合金包括邻近该第二栅极电极结构选择性形成拉伸应变诱导半导体合金,以在该第二沟道区中诱发拉伸应变,同时在该第一沟道区中保持较低的拉伸应变水平。
19.如权利要求16所述的方法,其中,形成该嵌埋半导体合金包括邻近该第一栅极电极结构选择性形成压缩应变诱导半导体合金,以在该第一沟道区中诱发压缩应变,以及邻近该第二栅极电极结构选择性形成拉伸应变诱导半导体合金,以在该第二沟道区中诱发拉伸应变。
20.如权利要求16所述的方法,还包括在该工作区上方形成一个或多个额外栅极电极结构。
21.一种半导体器件,包括:
半导体工作区,形成于基板上方;
第一晶体管,形成于该半导体工作区中及上方,该第一晶体管包括具有第一应变水平的第一沟道区;以及
第二晶体管,形成于该半导体工作区中及上方,该第二晶体管包括具有第二应变水平的第二沟道区,该第二应变水平不同于该第一应变水平,该第一应变水平和该第二应变水平的至少其中一者受局部嵌埋于该半导体工作区中的应变诱导半导体合金的影响。
22.如权利要求21所述的半导体器件,其中,该第一晶体管和该第二晶体管的晶体管宽度基本相同。
23.如权利要求21所述的半导体器件,其中,该应变诱导半导体合金在空间上限于该第一晶体管,以在该第一沟道区中诱发第一类型的应变,同时在该第二沟道区中诱发的该第一类型的应变不太显着。
24.如权利要求22所述的半导体器件,其中,该应变诱导半导体合金在空间上限于该第二晶体管,以在该第二沟道区中诱发第二类型的应变,同时在该第一沟道区中诱发的该第二类型的应变不太显着,其中,该第二类型的应变不同于该第一类型的应变。
25.如权利要求21所述的半导体器件,其中,该第一晶体管和该第二晶体管代表存储器单元的晶体管,并且其中,该第一晶体管的第一驱动电流能力低于该第二晶体管的第二驱动电流能力。
26.如权利要求25所述的半导体器件,其中,该工作区包括一个或多个额外晶体管。
27.如权利要求26所述的半导体器件,其中,该一个或多个额外晶体管的其中第一者具有与该第一晶体管相同的组态,而该一个或多个额外晶体管的其中第二者具有与该第二晶体管相同的组态。
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102008045034.0 | 2008-08-29 | ||
DE102008045034A DE102008045034B4 (de) | 2008-08-29 | 2008-08-29 | Durchlassstromeinstellung für Transistoren, die im gleichen aktiven Gebiet hergestellt sind, durch lokales Vorsehen eines eingebetteten verformungsinduzierenden Halbleitermaterials in dem aktiven Gebiet |
US12/507,544 | 2009-07-22 | ||
US12/507,544 US8034669B2 (en) | 2008-08-29 | 2009-07-22 | Drive current adjustment for transistors formed in the same active region by locally providing embedded strain-inducing semiconductor material in the active region |
PCT/EP2009/006259 WO2010022971A1 (en) | 2008-08-29 | 2009-08-28 | Drive current adjustment for transistors formed in the same active region by locally providing embedded strain inducing semiconductor material in the active region |
Publications (2)
Publication Number | Publication Date |
---|---|
CN102203937A true CN102203937A (zh) | 2011-09-28 |
CN102203937B CN102203937B (zh) | 2015-09-23 |
Family
ID=41724039
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN200980141963.0A Active CN102203937B (zh) | 2008-08-29 | 2009-08-28 | 半导体器件及其制造方法 |
Country Status (6)
Country | Link |
---|---|
US (1) | US8034669B2 (zh) |
JP (1) | JP5926559B2 (zh) |
KR (1) | KR101520441B1 (zh) |
CN (1) | CN102203937B (zh) |
DE (1) | DE102008045034B4 (zh) |
GB (1) | GB2475208B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102683288A (zh) * | 2012-05-04 | 2012-09-19 | 上海华力微电子有限公司 | 一种提高静态随机存储器读出冗余度的方法 |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102008054075B4 (de) * | 2008-10-31 | 2010-09-23 | Advanced Micro Devices, Inc., Sunnyvale | Halbleiterbauelement mit Abgesenktem Drain- und Sourcebereich in Verbindung mit einem Verfahren zur komplexen Silizidherstellung in Transistoren |
US8466018B2 (en) | 2011-07-26 | 2013-06-18 | Globalfoundries Inc. | Methods of forming a PMOS device with in situ doped epitaxial source/drain regions |
CN102280379B (zh) * | 2011-09-05 | 2016-06-01 | 上海集成电路研发中心有限公司 | 一种应变硅nmos器件的制造方法 |
CN102738084B (zh) * | 2012-05-04 | 2014-09-03 | 上海华力微电子有限公司 | 一种提高静态随机存储器写入冗余度的方法 |
CN103579244B (zh) * | 2013-10-18 | 2016-08-17 | 上海华力微电子有限公司 | 静态随机存储器及其写入冗余度改善的方法 |
US20190259618A1 (en) * | 2018-02-19 | 2019-08-22 | Stmicroelectronics (Crolles 2) Sas | Process for forming a layer of a work function metal for a mosfet gate having a uniaxial grain orientation |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070164364A1 (en) * | 2006-01-06 | 2007-07-19 | Hirohisa Kawasaki | Semiconductor device using sige for substrate and method for fabricating the same |
US20070236982A1 (en) * | 2006-03-29 | 2007-10-11 | International Business Machines Corporation | Asymmetrical memory cells and memories using the cells |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6962039B2 (en) * | 2002-03-11 | 2005-11-08 | Robert Greenhoe | Lawn striping assembly |
US7307273B2 (en) * | 2002-06-07 | 2007-12-11 | Amberwave Systems Corporation | Control of strain in device layers by selective relaxation |
JP2005079194A (ja) * | 2003-08-28 | 2005-03-24 | Sony Corp | 半導体素子及び半導体装置の製造方法 |
JP4763967B2 (ja) * | 2004-01-29 | 2011-08-31 | 富士通セミコンダクター株式会社 | 半導体記憶装置の製造方法 |
JP2005286341A (ja) * | 2004-03-30 | 2005-10-13 | Samsung Electronics Co Ltd | 低ノイズ及び高性能のlsi素子、レイアウト及びその製造方法 |
US7023018B2 (en) | 2004-04-06 | 2006-04-04 | Texas Instruments Incorporated | SiGe transistor with strained layers |
US6984564B1 (en) | 2004-06-24 | 2006-01-10 | International Business Machines Corporation | Structure and method to improve SRAM stability without increasing cell area or off current |
JP2007027194A (ja) | 2005-07-12 | 2007-02-01 | Renesas Technology Corp | 半導体装置 |
JP2007027461A (ja) * | 2005-07-19 | 2007-02-01 | Sumida Corporation | コアおよびコアを備えたインダクタ |
DE102005041225B3 (de) * | 2005-08-31 | 2007-04-26 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung vertiefter verformter Drain/Source-Gebiete in NMOS- und PMOS-Transistoren |
US7605447B2 (en) * | 2005-09-22 | 2009-10-20 | International Business Machines Corporation | Highly manufacturable SRAM cells in substrates with hybrid crystal orientation |
KR100714479B1 (ko) * | 2006-02-13 | 2007-05-04 | 삼성전자주식회사 | 반도체 집적 회로 장치 및 그 제조 방법 |
DE102006015090B4 (de) * | 2006-03-31 | 2008-03-13 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung unterschiedlicher eingebetteter Verformungsschichten in Transistoren |
US7449753B2 (en) * | 2006-04-10 | 2008-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Write margin improvement for SRAM cells with SiGe stressors |
US7436696B2 (en) * | 2006-04-28 | 2008-10-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Read-preferred SRAM cell design |
US8114790B2 (en) * | 2006-05-31 | 2012-02-14 | Tokyo Electron Limited | Plasma CVD method, silicon nitride film formation method, semiconductor device manufacturing method, and plasma CVD apparatus |
US8384138B2 (en) | 2006-06-14 | 2013-02-26 | Texas Instruments Incorporated | Defect prevention on SRAM cells that incorporate selective epitaxial regions |
JP2008060408A (ja) * | 2006-08-31 | 2008-03-13 | Toshiba Corp | 半導体装置 |
JP4896789B2 (ja) * | 2007-03-29 | 2012-03-14 | 株式会社東芝 | 半導体装置の製造方法 |
US20090189227A1 (en) * | 2008-01-25 | 2009-07-30 | Toshiba America Electronic Components, Inc. | Structures of sram bit cells |
US8624295B2 (en) * | 2008-03-20 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | SRAM devices utilizing strained-channel transistors and methods of manufacture |
US7838372B2 (en) * | 2008-05-22 | 2010-11-23 | Infineon Technologies Ag | Methods of manufacturing semiconductor devices and structures thereof |
-
2008
- 2008-08-29 DE DE102008045034A patent/DE102008045034B4/de not_active Expired - Fee Related
-
2009
- 2009-07-22 US US12/507,544 patent/US8034669B2/en active Active
- 2009-08-28 GB GB1104064.9A patent/GB2475208B/en not_active Expired - Fee Related
- 2009-08-28 KR KR1020117007150A patent/KR101520441B1/ko active IP Right Grant
- 2009-08-28 CN CN200980141963.0A patent/CN102203937B/zh active Active
- 2009-08-28 JP JP2011524261A patent/JP5926559B2/ja active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070164364A1 (en) * | 2006-01-06 | 2007-07-19 | Hirohisa Kawasaki | Semiconductor device using sige for substrate and method for fabricating the same |
US20070236982A1 (en) * | 2006-03-29 | 2007-10-11 | International Business Machines Corporation | Asymmetrical memory cells and memories using the cells |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102683288A (zh) * | 2012-05-04 | 2012-09-19 | 上海华力微电子有限公司 | 一种提高静态随机存储器读出冗余度的方法 |
CN102683288B (zh) * | 2012-05-04 | 2014-08-20 | 上海华力微电子有限公司 | 一种提高静态随机存储器读出冗余度的方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20110044331A (ko) | 2011-04-28 |
KR101520441B1 (ko) | 2015-05-15 |
US20100052068A1 (en) | 2010-03-04 |
GB2475208B (en) | 2012-08-08 |
JP2012510712A (ja) | 2012-05-10 |
GB2475208A (en) | 2011-05-11 |
JP5926559B2 (ja) | 2016-05-25 |
CN102203937B (zh) | 2015-09-23 |
US8034669B2 (en) | 2011-10-11 |
GB201104064D0 (en) | 2011-04-20 |
DE102008045034B4 (de) | 2012-04-05 |
DE102008045034A1 (de) | 2010-04-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11705458B2 (en) | Integrated circuit devices and fabrication techniques | |
JP5229587B2 (ja) | 成長型ナノFinトランジスタ | |
US7768051B2 (en) | DRAM including a vertical surround gate transistor | |
US7696032B2 (en) | Semiconductor device including a crystal semiconductor layer, its fabrication and its operation | |
US6967351B2 (en) | Finfet SRAM cell using low mobility plane for cell stability and method for forming | |
TWI506706B (zh) | 金屬氧化物半導體裝置結構用之鰭狀物的形成方法 | |
US10170475B2 (en) | Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region | |
US10038075B2 (en) | Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region | |
CN102203937B (zh) | 半导体器件及其制造方法 | |
CN101894793A (zh) | 具有硅通孔的集成电路系统及其制造方法 | |
US9419015B1 (en) | Method for integrating thin-film transistors on an isolation region in an integrated circuit and resulting device | |
US8525248B2 (en) | Memory cell comprising a floating body, a channel region, and a diode | |
KR100861301B1 (ko) | 반도체 소자 및 그의 제조방법 | |
US20090294868A1 (en) | Drive current adjustment for transistors formed in the same active region by locally inducing different lateral strain levels in the active region | |
TWI836152B (zh) | 電晶體結構 | |
CN102044437B (zh) | 用于制造半导体器件的方法 | |
WO2010022971A1 (en) | Drive current adjustment for transistors formed in the same active region by locally providing embedded strain inducing semiconductor material in the active region |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant |