JP5925546B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP5925546B2 JP5925546B2 JP2012064435A JP2012064435A JP5925546B2 JP 5925546 B2 JP5925546 B2 JP 5925546B2 JP 2012064435 A JP2012064435 A JP 2012064435A JP 2012064435 A JP2012064435 A JP 2012064435A JP 5925546 B2 JP5925546 B2 JP 5925546B2
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- 239000004065 semiconductor Substances 0.000 title claims description 49
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 239000010410 layer Substances 0.000 claims description 102
- 238000000034 method Methods 0.000 claims description 35
- 238000005530 etching Methods 0.000 claims description 28
- 239000011229 interlayer Substances 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 12
- 238000001459 lithography Methods 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 239000011368 organic material Substances 0.000 claims 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 15
- 125000006850 spacer group Chemical group 0.000 description 8
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 229910004298 SiO 2 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 239000012467 final product Substances 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920000620 organic polymer Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 239000004734 Polyphenylene sulfide Substances 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- ISQINHMJILFLAQ-UHFFFAOYSA-N argon hydrofluoride Chemical compound F.[Ar] ISQINHMJILFLAQ-UHFFFAOYSA-N 0.000 description 1
- 235000013405 beer Nutrition 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 150000002894 organic compounds Chemical class 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229920006122 polyamide resin Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920001955 polyphenylene ether Polymers 0.000 description 1
- 229920000069 polyphenylene sulfide Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229920006337 unsaturated polyester resin Polymers 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76811—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving multiple stacked pre-patterned masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Description
Claims (11)
- 半導体装置の層間膜に設けられた金属膜上に複数の直方体柱部をリソグラフィーにより形成する工程と、
前記各直方体柱部の側面に絶縁膜を形成し、前記各直方体柱部の側面に前記絶縁膜の一部がサイドウォールとして残るように、前記絶縁膜を選択的に除去する工程と、
前記複数の直方体柱部を除去する工程と、
前記複数の直方体柱部を除去する工程後に残った複数のサイドウォールを有機平坦化膜で被覆し、開口を有するフォトレジストマスクを前記有機平坦化膜上に形成し、前記フォトレジストマスクを介して前記有機平坦化膜をエッチングし、前記フォトレジストマスクおよび前記有機平坦化膜のエッチング後に残存する前記有機平坦化膜を除去する工程と、ここで、前記フォトレジストマスクは、平面視で、前記複数のサイドウォールのうちで連続するn(≧2)個のサイドウォールが前記フォトレジストマスクの前記開口に含まれるように形成されており、
開口を有する第1マスクを形成する工程であって、前記n個のサイドウォールのうち、互いに隣り合う第1サイドウォールおよび第2サイドウォールの間にある前記層間膜に前記開口が位置するように、前記第1マスクを形成する工程と、
前記第1マスクを介して前記層間膜をエッチングする第1エッチング工程と、
前記開口の外部に残った前記第1マスクを除去し、前記金属膜上に存在する前記複数のサイドウォールを除去し、前記層間膜上に残った前記金属膜を第2マスクとして前記層間膜をエッチングする第2エッチング工程と
を具備し、
前記開口は、平面視で、前記第1サイドウォールおよび前記第2サイドウォールの間の幅よりも広く、前記第1サイドウォールの上面の一部と前記第2サイドウォールの上面の一部とを包含する大きさを持つ
半導体装置の製造方法。 - 請求項1に記載された半導体装置の製造方法であって、
前記第1エッチング工程によって、前記第1サイドウォールおよび前記第2サイドウォールの間の前記層間膜にビアが形成され、
前記ビアは、前記層間膜の厚さ全体を通じて延びている
半導体装置の製造方法。 - 請求項1に記載された半導体装置の製造方法であって、
前記第2エッチング工程によって、前記開口の外部にある前記層間膜に溝が形成され、
前記溝は、前記層間膜の厚さの途中まで延びている
半導体装置の製造方法。 - 請求項1に記載された半導体装置の製造方法であって、
前記各サイドウォールの厚み及びスペースの少なくとも一方は、前記リソグラフィの実行時における解像度以下である
半導体装置の製造方法。 - 請求項1に記載された半導体装置の製造方法であって、
前記各直方体柱部は、化学蒸着又はスピンーオン法により堆積された有機材料である
半導体装置の製造方法。 - 請求項5に記載された半導体装置の製造方法であって、
前記各直方体柱部は、アモルファスカーボンにより形成される
半導体装置の製造方法。 - 請求項1に記載された半導体装置の製造方法であって、
前記第1エッチング工程によって、前記第1サイドウォールおよび前記第2サイドウォールの間の前記層間膜にビアが形成され、
前記第2エッチング工程によって、前記開口の外部にある前記層間膜に溝が形成され、
前記ビア及び前記溝は、銅により埋め込まれる
半導体装置の製造方法。 - 請求項1に記載された半導体装置の製造方法であって、
前記第1マスクは、上層のフォトレジスト層、及び、下層の有機平坦化層を備えている
半導体装置の製造方法。 - 請求項1に記載された半導体装置の製造方法であって、
前記複数の直方体柱部を除去する工程では、前記複数の直方体柱部を引き抜く
半導体装置の製造方法。 - 請求項1に記載された半導体装置の製造方法であって、
前記第1マスクは、複数の開口を備え、
前記複数の開口の各々は、前記第2マスクと共に、単一のビアパターンを規定する
半導体装置の製造方法。 - 請求項1に記載された半導体装置の製造方法であって、
前記第1マスクは、前記第2マスクと共に、隣接する一連のビアパターンを規定する、細長い開口を備えている
半導体装置の製造方法。
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US201161468365P | 2011-03-28 | 2011-03-28 | |
US61/468365 | 2011-03-28 |
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JP2012209552A JP2012209552A (ja) | 2012-10-25 |
JP5925546B2 true JP5925546B2 (ja) | 2016-05-25 |
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JP (1) | JP5925546B2 (ja) |
Families Citing this family (22)
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US8586482B2 (en) * | 2011-06-29 | 2013-11-19 | International Business Machines Corporation | Film stack including metal hardmask layer for sidewall image transfer fin field effect transistor formation |
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KR20130070351A (ko) * | 2011-12-19 | 2013-06-27 | 에스케이하이닉스 주식회사 | 반도체장치 제조 방법 |
JP6017928B2 (ja) * | 2012-11-09 | 2016-11-02 | 東京エレクトロン株式会社 | プラズマエッチング方法及びプラズマエッチング装置 |
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US8859384B1 (en) * | 2013-08-01 | 2014-10-14 | International Business Machines Corporation | Inductor formation with sidewall image transfer |
US20150118832A1 (en) * | 2013-10-24 | 2015-04-30 | Applied Materials, Inc. | Methods for patterning a hardmask layer for an ion implantation process |
US9997405B2 (en) | 2014-09-30 | 2018-06-12 | Lam Research Corporation | Feature fill with nucleation inhibition |
US20160314964A1 (en) | 2015-04-21 | 2016-10-27 | Lam Research Corporation | Gap fill using carbon-based films |
CN106373880B (zh) * | 2015-07-22 | 2021-05-25 | 联华电子股份有限公司 | 半导体元件及其形成方法 |
US10814349B2 (en) | 2015-10-09 | 2020-10-27 | Asm Ip Holding B.V. | Vapor phase deposition of organic films |
US10695794B2 (en) | 2015-10-09 | 2020-06-30 | Asm Ip Holding B.V. | Vapor phase deposition of organic films |
US10453701B2 (en) * | 2016-06-01 | 2019-10-22 | Asm Ip Holding B.V. | Deposition of organic films |
US10373820B2 (en) | 2016-06-01 | 2019-08-06 | Asm Ip Holding B.V. | Deposition of organic films |
WO2018075755A1 (en) * | 2016-10-20 | 2018-04-26 | Tokyo Electron Limited | Method of reducing overlay error in via to grid patterning |
US9806153B1 (en) * | 2017-02-09 | 2017-10-31 | International Business Machines Corporation | Controlling channel length for vertical FETs |
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CN112768351B (zh) * | 2019-11-06 | 2022-06-10 | 长鑫存储技术有限公司 | 一种图形形成方法 |
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JP3854247B2 (ja) * | 2003-05-30 | 2006-12-06 | 株式会社東芝 | 不揮発性半導体記憶装置 |
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JP2010135624A (ja) * | 2008-12-05 | 2010-06-17 | Tokyo Electron Ltd | 半導体装置の製造方法 |
JP5361406B2 (ja) * | 2009-01-20 | 2013-12-04 | 株式会社東芝 | 半導体装置の製造方法 |
FR2960657B1 (fr) * | 2010-06-01 | 2013-02-22 | Commissariat Energie Atomique | Procede de lithographie a dedoublement de pas |
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US20120329268A1 (en) | 2012-12-27 |
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