JP5920383B2 - 半導体装置を製造する方法及び半導体装置 - Google Patents
半導体装置を製造する方法及び半導体装置 Download PDFInfo
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Description
(特徴1)半導体装置が、IGBTのコレクタ領域であって、表面に露出するp型のコレクタ領域と、ダイオードのカソード領域であって、前記表面に露出するとともにコレクタ領域に隣接するn型のカソード領域と、コレクタ領域及びカソード領域に対して深い側から隣接するとともにカソード領域よりもn型不純物濃度が低いn型のバッファ領域と、バッファ領域に対して深い側から隣接するとともにバッファ領域よりもn型不純物濃度が低いn型のドリフト領域を有する。なお、「深い側」とは、表面(すなわち、コレクタ領域及びカソード領域が露出している表面)から遠い側を意味する。
(特徴2)酸化膜を形成するステップと表面を加熱するステップが実施される範囲が、カソード領域とコレクタ領域の境界近傍のコレクタ領域の表面を含む。なお、特徴2は、前記2つのステップの実施時にカソード領域及びコレクタ領域が形成されていることを限定するものではなく、上記2つのステップが実施される範囲が、最終的に製造される半導体装置のカソード領域とコレクタ領域に対して上記の関係を満たしていればよい。したがって、前記2つのステップの実施時にカソード領域及びコレクタ領域が形成されていなくてもよい。
(特徴3)半導体装置において、コレクタ領域がカソード領域を取り囲むように配置されている。酸化膜を形成するステップと表面を加熱するステップが実施される範囲が、カソード領域を取り囲むようにコレクタ領域の表面に配置されている。なお、特徴3は、前記2つのステップの実施時にカソード領域及びコレクタ領域が形成されていることを限定するものではなく、上記2つのステップが実施される範囲が、最終的に製造される半導体装置のカソード領域とコレクタ領域に対して上記の関係を満たしていればよい。したがって、前記2つのステップの実施時にカソード領域及びコレクタ領域が形成されていなくてもよい。
(特徴4)酸化膜を形成するステップと表面を加熱するステップが実施される範囲に、カソード領域の少なくとも一部の表面が含まれていない。カソード領域の前記少なくとも一部の表面の酸化膜を除去するステップと、酸化膜除去後のカソード領域の前記少なくとも一部の表面を加熱するステップをさらに有する。電極を形成するステップでは、加熱後のカソード領域の前記少なくとも一部の表面にも電極を形成する。なお、特徴4は、酸化膜を形成するステップと表面を加熱するステップの実施時にカソード領域が形成されていることを限定するものではなく、これら2つのステップが実施される範囲が、最終的に製造される半導体装置のカソード領域に対して上記の関係を満たしていればよい。したがって、前記2つのステップの実施時にカソード領域が形成されていなくてもよい。
(特徴5)溝が、カソード領域の近傍にのみ形成されている。
本明細書または図面に説明した技術要素は、単独であるいは各種の組み合わせによって技術的有用性を発揮するものであり、出願時請求項記載の組み合わせに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。
12:半導体基板
12a:上面
12b:下面
14:上部電極
16:下部電極
20:エミッタ領域
22:ボディ領域
28:ドリフト領域
30:バッファ領域
32:コレクタ領域
34:アノード領域
36:カソード領域
40:ゲート絶縁膜
42:ゲート電極
50:絶縁膜
52:制御電極
60:溝
62:酸化膜
90:IGBT領域
92:ダイオード領域
Claims (7)
- 半導体装置を製造する方法であって、
半導体基板の表面をアンモニア過水に曝すことで、前記表面に酸化膜を形成するステップと、
光を照射することによって前記酸化膜に覆われた前記表面を加熱することで、前記表面に溝を形成するステップと、
前記酸化膜を除去して前記表面を露出させるステップと、
露出させた前記表面に電極を形成するステップ、
を有する方法。 - 前記半導体装置が、
IGBTのコレクタ領域であって、前記表面に露出するp型のコレクタ領域と、
ダイオードのカソード領域であって、前記表面に露出するとともに前記コレクタ領域に隣接するn型のカソード領域と、
前記コレクタ領域及び前記カソード領域に対して深い側から隣接するとともに前記カソード領域よりもn型不純物濃度が低いn型のバッファ領域と、
前記バッファ領域に対して深い側から隣接するとともに前記バッファ領域よりもn型不純物濃度が低いn型のドリフト領域、
を有する請求項1の方法。 - 前記酸化膜を形成する前記ステップと前記表面を加熱する前記ステップが実施される範囲が、前記カソード領域と前記コレクタ領域の境界近傍の前記コレクタ領域の表面を含む請求項2の方法。
- 前記半導体装置において、前記コレクタ領域が前記カソード領域を取り囲むように配置されており、
前記酸化膜を形成する前記ステップと前記表面を加熱する前記ステップが実施される範囲が、前記カソード領域を取り囲むように前記コレクタ領域の表面に配置されている請求項2または3の方法。 - 前記酸化膜を形成する前記ステップと前記表面を加熱する前記ステップが実施される範囲に、前記カソード領域の少なくとも一部の表面が含まれておらず、
前記カソード領域を形成すべき範囲に、n型不純物を注入して前記カソード領域を形成するステップと、
前記カソード領域の前記少なくとも一部の表面の自然酸化膜を除去するステップと、
前記自然酸化膜除去後の前記カソード領域の前記少なくとも一部の表面を加熱することによって前記カソード領域内のn型不純物を活性化させるステップ、
をさらに有し、
前記電極を形成するステップでは、前記n型不純物を活性化させる加熱の後の前記カソード領域の前記少なくとも一部の表面にも電極を形成する、
請求項2〜4の何れか一項の方法。 - IGBTとダイオードが形成された半導体基板を有する半導体装置であって、
半導体基板が、
前記ダイオードのカソード領域であって、前記半導体基板の表面に露出するn型のカソード領域と、
前記IGBTのコレクタ領域であって、前記表面に露出し、前記カソード領域に隣接し、前記カソード領域を取り囲むように配置されているp型のコレクタ領域と、
前記コレクタ領域及び前記カソード領域に対して深い側から隣接するとともに前記カソード領域よりもn型不純物濃度が低いn型のバッファ領域と、
前記バッファ領域に対して深い側から隣接するとともに前記バッファ領域よりもn型不純物濃度が低いn型のドリフト領域、
を有し、
前記コレクタ領域の表面に、前記カソード領域の周囲を取り囲む溝が形成されており、
前記コレクタ領域と前記バッファ領域が前記溝が形成されている範囲で他の位置に比べて前記溝の深さ方向にシフトするように、前記コレクタ領域と前記バッファ領域が前記溝に沿って湾曲しており、
前記溝の内面に、前記コレクタ領域が露出しており、前記バッファ領域が露出しておらず、
前記コレクタ領域の前記表面と前記カソード領域の表面に、電極が形成されており、
前記電極が、前記溝の内部に充填されており、前記溝の内部で前記コレクタ領域に接している、
半導体装置。 - 前記溝が、前記カソード領域の近傍にのみ形成されている請求項6の半導体装置。
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JP2014040414A JP5920383B2 (ja) | 2014-03-03 | 2014-03-03 | 半導体装置を製造する方法及び半導体装置 |
US14/620,768 US9437719B2 (en) | 2014-03-03 | 2015-02-12 | Method for manufacturing semiconductor device having grooved surface |
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