JP5892430B2 - セラミック電子部品、及びセラミック電子部品の製造方法 - Google Patents
セラミック電子部品、及びセラミック電子部品の製造方法 Download PDFInfo
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- JP5892430B2 JP5892430B2 JP2013531363A JP2013531363A JP5892430B2 JP 5892430 B2 JP5892430 B2 JP 5892430B2 JP 2013531363 A JP2013531363 A JP 2013531363A JP 2013531363 A JP2013531363 A JP 2013531363A JP 5892430 B2 JP5892430 B2 JP 5892430B2
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- Engineering & Computer Science (AREA)
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Description
次に、Cu、Fe、及びMnの含有モル量を、CuO、Fe2O3、及びMn2O3に換算し、上述の範囲にした理由について詳述する。
Ni−Zn系フェライトでは、融点が1026℃と低いCuOをフェライト磁器組成物中に含有させることにより、より低温での焼成が可能となり、焼結性を向上させることができる。
Fe2O3を化学量論組成から減量させ、Feの一部をMnで置換する形態でMn2O3を含有させることにより、比抵抗ρが低下するのを回避でき、絶縁性の向上を図ることができる。
まず、磁性体シートとして、実施例2で作製した試料番号203の磁性体シートを用意した。
磁性体シートとして、実施例2で作製した試料番号209の磁性体シートを用意した。
試料番号203a〜203d、及び209a〜209dの各試料について、温度85℃、湿度85%RHの高湿度環境下、9Vの直流電圧を印加して耐湿負荷試験を行った。
磁性体シートとして、実施例2で作製した試料番号203の磁性体シートを用意した。
実施例2で作製した試料番号209の磁性体シートを用意した。そして、実施例4で作製した非磁性体シート及び非磁性体シート用仮焼粉末を使用し、導電性材料としてCuに代えてAgを使用し、焼成雰囲気を大気で行った以外は、本発明試料と同様の方法・手順で試料番号209eの試料を作製した。
IEC規格のIEC61000-4-2に準拠し、放電試験を行った。すなわち、8kV、4kV、3kV、2kVの接触放電を行い、放電電圧波形を測定し、そのピーク電圧、及びピーク電圧から30ns後に観測された電圧を測定した。尚、印加回数は20回とした。
そして、ピーク電圧Vpeakの最大値が700V未満の試料を良好(○)、700V以上の試料を不良(×)とした。また、30ns後に観測された電圧が100V以下となる試料を良(○)、100Vを超える試料を不良(×)とした。
2 第1の非磁性体層
3 第2の非磁性体層
4 コイル導体
5b 外部電極
6b 外部電極
9 第3のビア電極(ビア電極)
10a〜10f、34a〜34g 磁性体シート(第1のセラミックグリーンシート)
11a、11b、35a、35b 非磁性体シート(第2のセラミックグリーンシート)
14b〜14g ビア導体(第2のビア導体)
14a、14h ビア導体(第3のビア導体)
29 不活性ガス
30 空洞部
31a、31b 放電電極
32 補助電極
Claims (10)
- コイル導体と、該コイル導体と離間して配されたビア電極とが磁性体層に埋設されたセラミック電子部品であって、
前記コイル導体及び前記ビア電極がCuを主成分とする導電性材料で形成されると共に、前記磁性体層がフェライト磁器組成物で形成され、
前記フェライト磁器組成物が、少なくともFe、Mn、Ni、及びZnを含有し、Cuの含有モル量がCuOに換算して0〜5mol%であり、かつ、FeをFe2O3に換算したときの含有モル量xmol%、及びMnをMn2O3に換算したときの含有モル量ymol%を(x,y)で表したときに、(x,y)が、A(25,1)、B(47,1)、C(47,7.5)、D(45,7.5)、E(45,10)、F(35,10)、G(35,7.5)、及びH(25,7.5)で囲まれる領域にあり、
前記コイル導体、前記ビア電極、及び前記磁性体層が同時焼成されてなることを特徴とするセラミック電子部品。 - 前記Znの含有モル量が、ZnOに換算して33mol%以下であることを特徴とする請求項1記載のセラミック電子部品。
- 前記Znの含有モル量が、ZnOに換算して6mol%以上であることを特徴とする請求項1又は請求項2記載のセラミック電子部品。
- 前記磁性体層が、一対の非磁性体層に挟着されると共に、前記非磁性体層の主面に形成された外部電極間が前記ビア電極を介して電気的に接続され、
かつ、前記非磁性体層が、前記コイル導体、前記ビア電極、及び前記磁性体層と共に、同時焼成されてなることを特徴とする請求項1乃至請求項3のいずれかに記載のセラミック電子部品。 - 前記磁性体層の少なくとも一方の主面に非磁性体層が形成されると共に、
該非磁性体層及び前記磁性体層のうちのいずれか一方に、不活性ガスを充満した空洞部が形成され、かつ、少なくとも一対の放電電極が、前記空洞部内で所定間隔を有して対向状に配され、
前記放電電極が、Cuを主成分とする導電性材料で形成され、
かつ、前記非磁性体層が、前記コイル導体、前記ビア電極、及び前記磁性体層と共に、同時焼成されてなることを特徴とする請求項1乃至請求項3のいずれかに記載のセラミック電子部品。 - 前記一対の放電電極同士が補助電極を介して接続されると共に、
前記補助電極は、Cuを主成分とする導電性材料が、前記非磁性体層を形成する非磁性体材料中及び前記磁性体層を形成する磁性体材料中のいずれか一方に分散されていることを特徴とする請求項5記載のセラミック電子部品。 - 前記非磁性体層は、少なくともFe、Mn、及びZnを含有し、Niを含有せず、Cuの含有モル量がCuOに換算して0〜5mol%であり、かつ、FeをFe2O3に換算したときの含有モル量xmol%、及びMnをMn2O3に換算したときの含有モル量ymol%を(x,y)で表したときに、(x,y)が、(x,y)が、A(25,1)、B(47,1)、C(47,7.5)、D(45,7.5)、E(45,10)、F(35,10)、G(35,7.5)、及びH(25,7.5)で囲まれる領域にあることを特徴とする請求項4乃至請求項6のいずれかに記載のセラミック電子部品。
- Cuの含有モル量がCuOに換算して0〜5mol%であり、かつ、FeをFe2O3に換算したときの含有モル量xmol%、及びMnをMn2O3に換算したときの含有モル量ymol%を(x,y)で表したときに、(x,y)が、A(25,1)、B(47,1)、C(47,7.5)、D(45,7.5)、E(45,10)、F(35,10)、G(35,7.5)、及びH(25,7.5)で囲まれる領域を満たすようにFe化合物、Mn化合物、Cu化合物、Zn化合物、及びNi化合物を秤量し、これら秤量物を混合した後、仮焼して第1の仮焼粉末を作製する第1の仮焼工程と、
前記第1の仮焼粉末から磁性体層となるべき第1のセラミックグリーンシートを作製するセラミックグリーンシート作製工程と、
前記第1のセラミックグリーンシートの所定箇所に貫通孔を形成する貫通孔形成工程と、
Cuを主成分とする導電性ペーストを前記第1のセラミックグリーンシートに塗布して所定パターンの導電膜を形成すると共に、前記導電性ペーストを前記貫通孔に充填して前記導電膜間を導通させる第1のビア導体と、前記導電膜と電気的に絶縁されたビア電極となるべき第2のビア導体とを形成する導電膜・ビア導体形成工程と、
前記導電膜及び第1及び第2のビア導体が形成された第1のセラミックグリーンシートを所定順序で積層し、積層体を形成する積層体形成工程と、
Cu−Cu2Oの平衡酸素分圧以下の焼成雰囲気で前記積層体を焼成する焼成工程とを含んでいることを特徴とするセラミック電子部品の製造方法。 - Cuの含有モル量がCuOに換算して0〜5mol%であり、かつ、FeをFe2O3に換算したときの含有モル量xmol%、及びMnをMn2O3に換算したときの含有モル量ymol%を(x,y)で表したときに、(x,y)が、前記A〜Hで囲まれる領域を満たすようにFe化合物、Mn化合物、Cu化合物、及びZn化合物を秤量し、これら秤量物を混合した後、仮焼して第2の仮焼粉末を作製する第2の仮焼工程と、
前記第2の仮焼粉末から非磁性体層となるべき第2のセラミックグリーンシートを作製する第2のセラミックグリーンシート作製工程と、
前記第2のセラミックグリーンシートの所定箇所に前記第2のビア導体と導通可能となるように第3のビア導体を形成する第3のビア導体形成工程とを含み、
前記積層体形成工程は、前記第1のセラミックグリーンシート及び前記第2のセラミックグリーンシートを所定順序で積層し、積層体を形成することを特徴とする請求項8記載のセラミック電子部品の製造方法。 - 磁性体材料又は非磁性体材料とCuを主成分とした導電性材料とを混合し、前記導電性材料が前記磁性体材料中又は前記非磁性体材料中に分散した混合ペーストを作製する混合ペースト作製工程と、
焼成により消失する熱分解性樹脂材料を含有した樹脂ペーストを作製する樹脂ペースト作製工程と、
前記第1又は前記第2のセラミックグリーンシート上に混合ペーストを塗布し、補助電極となるべき所定パターンの混合部を形成する混合部形成工程と、
前記混合部が形成された前記第1又は前記第2のセラミックグリーンシート上に放電電極となるべき所定パターンの電極膜を形成する電極膜形成工程と、
前記電極膜の形成された前記第1又は前記第2のセラミックグリーンシート上に前記樹脂ペーストを塗布し、空洞部となるべき樹脂塗布部を作製する樹脂塗布部作製工程とを含み、
前記積層体形成工程で前記樹脂塗布部が形成された前記第1又は前記第2のセラミックグリーンシートに別の第1又は第2のセラミックグリーンシートを積層し、
前記焼成工程で前記樹脂塗布部を消失させて前記空洞部を形成することを特徴とする請求項9記載のセラミック電子部品の製造方法。
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