JP5868968B2 - 電子デバイスを製造する方法 - Google Patents
電子デバイスを製造する方法 Download PDFInfo
- Publication number
- JP5868968B2 JP5868968B2 JP2013517641A JP2013517641A JP5868968B2 JP 5868968 B2 JP5868968 B2 JP 5868968B2 JP 2013517641 A JP2013517641 A JP 2013517641A JP 2013517641 A JP2013517641 A JP 2013517641A JP 5868968 B2 JP5868968 B2 JP 5868968B2
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- Prior art keywords
- alloy
- silver
- copper
- cobalt
- nickel
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- 238000000034 method Methods 0.000 title claims description 97
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 229910001128 Sn alloy Inorganic materials 0.000 claims description 147
- 229910052751 metal Inorganic materials 0.000 claims description 100
- 239000002184 metal Substances 0.000 claims description 100
- 230000004888 barrier function Effects 0.000 claims description 99
- 239000000203 mixture Substances 0.000 claims description 92
- 239000000758 substrate Substances 0.000 claims description 88
- 238000009736 wetting Methods 0.000 claims description 79
- 238000007772 electroless plating Methods 0.000 claims description 75
- 229910001316 Ag alloy Inorganic materials 0.000 claims description 73
- 238000007747 plating Methods 0.000 claims description 49
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 47
- 229910052737 gold Inorganic materials 0.000 claims description 47
- 239000010931 gold Substances 0.000 claims description 47
- 229910000679 solder Inorganic materials 0.000 claims description 39
- 229910000881 Cu alloy Inorganic materials 0.000 claims description 38
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 24
- 229910000990 Ni alloy Inorganic materials 0.000 claims description 23
- 239000004020 conductor Substances 0.000 claims description 22
- WDHWFGNRFMPTQS-UHFFFAOYSA-N cobalt tin Chemical compound [Co].[Sn] WDHWFGNRFMPTQS-UHFFFAOYSA-N 0.000 claims description 20
- 229910000531 Co alloy Inorganic materials 0.000 claims description 19
- 229910000640 Fe alloy Inorganic materials 0.000 claims description 18
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 16
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 16
- 229910052796 boron Inorganic materials 0.000 claims description 16
- 229910017052 cobalt Inorganic materials 0.000 claims description 16
- 239000010941 cobalt Substances 0.000 claims description 16
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 16
- 229910052698 phosphorus Inorganic materials 0.000 claims description 16
- 239000011574 phosphorus Substances 0.000 claims description 16
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 13
- 229910052721 tungsten Inorganic materials 0.000 claims description 13
- 239000010937 tungsten Substances 0.000 claims description 13
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 12
- 229910001080 W alloy Inorganic materials 0.000 claims description 12
- 229910052759 nickel Inorganic materials 0.000 claims description 12
- UYKQQBUWKSHMIM-UHFFFAOYSA-N silver tungsten Chemical compound [Ag][W][W] UYKQQBUWKSHMIM-UHFFFAOYSA-N 0.000 claims description 12
- WCRLBNSUFIYRKQ-UHFFFAOYSA-N [Ag].[Fe].[Sn] Chemical compound [Ag].[Fe].[Sn] WCRLBNSUFIYRKQ-UHFFFAOYSA-N 0.000 claims description 11
- HXEUYGWISODFLF-UHFFFAOYSA-N [Ag].[Sn].[Co] Chemical compound [Ag].[Sn].[Co] HXEUYGWISODFLF-UHFFFAOYSA-N 0.000 claims description 11
- DSKPCFOTNCDNME-UHFFFAOYSA-N [Co].[Ag].[Cu].[Sn] Chemical compound [Co].[Ag].[Cu].[Sn] DSKPCFOTNCDNME-UHFFFAOYSA-N 0.000 claims description 11
- WGLUFVNYIRPMST-UHFFFAOYSA-N [Co].[Cu].[Ag] Chemical compound [Co].[Cu].[Ag] WGLUFVNYIRPMST-UHFFFAOYSA-N 0.000 claims description 11
- ZJHIEQGQFJJLBM-UHFFFAOYSA-N [Co].[Sn].[Cu] Chemical compound [Co].[Sn].[Cu] ZJHIEQGQFJJLBM-UHFFFAOYSA-N 0.000 claims description 11
- BGHIFTNQWHSCCM-UHFFFAOYSA-N [Cu].[Ag].[Sn].[Fe] Chemical compound [Cu].[Ag].[Sn].[Fe] BGHIFTNQWHSCCM-UHFFFAOYSA-N 0.000 claims description 11
- WMGRVUWRBBPOSZ-UHFFFAOYSA-N [Cu].[Ni].[Ag].[Sn] Chemical compound [Cu].[Ni].[Ag].[Sn] WMGRVUWRBBPOSZ-UHFFFAOYSA-N 0.000 claims description 11
- WWSYNEUATFTEFP-UHFFFAOYSA-N [Fe].[Cu].[Ag] Chemical compound [Fe].[Cu].[Ag] WWSYNEUATFTEFP-UHFFFAOYSA-N 0.000 claims description 11
- ORTNWICOMQLICI-UHFFFAOYSA-N [Fe].[Cu].[Sn] Chemical compound [Fe].[Cu].[Sn] ORTNWICOMQLICI-UHFFFAOYSA-N 0.000 claims description 11
- PQJKKINZCUWVKL-UHFFFAOYSA-N [Ni].[Cu].[Ag] Chemical compound [Ni].[Cu].[Ag] PQJKKINZCUWVKL-UHFFFAOYSA-N 0.000 claims description 11
- RYTYSMSQNNBZDP-UHFFFAOYSA-N cobalt copper Chemical compound [Co].[Cu] RYTYSMSQNNBZDP-UHFFFAOYSA-N 0.000 claims description 11
- SQWDWSANCUIJGW-UHFFFAOYSA-N cobalt silver Chemical compound [Co].[Ag] SQWDWSANCUIJGW-UHFFFAOYSA-N 0.000 claims description 11
- YOCUPQPZWBBYIX-UHFFFAOYSA-N copper nickel Chemical compound [Ni].[Cu] YOCUPQPZWBBYIX-UHFFFAOYSA-N 0.000 claims description 11
- OVMJVEMNBCGDGM-UHFFFAOYSA-N iron silver Chemical compound [Fe].[Ag] OVMJVEMNBCGDGM-UHFFFAOYSA-N 0.000 claims description 11
- NNIPDXPTJYIMKW-UHFFFAOYSA-N iron tin Chemical compound [Fe].[Sn] NNIPDXPTJYIMKW-UHFFFAOYSA-N 0.000 claims description 11
- MOFOBJHOKRNACT-UHFFFAOYSA-N nickel silver Chemical compound [Ni].[Ag] MOFOBJHOKRNACT-UHFFFAOYSA-N 0.000 claims description 11
- 239000010956 nickel silver Substances 0.000 claims description 11
- WRAOBLMTWFEINP-UHFFFAOYSA-N [Sn].[Ag].[Ni] Chemical compound [Sn].[Ag].[Ni] WRAOBLMTWFEINP-UHFFFAOYSA-N 0.000 claims description 10
- VRUVRQYVUDCDMT-UHFFFAOYSA-N [Sn].[Ni].[Cu] Chemical compound [Sn].[Ni].[Cu] VRUVRQYVUDCDMT-UHFFFAOYSA-N 0.000 claims description 10
- IYRDVAUFQZOLSB-UHFFFAOYSA-N copper iron Chemical compound [Fe].[Cu] IYRDVAUFQZOLSB-UHFFFAOYSA-N 0.000 claims description 10
- UORVGPXVDQYIDP-UHFFFAOYSA-N borane Chemical compound B UORVGPXVDQYIDP-UHFFFAOYSA-N 0.000 claims description 8
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 7
- 239000004332 silver Substances 0.000 claims description 7
- 229910000085 borane Inorganic materials 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims 1
- 239000000956 alloy Substances 0.000 claims 1
- 238000009713 electroplating Methods 0.000 claims 1
- 239000010410 layer Substances 0.000 description 138
- 230000008569 process Effects 0.000 description 31
- 239000000463 material Substances 0.000 description 18
- 238000001465 metallisation Methods 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 239000010949 copper Substances 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 7
- 230000008901 benefit Effects 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- CLDVQCMGOSGNIW-UHFFFAOYSA-N nickel tin Chemical compound [Ni].[Sn] CLDVQCMGOSGNIW-UHFFFAOYSA-N 0.000 description 6
- 235000012431 wafers Nutrition 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 230000008859 change Effects 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 230000004913 activation Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000003638 chemical reducing agent Substances 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005536 corrosion prevention Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910000510 noble metal Inorganic materials 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- OFNHPGDEEMZPFG-UHFFFAOYSA-N phosphanylidynenickel Chemical compound [P].[Ni] OFNHPGDEEMZPFG-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 238000007704 wet chemistry method Methods 0.000 description 1
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Description
[適用例1]電子デバイスを製造する方法であって、
基板を準備する工程と、
少なくとも前記基板の一部の上にバリア金属を無電解めっきする工程と、
はんだぬれ性を有する実質的に金を含まない湿潤層を前記バリア金属上に無電解めっきする工程と
を備える方法。
[適用例2]適用例1に記載の方法であって、実質的に金を含まない湿潤層を無電解めっき
する工程は、ボランを含む無電解めっき浴を用いて実現される方法。
[適用例3]適用例1に記載の方法であって、前記基板を準備する工程は、1または複数の
電気接点パッドを備える基板を準備する工程を含み、少なくとも前記基板の一部の上に前記バリア金属を無電解めっきする工程は、前記1または複数の電気接点パッド上に前記バリア金属をめっきする工程を含む方法。
[適用例4]適用例1に記載の方法であって、前記基板を準備する工程は、1または複数の
基板貫通ビア導電体を備える基板を準備する工程を含み、少なくとも前記基板の一部の上に前記バリア金属を無電解めっきする工程は、前記1または複数の基板貫通ビア導電体上に前記バリア金属をめっきする工程を含む方法。
[適用例5]適用例1に記載の方法であって、前記基板を準備する工程は、1または複数の
ビアを有する基板を準備する工程を含み、少なくとも前記基板の一部の上に前記バリア金属を無電解めっきする工程は、前記1または複数のビアの壁の上に前記バリア金属をめっきする工程を含む方法。
[適用例6]適用例1に記載の方法であって、少なくとも前記基板の一部の上に前記バリア
金属を無電解めっきする工程は、コバルトを含むバリア金属をめっきする工程を含む方法。
[適用例7]適用例1に記載の方法であって、少なくとも前記基板の一部の上に前記バリア
金属を無電解めっきする工程は、0.2マイクロメートルから1マイクロメートルの範囲、ならびに前記範囲に含まれるすべての値および範囲の厚さで前記バリア金属をめっきする工程を含む方法。
[適用例8]適用例1に記載の方法であって、実質的に金を含まない湿潤層を無電解めっき
する工程は、錫を無電解めっきする工程を含む方法。
[適用例9]適用例1に記載の方法であって、実質的に金を含まない湿潤層を無電解めっき
する工程は、銀または銀合金を無電解めっきする工程を含む方法。
[適用例10]適用例1に記載の方法であって、実質的に金を含まない湿潤層を無電解めっき
する工程は、3〜4原子百分率のタングステンを含む銀−タングステン合金を無電解めっきする工程を含む方法。
[適用例11]適用例1に記載の方法であって、実質的に金を含まない湿潤層を無電解めっき
する工程は、コバルト−錫合金、コバルト−銅合金、コバルト−銀合金、コバルト−銅−錫合金、コバルト−銅−銀合金、コバルト−銀−錫合金、または、コバルト−銅−銀−錫合金を無電解めっきする工程を含む方法。
[適用例12]適用例11に記載の方法であって、さらに、前記実質的に金を含まない湿潤層
にホウ素および/またはリンを組み込む工程を備える方法。
[適用例13]適用例1に記載の方法であって、実質的に金を含まない湿潤層を無電解めっき
する工程は、ニッケル−銅合金、ニッケル−銀合金、ニッケル−銅−銀合金、ニッケル−銅−錫合金、ニッケル−銀−錫合金、または、ニッケル−銅−銀−錫合金を無電解めっきする工程を含む方法。
[適用例14]適用例13に記載の方法であって、さらに、前記実質的に金を含まない湿潤層
にホウ素および/またはリンを組み込む工程を備える方法。
[適用例15]適用例1に記載の方法であって、実質的に金を含まない湿潤層を無電解めっき
する工程は、鉄−錫合金、鉄−銅合金、鉄−銀合金、鉄−銅−錫合金、鉄−銅−銀合金、鉄−銀−錫合金、または、鉄−銅−銀−錫合金を無電解めっきする工程を含む方法。
[適用例16]適用例15に記載の方法であって、さらに、前記実質的に金を含まない湿潤層
にホウ素および/またはリンを組み込む工程を備える方法。
[適用例17]適用例1に記載の方法であって、実質的に金を含まない湿潤層を無電解めっき
する工程は、第1の組成を有する所定厚さのニッケル合金および第2の組成を有する所定厚さのニッケル合金を無電解めっきする工程を含む方法。
[適用例18]適用例1に記載の方法であって、実質的に金を含まない湿潤層を無電解めっき
する工程は、第1の組成を有する所定厚さのコバルト−錫合金および第2の組成を有する所定厚さのコバルト−錫合金を無電解めっきする工程を含む方法。
[適用例19]適用例1に記載の方法であって、少なくとも前記基板の一部の上に前記バリア
金属を無電解めっきする工程、および、はんだぬれ性を有する実質的に金を含まない湿潤層を無電解めっきする工程は、所定温度範囲で無電解めっき浴組成を用いて前記バリア金属をめっきし、別の温度範囲で前記無電解めっき浴組成を用いて前記湿潤層をめっきすることによって実現される方法。
[適用例20]電子デバイスを製造する方法であって、
1または複数の電気接点パッドならびに/もしくは1または複数の基板貫通ビア導電体を含む基板を準備する工程と、
ニッケル元素およびコバルト元素の少なくとも一方を含むバリア金属を、前記1または複数の電気接点パッドならびに/もしくは前記1または複数の基板貫通ビア導電体の少なくとも一部の上に、0.2マイクロメートルから1マイクロメートルの範囲、ならびに前記範囲に含まれるすべての値および範囲の厚さで無電解めっきする工程と、
1.錫または錫合金;
2.3〜4原子百分率のタングステンを含む銀−タングステン合金;
3.コバルト−錫合金、コバルト−銅合金、コバルト−銀合金、コバルト−銅−錫合金、コバルト−銅−銀合金、コバルト−銀−錫合金、または、コバルト−銅−銀−錫合金;
4.ニッケル−銅合金、ニッケル−銀合金、ニッケル−銅−銀合金、ニッケル−銅−錫合金、ニッケル−銀−錫合金、または、ニッケル−銅−銀−錫合金; 5.鉄−錫合金、鉄−銅合金、鉄−銀合金、鉄−銅−錫合金、鉄−銅−銀合金、鉄−銀−錫合金、または、鉄−銅−銀−錫合金;
6.第1の組成を有する所定厚さのニッケル合金および第2の組成を有する所定厚さのニッケル合金;
7.第1の組成を有する所定厚さのコバルト合金および第2の組成を有する所定厚さのコバルト合金;ならびに
8.第1の組成を有する所定厚さの鉄合金および第2の組成を有する所定厚さの鉄合金
の内の少なくとも1つを無電解めっきして、前記バリア金属と接触し、はんだぬれ性を有する実質的に金を含まない湿潤層を形成する工程と、
前記実質的に金を含まない湿潤層へのはんだ接点を形成する工程と
を備える方法。
[適用例21]メタライゼーションスタックを含む電子デバイスであって、前記メタライゼー
ションスタックは、無電解めっきされたバリア金属および無電解めっきされた実質的に金を含まない湿潤層を備え、前記バリア金属は前記湿潤層に接触し、前記湿潤層は、はんだによって湿潤可能である電子デバイス。
[適用例22]適用例21に記載の電子デバイスであって、さらに、前記バリア金属によって
少なくとも部分的に覆われた電気接点パッドを備える電子デバイス。
[適用例23]適用例21に記載の電子デバイスであって、さらに、前記バリア金属によって
少なくとも部分的に覆われた基板貫通ビア導電体を備える電子デバイス。
[適用例24]適用例21に記載の電子デバイスであって、前記基板は、1または複数の基板
貫通ビアを有し、前記1または複数のビアを形成する前記基板の壁は、前記バリア金属によって少なくとも部分的に覆われ、
前記電子デバイスは、さらに、前記湿潤層に接触して前記1または複数のビアを実質的に満たすはんだを備える電子デバイス。
[適用例25]適用例21に記載の電子デバイスであって、前記バリア金属は、0.2マイク
ロメートルから1マイクロメートルの範囲、ならびに前記範囲に含まれるすべての値および範囲の厚さを有する電子デバイス。
[適用例26]適用例21に記載の電子デバイスであって、前記バリア金属はコバルトを含む
電子デバイス。
[適用例27]適用例21に記載の電子デバイスであって、前記湿潤層は錫または錫合金を含
む電子デバイス。
[適用例28]適用例21に記載の電子デバイスであって、前記湿潤層は、3〜4原子百分率
のタングステンを含む銀−タングステン合金を含む電子デバイス。
[適用例29]適用例21に記載の電子デバイスであって、前記湿潤層は、コバルト−錫合金
、コバルト−銅合金、コバルト−銀合金、コバルト−銅−錫合金、コバルト−銅−銀合金、コバルト−銀−錫合金、または、コバルト−銅−銀−錫合金を含む電子デバイス。
[適用例30]適用例29に記載の電子デバイスであって、前記湿潤層は、さらに、ホウ素お
よび/またはリンを含む電子デバイス。
[適用例31]適用例21に記載の電子デバイスであって、前記湿潤層は、ニッケル−銅合金
、ニッケル−銀合金、ニッケル−銅−銀合金、ニッケル−銅−錫合金、ニッケル−銀−錫合金、または、ニッケル−銅−銀−錫合金を含む電子デバイス。
[適用例32]適用例31に記載の電子デバイスであって、前記湿潤層は、さらに、ホウ素お
よび/またはリンを含む電子デバイス。
[適用例33]適用例21に記載の電子デバイスであって、前記湿潤層は、鉄−錫合金、鉄−
銅合金、鉄−銀合金、鉄−銅−錫合金、鉄−銅−銀合金、鉄−銀−錫合金、または、鉄−銅−銀−錫合金を含む電子デバイス。
[適用例34]適用例33に記載の電子デバイスであって、前記湿潤層は、さらに、ホウ素お
よび/またはリンを含む電子デバイス。
[適用例35]適用例21に記載の電子デバイスであって、前記湿潤層は、第1の組成を有す
る所定厚さのニッケル−錫合金および第2の組成を有する所定厚さのニッケル−錫合金を含む電子デバイス。
[適用例36]適用例21に記載の電子デバイスであって、前記湿潤層は、第1の組成を有す
る所定厚さのコバルト−錫合金および第2の組成を有する厚さのコバルト−錫合金を含む電子デバイス。
[適用例37]適用例21に記載の電子デバイスであって、前記バリア金属は、0.2マイク
ロメートルから1マイクロメートルの範囲(ならびに前記範囲に含まれるすべての値および範囲)の厚さを有し、前記バリア金属は、ニッケル元素およびコバルト元素の少なくとも一方を含み、
前記湿潤層は、
1.錫または錫合金;
2.3〜4原子百分率のタングステンを含む銀−タングステン合金;
3.コバルト−錫合金、コバルト−銅合金、コバルト−銀合金、コバルト−銅−錫合金、コバルト−銅−銀合金、コバルト−銀−錫合金、または、コバルト−銅−銀−錫合金;
4.ニッケル−銅合金、ニッケル−銀合金、ニッケル−銅−銀合金、ニッケル−銅−錫合金、ニッケル−銀−錫合金、または、ニッケル−銅−銀−錫合金; 5.鉄−錫合金、鉄−銅合金、鉄−銀合金、鉄−銅−錫合金、鉄−銅−銀合金、鉄−銀−錫合金、または、鉄−銅−銀−錫合金;
6.第1の組成を有する所定厚さのニッケル合金および第2の組成を有する所定厚さのニッケル合金;
7.第1の組成を有する所定厚さのコバルト合金および第2の組成を有する所定厚さのコバルト合金;もしくは
8.第1の組成を有する所定厚さの鉄合金および第2の組成を有する所定厚さの鉄合金
を含み、
前記電子デバイスは、さらに、前記バリア金属によって少なくとも部分的覆われた1または複数の電気接点パッド、ならびに/もしくは、前記バリア金属によって少なくとも部分的に覆われた1または複数の基板貫通ビア導電体と、前記湿潤層に接触するはんだとを備える電子デバイス。
Claims (19)
- 電子デバイスを製造する方法であって、
基板を準備する工程と、
少なくとも前記基板の一部の上にバリア金属を無電解めっきする工程と、
はんだぬれ性を有する実質的に金を含まない湿潤層を前記バリア金属上に無電解めっきする工程と
を備え、
少なくとも前記基板の一部の上に前記バリア金属を無電解めっきする工程、および、はんだぬれ性を有する実質的に金を含まない湿潤層を無電解めっきする工程は、所定温度範囲で無電解めっき浴組成を用いて前記バリア金属をめっきし、別の温度範囲で前記無電解めっき浴組成を用いて前記湿潤層をめっきすることによって実現される方法。 - 請求項1に記載の方法であって、実質的に金を含まない湿潤層を無電解めっきする工程は、ボランを含む無電解めっき浴を用いて実現される方法。
- 請求項1に記載の方法であって、前記基板を準備する工程は、1または複数の電気接点パッドを備える基板を準備する工程を含み、少なくとも前記基板の一部の上に前記バリア金属を無電解めっきする工程は、前記1または複数の電気接点パッド上に前記バリア金属をめっきする工程を含む方法。
- 請求項1に記載の方法であって、前記基板を準備する工程は、1または複数の基板貫通ビア導電体を備える基板を準備する工程を含み、少なくとも前記基板の一部の上に前記バリア金属を無電解めっきする工程は、前記1または複数の基板貫通ビア導電体上に前記バリア金属をめっきする工程を含む方法。
- 請求項1に記載の方法であって、前記基板を準備する工程は、1または複数のビアを有する基板を準備する工程を含み、少なくとも前記基板の一部の上に前記バリア金属を無電解めっきする工程は、前記1または複数のビアの壁の上に前記バリア金属をめっきする工程を含む方法。
- 請求項1に記載の方法であって、少なくとも前記基板の一部の上に前記バリア金属を無電解めっきする工程は、コバルトを含むバリア金属をめっきする工程を含む方法。
- 請求項1に記載の方法であって、少なくとも前記基板の一部の上に前記バリア金属を無電解めっきする工程は、0.2マイクロメートルから1マイクロメートルの範囲、ならびに前記範囲に含まれるすべての値および範囲の厚さで前記バリア金属をめっきする工程を含む方法。
- 請求項1に記載の方法であって、実質的に金を含まない湿潤層を無電解めっきする工程は、錫を無電解めっきする工程を含む方法。
- 請求項1に記載の方法であって、実質的に金を含まない湿潤層を無電解めっきする工程は、銀または銀合金を無電解めっきする工程を含む方法。
- 請求項1に記載の方法であって、実質的に金を含まない湿潤層を無電解めっきする工程は、3〜4原子百分率のタングステンを含む銀−タングステン合金を無電解めっきする工程を含む方法。
- 請求項1に記載の方法であって、実質的に金を含まない湿潤層を無電解めっきする工程は、コバルト−錫合金、コバルト−銅合金、コバルト−銀合金、コバルト−銅−錫合金、コバルト−銅−銀合金、コバルト−銀−錫合金、または、コバルト−銅−銀−錫合金を無電解めっきする工程を含む方法。
- 請求項11に記載の方法であって、さらに、前記実質的に金を含まない湿潤層にホウ素および/またはリンを組み込む工程を備える方法。
- 請求項1に記載の方法であって、実質的に金を含まない湿潤層を無電解めっきする工程は、ニッケル−銅合金、ニッケル−銀合金、ニッケル−銅−銀合金、ニッケル−銅−錫合金、ニッケル−銀−錫合金、または、ニッケル−銅−銀−錫合金を無電解めっきする工程を含む方法。
- 請求項13に記載の方法であって、さらに、前記実質的に金を含まない湿潤層にホウ素および/またはリンを組み込む工程を備える方法。
- 請求項1に記載の方法であって、実質的に金を含まない湿潤層を無電解めっきする工程は、鉄−錫合金、鉄−銅合金、鉄−銀合金、鉄−銅−錫合金、鉄−銅−銀合金、鉄−銀−錫合金、または、鉄−銅−銀−錫合金を無電解めっきする工程を含む方法。
- 請求項15に記載の方法であって、さらに、前記実質的に金を含まない湿潤層にホウ素および/またはリンを組み込む工程を備える方法。
- 請求項1に記載の方法であって、実質的に金を含まない湿潤層を無電解めっきする工程は、第1の組成を有する所定厚さのニッケル合金および第2の組成を有する所定厚さのニッケル合金を無電解めっきする工程を含む方法。
- 請求項1に記載の方法であって、実質的に金を含まない湿潤層を無電解めっきする工程は、第1の組成を有する所定厚さのコバルト−錫合金および第2の組成を有する所定厚さのコバルト−錫合金を無電解めっきする工程を含む方法。
- 電子デバイスを製造する方法であって、
1または複数の電気接点パッドならびに/もしくは1または複数の基板貫通ビア導電体を含む基板を準備する工程と、
ニッケル元素およびコバルト元素の少なくとも一方を含むバリア金属を、前記1または複数の電気接点パッドならびに/もしくは前記1または複数の基板貫通ビア導電体の少なくとも一部の上に、0.2マイクロメートルから1マイクロメートルの範囲、ならびに前記範囲に含まれるすべての値および範囲の厚さで無電解めっきする工程と、
1.錫または錫合金;
2.3〜4原子百分率のタングステンを含む銀−タングステン合金;
3.コバルト−錫合金、コバルト−銅合金、コバルト−銀合金、コバルト−銅−錫合金、コバルト−銅−銀合金、コバルト−銀−錫合金、または、コバルト−銅−銀−錫合金;
4.ニッケル−銅合金、ニッケル−銀合金、ニッケル−銅−銀合金、ニッケル−銅−錫合金、ニッケル−銀−錫合金、または、ニッケル−銅−銀−錫合金;
5.鉄−錫合金、鉄−銅合金、鉄−銀合金、鉄−銅−錫合金、鉄−銅−銀合金、鉄−銀−錫合金、または、鉄−銅−銀−錫合金;
6.第1の組成を有する所定厚さのニッケル合金および第2の組成を有する所定厚さのニッケル合金;
7.第1の組成を有する所定厚さのコバルト合金および第2の組成を有する所定厚さのコバルト合金;ならびに
8.第1の組成を有する所定厚さの鉄合金および第2の組成を有する所定厚さの鉄合金
の内の少なくとも1つを無電解めっきして、前記バリア金属と接触し、はんだぬれ性を有する実質的に金を含まない湿潤層を形成する工程と、
前記実質的に金を含まない湿潤層へのはんだ接点を形成する工程と
を備え、
前記1.〜8.の内の少なくとも1つを無電解めっきして、前記バリア金属と接触し、はんだぬれ性を有する実質的に金を含まない湿潤層を形成する工程、および前記実質的に金を含まない湿潤層へのはんだ接点を形成する工程は、所定温度範囲で無電解めっき浴組成を用いて前記バリア金属をめっきし、別の温度範囲で前記無電解めっき浴組成を用いて前記湿潤層をめっきすることによって実現される方法。
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US9519501B1 (en) | 2012-09-30 | 2016-12-13 | F5 Networks, Inc. | Hardware assisted flow acceleration and L2 SMAC management in a heterogeneous distributed multi-tenant virtualized clustered system |
US10375155B1 (en) | 2013-02-19 | 2019-08-06 | F5 Networks, Inc. | System and method for achieving hardware acceleration for asymmetric flow connections |
US9554418B1 (en) | 2013-02-28 | 2017-01-24 | F5 Networks, Inc. | Device for topology hiding of a visited network |
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JP6527030B2 (ja) | 2015-06-19 | 2019-06-05 | 東京エレクトロン株式会社 | めっき処理方法及びめっき処理部品並びにめっき処理システム |
EP3400762A4 (en) * | 2016-01-08 | 2019-08-14 | Lilotree, L.L.C. | PCB SURFACE COATING, METHOD OF USE AND ARRANGEMENTS OBTAINED THEREFROM |
US10412198B1 (en) | 2016-10-27 | 2019-09-10 | F5 Networks, Inc. | Methods for improved transmission control protocol (TCP) performance visibility and devices thereof |
US11223689B1 (en) | 2018-01-05 | 2022-01-11 | F5 Networks, Inc. | Methods for multipath transmission control protocol (MPTCP) based session migration and devices thereof |
US12003422B1 (en) | 2018-09-28 | 2024-06-04 | F5, Inc. | Methods for switching network packets based on packet data and devices |
TW202039026A (zh) | 2019-03-08 | 2020-11-01 | 美商美威高能離子醫療系統公司 | 藉由管柱之輻射遞送及自其產生治療計劃 |
JP6771613B2 (ja) * | 2019-05-09 | 2020-10-21 | 東京エレクトロン株式会社 | めっき処理方法及びめっき処理部品並びにめっき処理システム |
JP2021101451A (ja) * | 2019-12-24 | 2021-07-08 | 株式会社荏原製作所 | 基板処理装置 |
CN112708854A (zh) * | 2020-12-19 | 2021-04-27 | 合肥开泰机电科技有限公司 | 一种用于大面积钎焊的真空镀膜结构 |
US20220336400A1 (en) * | 2021-04-15 | 2022-10-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Connecting structure, package structure and manufacturing method thereof |
Family Cites Families (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04218919A (ja) * | 1990-04-17 | 1992-08-10 | Seiko Epson Corp | 電極及びその製造方法 |
US5736456A (en) | 1996-03-07 | 1998-04-07 | Micron Technology, Inc. | Method of forming conductive bumps on die for flip chip applications |
US5937320A (en) * | 1998-04-08 | 1999-08-10 | International Business Machines Corporation | Barrier layers for electroplated SnPb eutectic solder joints |
JP3968554B2 (ja) * | 2000-05-01 | 2007-08-29 | セイコーエプソン株式会社 | バンプの形成方法及び半導体装置の製造方法 |
JP4656275B2 (ja) * | 2001-01-15 | 2011-03-23 | 日本電気株式会社 | 半導体装置の製造方法 |
US6489229B1 (en) | 2001-09-07 | 2002-12-03 | Motorola, Inc. | Method of forming a semiconductor device having conductive bumps without using gold |
US7138293B2 (en) * | 2002-10-04 | 2006-11-21 | Dalsa Semiconductor Inc. | Wafer level packaging technique for microdevices |
US7276801B2 (en) * | 2003-09-22 | 2007-10-02 | Intel Corporation | Designs and methods for conductive bumps |
US7095116B1 (en) | 2003-12-01 | 2006-08-22 | National Semiconductor Corporation | Aluminum-free under bump metallization structure |
US6943106B1 (en) | 2004-02-20 | 2005-09-13 | Micron Technology, Inc. | Methods of fabricating interconnects for semiconductor components including plating solder-wetting material and solder filling |
US7325716B2 (en) * | 2004-08-24 | 2008-02-05 | Intel Corporation | Dense intermetallic compound layer |
JP2006086453A (ja) * | 2004-09-17 | 2006-03-30 | Yamato Denki Kogyo Kk | 表面処理方法、および電子部品の製造方法 |
JP4822694B2 (ja) * | 2004-11-22 | 2011-11-24 | 京セラ株式会社 | 半導体素子及び半導体素子実装基板 |
US7432202B2 (en) * | 2005-12-28 | 2008-10-07 | Intel Corporation | Method of substrate manufacture that decreases the package resistance |
US7682961B2 (en) | 2006-06-08 | 2010-03-23 | International Business Machines Corporation | Methods of forming solder connections and structure thereof |
KR100790527B1 (ko) * | 2006-07-27 | 2008-01-02 | 주식회사 네패스 | 웨이퍼레벨 패키지 및 그 제조 방법 |
US7727876B2 (en) | 2006-12-21 | 2010-06-01 | Stats Chippac, Ltd. | Semiconductor device and method of protecting passivation layer in a solder bump process |
US8314500B2 (en) | 2006-12-28 | 2012-11-20 | Ultratech, Inc. | Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers |
US7863189B2 (en) * | 2007-01-05 | 2011-01-04 | International Business Machines Corporation | Methods for fabricating silicon carriers with conductive through-vias with low stress and low defect density |
JP2008248269A (ja) * | 2007-03-29 | 2008-10-16 | Hitachi Chem Co Ltd | 銅表面の処理方法およびこの方法を用いた配線基板 |
US20090057909A1 (en) | 2007-06-20 | 2009-03-05 | Flipchip International, Llc | Under bump metallization structure having a seed layer for electroless nickel deposition |
TWI351729B (en) | 2007-07-03 | 2011-11-01 | Siliconware Precision Industries Co Ltd | Semiconductor device and method for fabricating th |
US7691747B2 (en) | 2007-11-29 | 2010-04-06 | STATS ChipPAC, Ltd | Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures |
US8022543B2 (en) * | 2008-03-25 | 2011-09-20 | International Business Machines Corporation | Underbump metallurgy for enhanced electromigration resistance |
US8288872B2 (en) | 2008-08-05 | 2012-10-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through silicon via layout |
US8932906B2 (en) | 2008-08-19 | 2015-01-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Through silicon via bonding structure |
US8518815B2 (en) | 2010-07-07 | 2013-08-27 | Lam Research Corporation | Methods, devices, and materials for metallization |
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US20120007239A1 (en) | 2012-01-12 |
US20140054776A1 (en) | 2014-02-27 |
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US9006893B2 (en) | 2015-04-14 |
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US8518815B2 (en) | 2013-08-27 |
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