CN105374701A - 电镀工艺中的活化处理 - Google Patents

电镀工艺中的活化处理 Download PDF

Info

Publication number
CN105374701A
CN105374701A CN201510859451.5A CN201510859451A CN105374701A CN 105374701 A CN105374701 A CN 105374701A CN 201510859451 A CN201510859451 A CN 201510859451A CN 105374701 A CN105374701 A CN 105374701A
Authority
CN
China
Prior art keywords
activation processing
processing solution
hardware
carry out
electroplating technology
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510859451.5A
Other languages
English (en)
Inventor
林志伟
郑明达
何明哲
刘重希
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN105374701A publication Critical patent/CN105374701A/zh
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
    • H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
    • H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/038—Post-treatment of the bonding area
    • H01L2224/0383—Reworking, e.g. shaping
    • H01L2224/03831—Reworking, e.g. shaping involving a chemical process, e.g. etching the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05181—Tantalum [Ta] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05639—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05647—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1141—Manufacturing methods by blanket deposition of the material of the bump connector in liquid form
    • H01L2224/11424—Immersion coating, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/116—Manufacturing methods by patterning a pre-deposited material
    • H01L2224/1162—Manufacturing methods by patterning a pre-deposited material using masks
    • H01L2224/11622—Photolithography
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1181—Cleaning, e.g. oxide removal step, desmearing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/119—Methods of manufacturing bump connectors involving a specific sequence of method steps
    • H01L2224/11901—Methods of manufacturing bump connectors involving a specific sequence of method steps with repetition of the same manufacturing step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13083—Three-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/13118—Zinc [Zn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01032—Germanium [Ge]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01072—Hafnium [Hf]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01073—Tantalum [Ta]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01327—Intermediate phases, i.e. intermetallics compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Metallurgy (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electroplating Methods And Accessories (AREA)
  • Chemically Coating (AREA)

Abstract

本发明提供一种形成装置的方法，包括进行第一电镀工艺以形成第一金属元件，以及在活化处理溶液中对第一金属元件的表面进行活化处理，其中活化处理溶液包括在去离子(DI)水中的处理剂。在进行活化处理步骤后，进行第二电镀工艺以形成第二金属元件并与第一金属元件的表面接触。本发明通过实施例显示在各层间的界面显著的改善，且观察到空隙显著的减少。再者，界面变得更加平滑。因此，相较于在电镀工艺间通过快速冲洗(QDR)而形成的金属凸块的传统方法中，本发明所得金属凸块的电子迁移(electro-migration,EM)性能提升，因此提升其可靠度。

Description

电镀工艺中的活化处理
本申请是申请日为2010年11月4日，申请号为201010537792.8，优先权日为2010年5月20日，发明名称为“电镀工艺中的活化处理”的发明专利申请的分案申请。
技术领域
本发明涉及一种集成电路，特别是涉及一种电镀工艺，更涉及以电镀工艺形成凸块的工艺。
背景技术
在形成半导体芯片时，首先在半导体芯片中的半导体基板表面形成集成电路装置如晶体管。而后在集成电路装置上形成内连线结构。在半导体芯片表面形成凸块以作为集成电路装置的接点。
在形成凸块的特定工艺中，先形成凸块底层金属(under-bumpmetallurgy,UBM)，而后在凸块底层金属上形成凸块。凸块底层金属的形成可包括形成铜晶种层(copperseedlayer)，以及在铜晶种层上形成一图案化掩模，而由掩模的开口暴露出部分铜晶种层。而后在暴露出来的部分铜晶种层上进行电镀步骤以电镀上厚铜层。接着，可依序电镀上额外层如镍层及焊料层。传统上在各电镀步骤间会以去离子水进行快速冲洗(quickdumprinse,QPR)，以清洗电镀层的表面。
经发现电镀层间的界面粗糙，且其中有空隙形成，使得凸块的电迁移(electro-migration,EM)性能下降，因而造成其可靠度下降。
发明内容
为克服现有技术的缺陷，根据本发明的形成装置的方法，包括进行第一电镀工艺以形成第一金属元件，以及在活化处理溶液中对第一金属元件的表面进行活化处理，其中活化处理溶液包括在去离子(de-ionized,DI)水中的处理剂。在进行活化处理步骤后，进行第二电镀工艺以形成第二金属元件且与第一金属元件的表面接触。
本发明也公开其他实施例。
本发明通过实施例显示在各层间的界面显著的改善，且观察到空隙显著的减少。再者，界面变得更加平滑。因此，相较于在电镀工艺间通过快速冲洗(QDR)而形成的金属凸块的传统方法中，本发明所得金属凸块的电子迁移(electro-migration,EM)性能提升，因此提升其可靠度。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出较佳实施例，并配合附图，作详细说明如下。
附图说明
图1～图7为一系列剖面图，用以说明根据一实施例制造金属凸块的中间阶段。
图8显示在晶片上进行活化处理工艺。
【主要附图标记说明】
2～晶片
10～基板
14～半导体装置
12～内连线结构
28～金属焊盘
30～保护层
40～扩散阻挡层
42～晶种层
46～掩模
45～开口
50～第一金属层
52～活化处理溶液
54～第二金属层
60～第三金属层
具体实施方式
本发明的实施例的制造与使用详述如下。应可理解的是，该些实施例所提供的许多发明概念可广泛的应用于各种特定范畴。所述特定实施例仅为举例说明而非以此为限。
在一实施例中，提供一种形成集成电路的新颖工艺。制造该实施例的中间阶段如图所示。本发明中讨论了不同的实施例。在不同的图示及实施例中，将使用类似的元件符号来表示类似的元件。
参照图1，提供包括基板10的晶片2。基板10可为半导体基板如硅块材基板，但也可包括其他半导体材料如锗硅、碳化硅、砷化镓等。可在基板10的表面形成半导体装置14如晶体管。在基板10上形成内连线结构12，该内连线结构包括在其中形成金属线及导孔(metallinesandvias)(未显示)，且金属线及导孔与半导体装置14接连。形成金属线及导孔的材料可为铜或铜合金，且可借熟知的镶嵌工艺(damasceneprocess)形成该金属线及导孔。内连线结构12可包括层间介电质(inter-layerdielectrics,ILDs)以及金属间介电质(inter-metaldielectrics,IMDs)。在另一实施例中，晶片2为中介晶片(interposerwafer)或封装基板，且晶片2中大体没有形成集成电路装置，如:晶体管、电阻器、电容、电感等。在这些实施例中，可以半导体材料或介电质材料如氧化硅来形成基板10。
在内连线结构12上形成金属焊盘28。金属焊盘28可包括铝、铜(Cu)、银(Ag)、金(Au)、镍(Ni)、钨(W)、前述的合金、以及/或前述的多层结构。金属焊盘28可与半导体装置14电性耦接，例如通过下方的内连线结构12。可形成保护层(passivationlayer)30以覆盖金属焊盘28的边缘部份。在一实施例中，形成保护层30的材料为聚酰亚胺(polyimide)或其他已知介电质材料如氧化硅、氮化硅及前述的多层结构。
参照图2，毯覆性形成凸块底层金属(under-bumpmetallurgy,UBM)，该凸块底层金属可包括扩散阻挡层40(此可为视需要形成)以及晶种层(seedlayer)42。扩散阻挡层40可为钛层、氮化钛层、钽层或氮化钽层。晶种层42的材料可包括铜或铜合金，因此之后将称之为铜晶种层42。然而，也可包括其他金属如银、金、铝、以及前述的组合。在一实施例中，以物理气相沉积或是其他可应用的方法形成扩散阻挡层40及铜晶种层42。
图3显示掩模46的形成，该掩模46例如可由光致抗蚀剂形成。于是，经由掩模46的开口45暴露出铜晶种层42。而后，如图4所示，将晶片2设置于电镀溶液(未显示)中，在凸块底层金属(UBM)40/42及开口45上进行电镀以形成第一金属元件50。电镀可为电子电镀(electro-plating)、化学电镀(electroless-plating)、浸镀(immersionplating)等。在一实施例中，第一金属层50为铜层或铜合金层。
参照图8所示，在形成第一金属层50后，进行活化处理。在一实施例中，如图8所示，活化处理溶液52包括去离子(DI)水以及溶解在其中的额外的添加剂。添加剂可包括可活化及清洗第一金属层50表面的处理剂，例如酸或其他化学物质。在一实施例中，在活化处理溶液52中的处理剂包括CX100，其可包括约30％的柠檬酸(C6H8O7)。该处理剂也可包括氢氟酸、草酸(oxalicacid)、硝酸、盐酸、氢氧化铵、硫酸等。处理剂的重量百分比范围可介于约1％至约40％。在活化处理中，处理溶液52的温度可介于约25℃至约50℃。在活化处理时清洗第一金属层50的表面，而移除在第一金属层50上的任何氧化物如氧化铜。
而后，如图5所示，在第一金属层50的表面形成第二金属层54，其中其形成方法可为电子电镀、化学电镀、浸镀等。在一实施例中，第二金属层54为镍层。接着，在第二活化处理溶液中，在第二金属层54的表面上进行第二活化处理，该活化处理溶液基本上与图8所示活化处理溶液52相同。相似地，第二活化处理的功能为活化及清洗第二金属层54的表面，并且移除形成在第二金属层54表面的氧化物。
图6显示在第二金属层54的表面上形成第三金属层60，其形成方法包括电子电镀、化学电镀或浸镀。第三金属层60可为焊料层，该焊料层可为共晶焊料或无铅焊料。在一实施例中，第三金属层60的焊料包括锌、银及铜，但也可使用其他元素。而后，在活化处理溶液中，在第三金属层60的表面上进行第三活化处理，该活化处理溶液基本上与图8所示的处理溶液52相同。
在形成第三金属层60后，移除掩模46，并且例如通过蚀刻来移除之前被掩模46覆盖的部分凸块底层金属(UBM)40/42。所得结构如图7所示。
应注意虽然实施例以在基板表面上形成金属凸块为例子，但本发明也可应用于通过电镀工艺形成其他金属元件。
本发明通过实施例显示在各层间的界面显著的改善，且观察到空隙显著的减少。再者，界面变得更加平滑。因此，相较于在电镀工艺间通过快速冲洗(QDR)而形成的金属凸块的传统方法中，本发明所得金属凸块的电子迁移(electro-migration,EM)性能提升，因此提升其可靠度。
虽然本发明已以多个较佳实施例公开如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。

Claims (7)

1.一种形成装置的方法，包括：
进行一第一电镀工艺以形成一第一金属元件；
将该第一金属元件浸入在一第一活化处理溶液中，以对该第一金属元件的一表面进行一第一活化处理，该第一活化处理溶液包括在去离子水中的一第一处理剂，且该第一活化处理溶液的温度介于25-50℃；
在进行该第一活化处理步骤后，进行一第二电镀工艺，以形成一第二金属元件，且与该第一金属元件的该表面接触；
在进行该第二电镀工艺的步骤后，将该第二金属元件浸入在一第二活化处理溶液中，对该第二金属元件的一表面进行一第二活化处理，该第二活化处理溶液与第一活化处理溶液相同；
在进行该第二活化处理步骤后，进行一第三电镀工艺，以形成一第三金属元件，且与该第二金属元件的该表面接触；以及
在进行该第三电镀工艺的步骤后，将该第三金属元件浸入在一第三活化处理溶液中，以对该第三金属元件的一表面进行一第三活化处理，该第三活化处理溶液与第一活化处理溶液相同；
其中该第一金属元件为一铜层，而该第二金属元件为一镍层，而该第三金属元件为一焊料层。
2.根据权利要求1所述的形成装置的方法，其中该第一处理剂包括酸。
3.根据权利要求2所述的形成装置的方法，其中该第一处理剂包括含柠檬酸的CX100。
4.根据权利要求1所述的形成装置的方法，其中该第一处理剂在该第一活化处理溶液中的重量百分比介于1％至40％。
5.一种形成装置的方法，包括：
提供一基板；
在该基板上形成一凸块底层金属；
在该凸块底层金属上形成一图案化掩模，经由该掩模的一开口暴露出一部分的该凸块底层金属；
进行一第一电镀工艺以在经由该开口暴露出来的部分的该凸块底层金属形成一铜层；
将该铜层浸入在一第一活化处理溶液中，以对该铜层的一表面进行一第一活化处理，该第一活化处理溶液包括在去离子水中的一处理剂，且该第一活化处理溶液的温度介于25-50℃；
在进行该第一活化处理的步骤后，进行一第二电镀工艺以在该铜层的表面上形成一镍层；
在进行该第二电镀工艺的步骤后，将该镍层浸入在一第二活化处理溶液中，以对该镍层的一表面进行一第二活化处理，该第二活化处理溶液与第一活化处理溶液相同；
在进行该第二活化处理步骤后，进行一第三电镀工艺以在该镍层表面形成一焊料层；
在进行该第三电镀工艺步骤后，将该焊料层浸入在一第三活化处理溶液中，以对该焊料层的一表面进行一第三活化处理，该第三活化处理溶液与第一活化处理溶液相同；以及
移除该掩模以及直接在该掩模下的部分该凸块底层金属。
6.根据权利要求5所述的形成装置的方法，其中该处理剂包括柠檬酸。
7.根据权利要求5所述的形成装置的方法，该处理剂在该第一活化处理溶液和该第二活化处理溶液中的重量百分比介于1％至40％。
CN201510859451.5A 2010-05-20 2010-11-04 电镀工艺中的活化处理 Pending CN105374701A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/784,314 2010-05-20
US12/784,314 US8703546B2 (en) 2010-05-20 2010-05-20 Activation treatments in plating processes
CN2010105377928A CN102254842A (zh) 2010-05-20 2010-11-04 电镀工艺中的活化处理

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN2010105377928A Division CN102254842A (zh) 2010-05-20 2010-11-04 电镀工艺中的活化处理

Publications (1)

Publication Number Publication Date
CN105374701A true CN105374701A (zh) 2016-03-02

Family

ID=44972832

Family Applications (2)

Application Number Title Priority Date Filing Date
CN2010105377928A Pending CN102254842A (zh) 2010-05-20 2010-11-04 电镀工艺中的活化处理
CN201510859451.5A Pending CN105374701A (zh) 2010-05-20 2010-11-04 电镀工艺中的活化处理

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN2010105377928A Pending CN102254842A (zh) 2010-05-20 2010-11-04 电镀工艺中的活化处理

Country Status (2)

Country Link
US (1) US8703546B2 (zh)
CN (2) CN102254842A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110528042A (zh) * 2019-08-28 2019-12-03 深圳赛意法微电子有限公司 一种半导体器件电镀方法及用于电镀的活化槽

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9040385B2 (en) * 2013-07-24 2015-05-26 Taiwan Semiconductor Manufacturing Co., Ltd. Mechanisms for cleaning substrate surface for hybrid bonding
US20150048499A1 (en) * 2013-08-16 2015-02-19 Macrotech Technology Inc. Fine-pitch pillar bump layout structure on chip
CN104846410A (zh) * 2015-06-16 2015-08-19 沈阳飞机工业（集团）有限公司 一种在黄铜、紫铜合金上电镀镍的方法
CN115775724A (zh) * 2021-09-08 2023-03-10 盛美半导体设备(上海)股份有限公司 基板处理方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1835212A (zh) * 2005-03-17 2006-09-20 日立电线株式会社 电子装置用基板及其制造方法以及电子装置及其制造方法
CN1841689A (zh) * 2005-03-28 2006-10-04 富士通株式会社 半导体器件及半导体器件制造方法
CN1848381A (zh) * 2005-04-15 2006-10-18 中芯国际集成电路制造(上海)有限公司 形成低应力多层金属化结构和无铅焊料端电极的方法
CN1918325A (zh) * 2004-01-26 2007-02-21 应用材料公司 用于在单个室中的无电沉积期间选择性改变薄膜成分的方法和装置
US20110062580A1 (en) * 2009-09-14 2011-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Protection layer for preventing ubm layer from chemical attack and oxidation

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3558441A (en) * 1968-11-01 1971-01-26 Int Electronic Res Corp Method of making a metal core printed circuit board
CH690144A5 (de) * 1995-12-22 2000-05-15 Alusuisse Lonza Services Ag Strukturierte Oberfläche mit spitzenförmigen Elementen.
US6396148B1 (en) * 2000-02-10 2002-05-28 Epic Technologies, Inc. Electroless metal connection structures and methods
US6492197B1 (en) * 2000-05-23 2002-12-10 Unitive Electronics Inc. Trilayer/bilayer solder bumps and fabrication methods therefor
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
US7772043B2 (en) * 2001-12-12 2010-08-10 Sanyo Electric Co., Ltd. Plating apparatus, plating method and manufacturing method for semiconductor device
KR100430001B1 (ko) * 2001-12-18 2004-05-03 엘지전자 주식회사 다층기판의 제조방법, 그 다층기판의 패드 형성방법 및 그다층기판을 이용한 반도체 패키지의 제조방법
US6740577B2 (en) * 2002-05-21 2004-05-25 St Assembly Test Services Pte Ltd Method of forming a small pitch torch bump for mounting high-performance flip-flop devices
US20040007779A1 (en) * 2002-07-15 2004-01-15 Diane Arbuthnot Wafer-level method for fine-pitch, high aspect ratio chip interconnect
US7198705B2 (en) * 2002-12-19 2007-04-03 Texas Instruments Incorporated Plating-rinse-plating process for fabricating copper interconnects
US7465358B2 (en) * 2003-10-15 2008-12-16 Applied Materials, Inc. Measurement techniques for controlling aspects of a electroless deposition process
US7205233B2 (en) * 2003-11-07 2007-04-17 Applied Materials, Inc. Method for forming CoWRe alloys by electroless deposition
US20050181226A1 (en) * 2004-01-26 2005-08-18 Applied Materials, Inc. Method and apparatus for selectively changing thin film composition during electroless deposition in a single chamber
JP5001542B2 (ja) * 2005-03-17 2012-08-15 日立電線株式会社 電子装置用基板およびその製造方法、ならびに電子装置の製造方法
TW200707640A (en) * 2005-03-18 2007-02-16 Applied Materials Inc Contact metallization scheme using a barrier layer over a silicide layer
JP4171499B2 (ja) * 2006-04-10 2008-10-22 日立電線株式会社 電子装置用基板およびその製造方法、並びに電子装置およびその製造方法
JP4431123B2 (ja) * 2006-05-22 2010-03-10 日立電線株式会社 電子装置用基板およびその製造方法、並びに電子装置およびその製造方法
US20080116077A1 (en) * 2006-11-21 2008-05-22 M/A-Com, Inc. System and method for solder bump plating

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1918325A (zh) * 2004-01-26 2007-02-21 应用材料公司 用于在单个室中的无电沉积期间选择性改变薄膜成分的方法和装置
CN1835212A (zh) * 2005-03-17 2006-09-20 日立电线株式会社 电子装置用基板及其制造方法以及电子装置及其制造方法
CN1841689A (zh) * 2005-03-28 2006-10-04 富士通株式会社 半导体器件及半导体器件制造方法
CN1848381A (zh) * 2005-04-15 2006-10-18 中芯国际集成电路制造(上海)有限公司 形成低应力多层金属化结构和无铅焊料端电极的方法
US20110062580A1 (en) * 2009-09-14 2011-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Protection layer for preventing ubm layer from chemical attack and oxidation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110528042A (zh) * 2019-08-28 2019-12-03 深圳赛意法微电子有限公司 一种半导体器件电镀方法及用于电镀的活化槽

Also Published As

Publication number Publication date
CN102254842A (zh) 2011-11-23
US8703546B2 (en) 2014-04-22
US20110287628A1 (en) 2011-11-24

Similar Documents

Publication Publication Date Title
JP6078585B2 (ja) 小型電子機器、その形成方法、およびシステム
US8901735B2 (en) Connector design for packaging integrated circuits
US6335104B1 (en) Method for preparing a conductive pad for electrical connection and conductive pad formed
US7294565B2 (en) Method of fabricating a wire bond pad with Ni/Au metallization
JP3737482B2 (ja) 自己不動態化Ｃｕ合金を用いて接着されたＣｕパッド／Ｃｕワイヤ
JP2010508673A (ja) 終端アルミニウム金属層のないメタライゼーション層積層体
US6362089B1 (en) Method for processing a semiconductor substrate having a copper surface disposed thereon and structure formed
CN105374701A (zh) 电镀工艺中的活化处理
US9627335B2 (en) Method for processing a semiconductor workpiece and semiconductor workpiece
CN100517610C (zh) 半导体元件的处理方法以及半导体元件的形成方法
WO2013188156A1 (en) Method for applying a final metal layer for wafer level packaging and associated device
TWI595332B (zh) 光阻剝離方法
KR20130121041A (ko) 고 종횡비 필을 위한 반도체 리플로우 프로세싱
US20210028060A1 (en) Contact fabrication to mitigate undercut
CN115188678B (zh) 一种微波集成电路导电互联的制造方法
US20230123307A1 (en) Electronic device having chemically coated bump bonds
US9331033B1 (en) Method for forming stacked metal contact in electrical communication with aluminum wiring in semiconductor wafer of integrated circuit
US20060270234A1 (en) Method and composition for preparing a semiconductor surface for deposition of a barrier material
US9142456B2 (en) Method for capping copper interconnect lines
CN105826206A (zh) 用于形成堆栈金属接点与半导体晶圆内铝线电连通的方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20160302