CN1848381A - 形成低应力多层金属化结构和无铅焊料端电极的方法 - Google Patents

形成低应力多层金属化结构和无铅焊料端电极的方法 Download PDF

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CN1848381A
CN1848381A CNA200510025198XA CN200510025198A CN1848381A CN 1848381 A CN1848381 A CN 1848381A CN A200510025198X A CNA200510025198X A CN A200510025198XA CN 200510025198 A CN200510025198 A CN 200510025198A CN 1848381 A CN1848381 A CN 1848381A
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layer
metal dish
pvd film
substrate
thickness
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CNA200510025198XA
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CN100428414C (zh
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王津洲
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Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
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Priority to CNB200510025198XA priority Critical patent/CN100428414C/zh
Priority to US11/176,871 priority patent/US7462556B2/en
Publication of CN1848381A publication Critical patent/CN1848381A/zh
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Publication of CN100428414C publication Critical patent/CN100428414C/zh
Priority to US12/273,238 priority patent/US7816787B2/en
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Abstract

本发明提供了一种用于制造焊盘结构的技术。方法包括提供衬底。在衬底上方形成金属盘和钝化层。钝化层包括一开口以暴露金属盘的一部分。至少在金属盘的暴露部分上方沉积第一膜。在第一膜上方沉积第二膜。在衬底上方沉积光刻胶层，并且在光刻胶层中金属盘的所述部分正上方形成沟槽。在沟槽中第二膜的上方电镀第一层，并且在沟槽中第一层的上方电镀阻挡层。在沟槽中阻挡层的上方电镀包括锡的端电极。去除光刻胶层。此外，本方法包括进行刻蚀，以去除位于预定区域之外的第二膜和第一膜。然后回流端电极。阻挡层通过避免锡从端电极到第一层的扩散，防止在第一层附近形成金属间化合物。在具体实施例中，第一层包括包括镍的阻挡层下方的应力释放铜。

Description

形成低应力多层金属化结构和无铅焊料端电极的方法
技术领域
本发明涉及集成电路及其用于半导体器件制造的工艺。更具体地，本发明提供用于制造用于先进集成电路器件的焊盘结构的方法和结构，然而应该认识到本发明具有更加广泛的可应用性。
背景技术
集成电路已经从制造在单个硅芯片上的少数的互连器件发展到数百万个器件。传统集成电路提供的性能和复杂度已远远超过了当初的想象。为了实现复杂度和电路密度(即，能够被安置到给定芯片面积上的器件的数量)的提高，对于每一代集成电路，最小器件线宽的尺寸(也被称为器件“几何”)变得越来越小。
不断增大的电路密度不仅已提高了集成电路的复杂度和性能，而且也为客户提供了更低成本的部件。集成电路或者芯片制造工厂可能花费成百上千万，甚至十几亿美元。每一制造工厂将具有一定的晶片生产量，而每片晶片上将会有一定数量的集成电路。因此，通过制造更小的集成电路个体器件，更多的器件可以被制造在每一个晶片上，这样就可以增加制造工厂的产量。要使器件更小是很有挑战性的，因为每一种用于集成制造的工艺都存在限制。那也就是说，一种给定的工艺通常只能加工到某一特定的线宽尺寸，于是不是工艺就是器件布局需要被改变。此外，随着器件要求越来越快速的设计，工艺限制就伴随某些传统的工艺和材料而存在。
这样的工艺的示例是集成电路器件的焊盘结构的制造。这样的焊盘传统上已经变得越来越小，并且占据硅基板面中的更小的区域。虽然已经有了明显的改进，但是焊盘结构的设计仍然具有许多限制。仅仅作为示例，这些设计必须变得越来越小，但是仍然要提供足够的机械(键合)强度。但是，传统的焊盘设计常常存在质量和可靠性问题，特别是具有无铅端电极(或者焊料凸点)的设计。在传统焊盘设计中铜和锡的通常的共存促进了不希望的诸如Cu3Sn之类的金属间化合物的形成。这些金属间化合物的出现可以产生空洞，由此降低焊接的完整性。在本说明书中，更具体地在下文中将更加详细地描述这些和其他的限制。
从上面看出，用于处理半导体器件的改进技术是所希望的。
发明内容
根据本发明，提供了涉及集成电路和其用于半导体器件制造的处理的技术。更具体地，本发明提供用于制造用于先进集成电路器件的焊盘结构的方法和结构。然而，应该认识到本发明具有更加广泛的可应用性。
在一个具体实施例中，本发明提供了一种用于制造焊盘结构的方法。提供一个衬底。接着，在所述衬底上方形成金属盘和钝化层。钝化层包括一个开口，以暴露所述金属盘的一部分。至少在所述金属盘的所述暴露部分上方沉积第一膜。在所述第一膜上方沉积第二膜。在所述结构表面上方沉积一光刻胶层，并且利用掩模，在所述光刻胶层中所述金属盘的暴露部分正上方形成一个沟槽。在所述沟槽中所述第二膜的上方电镀第一层，并且在所述沟槽中所述第一层的上方电镀(可以包括镍的)阻挡层。在所述沟槽中所述阻挡层的上方电镀一端电极，所述端电极包括锡。去除所述光刻胶层。此外，本方法包括进行刻蚀，以去除位于预定区域之外的第二膜和第一膜。然后回流所述端电极。所述阻挡层通过避免锡从所述端电极到所述第一层的扩散，防止在所述第一层附近形成金属间化合物。
在另一实施例中，本发明提供了一种集成电路器件。该集成电路器件包括：一个衬底；至少一个金属盘，形成在所述衬底上；以及一钝化层，具有围绕所述至少一个金属盘形成的开口。该器件还包括：多层凸点下金属化(UBM)结构(也称为球限制金属化(BLM)结构)，耦合到所述至少一个金属盘。所述UBM结构包括：一铬PVD薄膜；所述铬PVD薄膜上方的一铜PVD薄膜；所述铜PVD薄膜上方的一电镀铜层；以及电镀铜层上方的电镀镍层。一个包括锡的端电极被耦合到所述凸点下金属化结构。所述电镀镍层通过避免锡从所述端电极到所述铜层的扩散，防止在所述铜层附近形成金属间化合物。
在另一个实施例中，提供了一种用于制造焊盘结构的方法。所述方法包括提供一个衬底。在所述衬底上方形成至少一个金属盘和一钝化层。所述钝化层包括开口以暴露所述至少一个金属盘的一部分。至少在所述至少一个金属盘的所述暴露部分上方沉积一粘附层。接着，在所述粘附层上方沉积润湿传导层；并且在表面上方沉积一光刻胶层。利用掩模，在所述光刻胶层中所述金属盘的一部分的正上方形成沟槽。在具体的实施例中，所述沟槽的周界限定出与所述至少一个金属盘的边界相一致的区域。在所述沟槽中所述润湿传导层的上方电镀一铜层。在所述沟槽中所述铜层的上方电镀一阻挡层。此外，在所述沟槽中所述阻挡层的上方电镀一端电极，所述端电极包括锡。去除所述光刻胶层。通过刻蚀，去除位于所述区域外部的所述润湿传导层和所述粘附层。回流所述端电极。所述阻挡层通过避免锡从所述端电极到所述铜层的扩散，防止在所述铜层附近形成金属间化合物。
较传统技术，通过本发明获得了的很多优点。例如，本技术为使用依赖于传统技术的工艺提供了便利。在一些实施例中，本方法提供了一种焊盘结构。此外，本方法提供了与传统工艺技术兼容而不用对传统设备和工艺进行实质修改的工艺。依据实施例，可以获得这些优点中的一个或多个。这些优点或其他优点将在本说明书全文中并且更具体地在下文中，进行更多的描述。
参考后面的详细说明和附图，可以更全面地了解本发明的各种其他目的、特征和优点。
附图说明
图1示出了根据本发明一个实施例制造焊盘结构的方法；
图2A-2G是示出了根据本发明一个实施例在制造过程中焊盘结构的横截面视图的简化图；和
图3是示出了根据本发明一个实施例的焊盘结构的横截面视图的简化图。
具体实施方式
根据本发明，提供了涉及集成电路和其用于半导体器件制造的处理的技术。更具体地，本发明提供用于制造用于先进集成电路器件的焊盘结构的方法和结构。然而，应该认识到本发明具有更加广泛的可应用性。
图1示出了根据本发明一个实施例制造焊盘结构的简化方法。方法100包括下面的工艺：
1.工艺102，提供衬底。
2.工艺104，在衬底上方形成金属盘。
3.工艺106，在衬底上方形成钝化层。该钝化层具有开口，以暴露金属盘的一部分。
4.工艺107，采用交流溅射(radio frequency sputter)蚀刻以去除所述金属盘上的所自然形成的氧化层。
5.工艺108，至少在金属盘的暴露部分的上方沉积第一膜。在具体的实施例中，第一模是包括铬的PVD薄膜。
6.工艺110，至少在金属盘的所述部分的上方沉积第二膜。在具体的实施例中，第二膜是包括铜的PVD薄膜。
7.工艺112，在衬底上方沉积光刻胶层。
8.工艺114，利用光刻工艺，在光刻胶中金属层区域的所述部分的正上方形成(图案化)沟槽。
9.工艺115，采用等离子除渣蚀刻(plasma descum etch)以去除沟槽中的光刻胶残留。
10.工艺116，在沟槽中第二膜的上方电镀第一层。在具体实施例中，第一层包括铜。
11.工艺118，在沟槽中铜层的上方电镀阻挡层。在具体实施例中，阻挡层包括镍。
12.工艺120，在沟槽中阻挡层的上方电镀端电极。在具体实施例中，端电极包括锡。
13工艺122，去除光刻胶层。
14.工艺124，进行刻蚀，以去除沉积于预定区域之外的第二膜。
15.工艺126，进行刻蚀，以去除沉积于该区域外部的第一膜。在一些实施例中，工艺124和126可以被合并。
16.工艺128，回流端电极。
上述顺序的工艺提供了根据本发明一个实施例的方法。还可以提供许多其他可供选择的方法，其中在不背离这里的权利要求的范围的情况下，加入某些步骤，删去一个或多个步骤，或者一个或多个步骤按照不同的顺序被提供。例如，附加的工艺被提供来形成钝化层中的附加的金属层区域。在本说明书全文中，更具体地在下文中，可以找到本方法的更多的细节。
图2A-2G是示出了根据本发明一个实施例在制造过程中焊盘结构200的横截面视图的简化图。这些图仅仅是示例，不应限制这里的发明的范围。本领域的普通技术人员将认识到很多变化、替代和修改。如图2A所示，焊盘结构200包括衬底202。优选地，衬底202是硅晶片或者绝缘体上硅晶片等。衬底202通常在其上或者在其中包括电子器件(诸如MOS器件、电阻器、晶体管、二极管、电容器等)。
在此具体实施例中，钝化层206上覆于衬底202。在可选实施例中，一层或者多层中间层可以被沉积在钝化层206和衬底202之间，所述中间层例如是电介质层和/或掺氟硅酸盐玻璃层。钝化层206保证使表面化学不活泼，并且防止氧化。钝化层206自身可以包括一层(例如，氧氮化硅(SiOxNy)层)或者多层(例如，覆盖于氮化硅层或者氧氮化硅层下面的氧化硅层)。钝化层206具有围绕金属盘204的一部分形成的开口。金属盘204通常可以包括铝(Al)、铜(Cu)或者其他金属材料。而且，金属盘204优选是矩形的，但是也可以任一的任意形状(例如，多边形、圆形、椭圆形、正方形等)。
图2B示出了凸点下金属化(UBM，under bump metallurgy)结构的沉积。在此具体实施例中，UBM结构包括第一PVD薄膜208和第二PVD薄膜210，第一PVD薄膜208和第二PVD薄膜210可通过溅射沉积完成。在第一PVD薄膜208沉积之前，采用一个交流溅射工艺以去除金属盘204上的氧化层。第一PVD薄膜208(或者粘附层)将UBM结构粘附到金属盘204。第一PVD薄膜208厚约500埃到约1000埃的范围，并且可以包括铬。第二PVD薄膜210提供一个润湿和传导层。第二PVD薄膜210厚约2000埃到4000埃的范围，并且可以包括铜。所述第二PVD薄膜210的厚度为所述第一PVD薄膜208的厚度的至少约两倍。
光刻胶层212被沉积在衬底202上方。如图2C所示，沟槽214被形成在光刻胶层212中金属盘204的一部分的正上方。沟槽214可以通过使用掩模的光刻工艺来形成。应该注意，在可选实施例中，抗反射层(没有图示)可以被涂敷到光刻胶层212下方。抗反射层减小了表面反射率，以在光刻工艺过程中提高线宽的尺寸控制。
在图2D中，UBM结构的第三层216被形成在沟槽中第二PVD薄膜210的上方。并且，第四层218被形成在沟槽中第三层216的上方。第三层216和第四层218分别都可以用电镀工艺来形成。优选地，第三层216包括电镀铜而第四层218(或者阻挡层)包括电镀镍。在第四层218上方，形成端电极220。在一个实施例中，端电极220利用电镀工艺来形成。在具体实施例中，端电极220是包括锡的无铅焊料凸点。但是，在可选实施例中，端电极220可以是任何低共熔焊料或者任何高铅焊料，特别是包括锡的那些焊料。所述端电极220还可以包括银。布置在第三层216和端电极220之间的第四层218提供减小或者避免不希望的金属间化合物的形成的阻挡层。例如，如果端电极220包含锡的话，那么由电镀镍形成的第四层将减小或者避免在下面的由电镀铜形成的第三层的附近Cu3Sn的形成。与低共熔焊料或者高铅焊料相比，本发明的这一特别实施例中的无铅焊料通常含约96％到98％的锡，其优点将更加显著。低共熔焊料和高铅焊料通常可以分别包含约63％和约5％的锡。
第四层218的厚度大于第三层216的厚度。在一个实施例中，第三层216的厚度为从约0.2微米到约0.8微米的范围，而第四层218(阻挡层)的厚度为从约2微米到约6微米的范围。
去除光刻胶层212，如图2E所示。可以通过许多工艺，包括剥离工艺和灰化工艺，来完成去除。在本发明的具有下面的抗反射层的实施例中，还常常利用湿法刻蚀工艺，去除抗反射层。接着，如图2F所示，第二PVD薄膜210和第一PVD薄膜208的多余部分可以被去除。在具体实施例中，多余部分对应于由沟槽214的尺寸所限定的预定区域外部的区域。这样，UBM结构中的四层中的每一层被对齐并且具有围绕整个周长的一致的边缘。或者，第二PVD薄膜210和第一PVD薄膜208可以被刻蚀，但是仍然延伸到沟槽214的尺寸之外。
如图2G所示，端电极被回流，以提供端电极220和UBM结构之间的牢固接合。作为回流的结果，端电极220可以发生焊球成球。在高温下的回流工艺还释放了电镀铜和铜以及铬结构的PVD薄膜的应力。
图3是示出了根据本发明一个实施例的焊盘结构300的横截面视图的简化图。此图仅仅是示例，不应限制这里的发明的范围。本领域的普通技术人员将认识到很多变化、替代和修改。如图所示，集成电路器件可以包括衬底302和至少一个形成在衬底302上的金属盘303。钝化层304被布置在衬底302上方，钝化层304具有围绕至少一个金属盘303形成的一个开口。UBM结构耦合到至少一个金属盘303。凸点下金属化结构可以包括(i)铬PVD薄膜306；(ii)铬PVD薄膜306上方的铜PVD薄膜308；(iii)铜PVD薄膜308上方的铜电镀层310；以及(iv)电镀层310上方的镍电镀层312。包括锡的端电极314被耦合到UBM结构。电镀层312通过避免锡从端电极314到层310的扩散，防止在层310附近形成金属间化合物。
还应当理解，这里所描述的示例和实施例只是为了说明的目的，本领域的普通技术人员可以根据上述示例和实施例对本发明进行各种修改或变化，这些修改和变化将被包括在本申请的精神和范围内，并且也在所附权利要求的范围内。

Claims (27)

1.一种用于制造焊盘结构的方法，所述方法包括：
提供一个衬底；
在所述衬底上方形成一个金属盘；
在所述衬底上方形成一钝化层，所述钝化层具有一个开口以暴露所述金属盘的一部分；
采用交流溅射蚀刻以去除所述金属盘上的氧化层；
至少在所述金属盘的所述暴露部分上方沉积包括铬的一个第一PVD薄膜；
在所述第一PVD薄膜上方沉积包括铜的一个第二PVD薄膜；
在所述衬底上方沉积一光刻胶层；
利用掩模，在所述光刻胶层中至少所述金属盘的一部分上方形成一个沟槽；
采用等离子除渣蚀刻以去除沟槽中的光刻胶残留；
在所述沟槽中所述第二PVD薄膜的上方电镀包括铜的一个第一层；
在所述沟槽中所述第一层的上方电镀包括镍的阻挡层；
在所述沟槽中所述阻挡层的上方电镀一端电极，所述端电极包括锡；
去除所述光刻胶层；
进行刻蚀，以去除位于一个区域之外的所述第二PVD薄膜；
进行刻蚀，以去除位于所述区域之外的所述第一PVD薄膜；以及
回流所述端电极，
其中，所述阻挡层通过避免锡从所述端电极到所述第一层的扩散，防止在所述第一层附近形成金属间化合物。
2.根据权利要求1所述的方法，其中所述金属间化合物是无Cu3Sn的。
3.根据权利要求1所述的方法，其中所述端电极还包括银。
4.根据权利要求1所述的方法，其中所述衬底是半导体衬底、电介质层和掺氟硅酸盐玻璃层中的至少一种。
5.根据权利要求1所述的方法，其中通过溅射沉积完成所述第一PVD薄膜的沉积。
6.根据权利要求1所述的方法，其中通过溅射沉积完成所述第二PVD薄膜的沉积。
7.根据权利要求1所述的方法，其中所述第一PVD薄膜的厚度为从约500埃到约1000埃的范围。
8.根据权利要求1所述的方法，其中所述第二PVD薄膜的厚度为从约2000埃到约4000埃的范围。
9.根据权利要求1所述的方法，其中所述第二PVD薄膜的厚度为所述第一PVD薄膜的厚度的至少约两倍。
10.根据权利要求1所述的方法，其中所述第一层的厚度为从约0.2微米到约0.8微米的范围。
11.根据权利要求1所述的方法，其中所述阻挡层的厚度为从约2微米到约6微米的范围。
12.根据权利要求1所述的方法，其中所述阻挡层的厚度大于所述第一层的厚度。
13.根据权利要求1所述的方法，其中所述金属盘包括铝。
14.根据权利要求1所述的方法，其中所述钝化层包括氧氮化硅材料、氧化硅材料或者氮化硅材料中的至少一种。
15.一种用于制造焊盘结构的方法，所述方法包括：
提供一个衬底；
在所述衬底上方形成至少一个金属盘；
在所述衬底上方形成一钝化层，所述钝化层具有开口以暴露所述至少一个金属盘的一部分；
采用交流溅射蚀刻以去除所述金属盘上的氧化层；
至少在所述至少一个金属盘的所述暴露部分上方沉积一粘附层；
在所述粘附层上方沉积润湿传导层；
在所述衬底上方沉积一光刻胶层；
利用掩模，在所述光刻胶层中所述金属盘的所述暴露部分正上方形成沟槽，所述沟槽的周界限定出平行于所述至少一个金属盘的区域；
采用等离子除渣蚀刻以去除沟槽中的光刻胶残留；
在所述沟槽中所述润湿传导层的上方电镀一铜层；
在所述沟槽中所述铜层的上方电镀一阻挡层；
在所述沟槽中所述阻挡层的上方电镀一端电极，所述端电极包括锡；
去除所述光刻胶层；
进行刻蚀，以去除位于一个区域外部的所述润湿传导层；
进行刻蚀，以去除位于所述区域外部的所述粘附层；以及
回流所述端电极，
其中，所述阻挡层通过避免锡从所述端电极到所述铜层的扩散，防止在所述铜层附近形成金属间化合物。
16.一种集成电路器件，包括：
一个衬底；
至少一个金属盘，形成在所述衬底上；
一钝化层，具有围绕所述至少一个金属盘形成的一个开口；
多层凸点下金属化结构，耦合到所述至少一个金属盘，所述凸点下金属化结构包括：
一包括铬的第一PVD薄膜，
一包括铜的第二PVD薄膜，所述第二PVD薄膜覆盖所述第一PVD薄膜；
一包括铜的电镀第一层，所述电镀第一层覆盖所述第二PVD薄膜；和
一包括镍的电镀第二层，所述电镀第二层覆盖所述电镀第一层；和
一个端电极，耦合到所述凸点下金属化结构，所述端电极包括锡，
其中，所述电镀第二层通过避免锡从所述端电极到所述电镀第一层的扩散，防止在所述电镀第一层附近形成金属间化合物。
17.根据权利要求16所述的集成电路器件，其中所述金属间化合物是无Cu3Sn的。
18.根据权利要求16所述的集成电路器件，其中所述端电极还包括银。
19.根据权利要求16所述的集成电路器件，其中所述衬底是半导体衬底、电介质层和掺氟硅酸盐玻璃层中的至少一种。
20.根据权利要求16所述的集成电路器件，其中所述第一PVD薄膜的厚度为从约500埃到约1000埃的范围。
21.根据权利要求16所述的集成电路器件，其中所述第二PVD薄膜的厚度为从约2000埃到约4000埃的范围。
22.根据权利要求16所述的集成电路器件，其中所述第二PVD薄膜的厚度为所述第一PVD薄膜的厚度的至少约两倍。
23.根据权利要求16所述的集成电路器件，其中所述电镀第一层的厚度为从约0.2微米到约0.8微米的范围。
24.根据权利要求16所述的集成电路器件，其中所述电镀第二层的厚度为从约2微米到约6微米的范围。
25.根据权利要求16所述的集成电路器件，其中所述电镀第二层的厚度大于所述电镀第一层的厚度。
26.根据权利要求16所述的集成电路器件，其中所述金属盘包括铝。
27.根据权利要求16所述的集成电路器件，其中所述钝化层包括氧氮化硅材料、氧化硅材料或者氮化硅材料中的至少一种。
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