JP5846225B2 - 信号変調回路 - Google Patents
信号変調回路 Download PDFInfo
- Publication number
- JP5846225B2 JP5846225B2 JP2014009807A JP2014009807A JP5846225B2 JP 5846225 B2 JP5846225 B2 JP 5846225B2 JP 2014009807 A JP2014009807 A JP 2014009807A JP 2014009807 A JP2014009807 A JP 2014009807A JP 5846225 B2 JP5846225 B2 JP 5846225B2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- quantizer
- integrator
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/324—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement
- H03M3/346—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by suppressing active signals at predetermined times, e.g. muting, using non-overlapping clock phases
- H03M3/348—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by means or methods for compensating or preventing more than one type of error at a time, e.g. by synchronisation or using a ratiometric arrangement by suppressing active signals at predetermined times, e.g. muting, using non-overlapping clock phases using return-to-zero signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M3/358—Continuously compensating for, or preventing, undesired influence of physical parameters of non-linear distortion, e.g. instability
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M3/42—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in parallel loops
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Amplifiers (AREA)
Description
まず、本実施形態において前提となる回路構成について説明する。図1に、前提となる回路構成を示す。図1の信号変調回路は、入力信号をデルタシグマ変調するものであり、減算器20と、積分器22と、量子化器としてのDFF(遅延型フリップフロップ)24を備える。クロック信号源26からのクロック信号は遅延回路28で遅延されてDFF24のクロック端子に供給され、かつ、クロック信号はDFF24のリセット端子にも供給される。
図2に、図1の回路構成を基本に用いた本実施形態の信号変調回路を示す。信号変調回路は、減算器20と、積分器22と、位相反転回路23と、バイアス生成回路50,51と、DFF24,25と、クロック信号源26及び遅延回路28と、1価3値波形生成回路40と、ドライバ回路42と、パルス合成回路34を備える。
スイッチングFET42c1→スピーカ44→スイッチングFET42c4
と流れる(+ON状態)。
スイッチングFET42c3→スピーカ44→スイッチングFET42c2
と流れる(−ON状態)。
Claims (2)
- クロック信号に同期して入力信号をデルタシグマ変調して出力する信号変調回路であって、
入力信号と帰還信号との差分を算出する減算器と、
前記減算器からの出力を積分する積分器と、
前記積分器で積分された信号に対し、前記クロック信号に同期したタイミングでゼロレベルを挿入しつつ遅延して量子化する量子化器と、
前記量子化器からの信号に基づき負荷を駆動するための駆動信号を生成するドライバ回路と、
前記ドライバ回路からの前記駆動信号を前記入力信号に帰還させる帰還回路と、
を備えることを特徴とする信号変調回路。 - クロック信号に同期して入力信号をデルタシグマ変調して出力する信号変調回路であって、
入力信号と帰還信号との差分を算出する減算器と、
前記減算器からの出力を積分する積分器と、
前記積分器で積分された信号の位相を反転する位相反転回路と、
前記積分器で積分された信号に対し、前記クロック信号に同期したタイミングでゼロレベルを挿入しつつ遅延して量子化する第1量子化器と、
位相反転器で位相反転された信号に対し、前記クロック信号に同期したタイミングでゼロレベルを挿入しつつ遅延して量子化する第2量子化器と、
前記第1量子化器からの信号と、前記第2量子化器からの信号を用いて、単電源に接続された負荷を正電流オン、負電流オン、及びオフの3値の通電状態で選択的に駆動するための3値信号を生成する3値信号生成回路と、
前記3値信号生成回路からの信号に基づき負荷を駆動するための駆動信号を生成するドライバ回路と、
前記ドライバ回路からの前記駆動信号を前記入力信号に帰還させる帰還回路と、
を備えることを特徴とする信号変調回路。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014009807A JP5846225B2 (ja) | 2014-01-22 | 2014-01-22 | 信号変調回路 |
EP15150016.2A EP2899889A1 (en) | 2014-01-22 | 2015-01-02 | Signal modulation circuit |
US14/594,329 US9590654B2 (en) | 2014-01-22 | 2015-01-12 | Signal modulation circuit |
CN201510032815.2A CN104796153B (zh) | 2014-01-22 | 2015-01-22 | 信号调制电路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014009807A JP5846225B2 (ja) | 2014-01-22 | 2014-01-22 | 信号変調回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015139105A JP2015139105A (ja) | 2015-07-30 |
JP5846225B2 true JP5846225B2 (ja) | 2016-01-20 |
Family
ID=52134095
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014009807A Expired - Fee Related JP5846225B2 (ja) | 2014-01-22 | 2014-01-22 | 信号変調回路 |
Country Status (4)
Country | Link |
---|---|
US (1) | US9590654B2 (ja) |
EP (1) | EP2899889A1 (ja) |
JP (1) | JP5846225B2 (ja) |
CN (1) | CN104796153B (ja) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6643709B2 (ja) * | 2016-01-12 | 2020-02-12 | オンキヨー株式会社 | 信号変調回路 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4972436A (en) * | 1988-10-14 | 1990-11-20 | Hayes Microcomputer Products, Inc. | High performance sigma delta based analog modem front end |
DE69120924T2 (de) * | 1991-01-15 | 1997-01-30 | Ibm | Sigma-Delta Wandler |
US5974089A (en) * | 1997-07-22 | 1999-10-26 | Tripath Technology, Inc. | Method and apparatus for performance improvement by qualifying pulses in an oversampled noise-shaping signal processor |
JP3369503B2 (ja) * | 1998-03-10 | 2003-01-20 | シャープ株式会社 | ディジタルスイッチングアンプ |
DE60015894T2 (de) * | 1999-04-21 | 2005-12-22 | Koninklijke Philips Electronics N.V. | Sigma-Delta-Analog-Digital-Wandler |
JP2002064383A (ja) * | 2000-08-18 | 2002-02-28 | Yamaha Corp | Δς変調器 |
US6664908B2 (en) * | 2001-09-21 | 2003-12-16 | Honeywell International Inc. | Synchronized pulse width modulator |
JP2004032501A (ja) * | 2002-06-27 | 2004-01-29 | Pioneer Electronic Corp | デジタル信号変換装置及び方法 |
US6998910B2 (en) * | 2004-01-22 | 2006-02-14 | Texas Instruments Incorporated | Amplifier using delta-sigma modulation |
US20060044057A1 (en) * | 2004-08-26 | 2006-03-02 | Rahmi Hezar | Class-D amplifier having high order loop filtering |
US7173483B2 (en) * | 2005-03-04 | 2007-02-06 | Aimtron Technology Corp. | Low-distortion tri-state switching amplifier |
JP2007312258A (ja) * | 2006-05-22 | 2007-11-29 | Sharp Corp | パルス信号生成装置 |
US7605653B2 (en) * | 2006-08-16 | 2009-10-20 | Intrinsix Corporation | Sigma-delta based class D audio power amplifier with high power efficiency |
JP4818900B2 (ja) * | 2006-12-25 | 2011-11-16 | シャープ株式会社 | ディジタルアンプおよびスイッチング回数制御方法 |
JP4805177B2 (ja) | 2007-01-31 | 2011-11-02 | シャープ株式会社 | ディジタルアンプ、および、ディジタルアンプの制御方法 |
US8106809B2 (en) | 2009-05-12 | 2012-01-31 | Qualcomm Incorporated | Sigma-delta converters and methods for analog-to-digital conversion |
US8736473B2 (en) * | 2010-08-16 | 2014-05-27 | Nxp, B.V. | Low power high dynamic range sigma-delta modulator |
JP5836020B2 (ja) * | 2011-09-02 | 2015-12-24 | スパンション エルエルシー | A/d変換器 |
-
2014
- 2014-01-22 JP JP2014009807A patent/JP5846225B2/ja not_active Expired - Fee Related
-
2015
- 2015-01-02 EP EP15150016.2A patent/EP2899889A1/en not_active Withdrawn
- 2015-01-12 US US14/594,329 patent/US9590654B2/en active Active
- 2015-01-22 CN CN201510032815.2A patent/CN104796153B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2015139105A (ja) | 2015-07-30 |
CN104796153B (zh) | 2020-01-10 |
CN104796153A (zh) | 2015-07-22 |
US20150207519A1 (en) | 2015-07-23 |
EP2899889A1 (en) | 2015-07-29 |
US9590654B2 (en) | 2017-03-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5786976B2 (ja) | 信号変調回路 | |
US7853029B2 (en) | Output stage for a hearing aid and method of driving output stage | |
JP5846225B2 (ja) | 信号変調回路 | |
JP6643709B2 (ja) | 信号変調回路 | |
US10250205B2 (en) | Power amplifying device | |
JP5219722B2 (ja) | 変調方法、変調器およびa/d変換器 | |
JP5846194B2 (ja) | 信号変調回路 | |
JP6268760B2 (ja) | 信号変調回路 | |
US9287867B2 (en) | Pulse synthesizing circuit | |
JP4481212B2 (ja) | デジタルスイッチングアンプ | |
JP6417903B2 (ja) | 信号変調回路 | |
JP2010063047A (ja) | D級増幅器 | |
JP2016134713A (ja) | 信号変調回路 | |
JP2006238293A (ja) | D級増幅器 | |
JP6398665B2 (ja) | 信号変調回路 | |
JP6609904B2 (ja) | デジタルアンプ | |
JP6197824B2 (ja) | 信号変調回路 | |
JP5451317B2 (ja) | 連続時間型多ビットδσadc回路 | |
JPWO2020175581A1 (ja) | デルタシグマ変調装置及び通信機器 | |
JP2016058974A (ja) | バイアス回路、オペアンプおよびδς型adコンバータ | |
JP2004172735A (ja) | スイッチング増幅器 | |
JP2006303964A (ja) | 増幅装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20151021 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20151027 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20151109 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5846225 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
S533 | Written request for registration of change of name |
Free format text: JAPANESE INTERMEDIATE CODE: R313533 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |