JP5819138B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP5819138B2
JP5819138B2 JP2011181492A JP2011181492A JP5819138B2 JP 5819138 B2 JP5819138 B2 JP 5819138B2 JP 2011181492 A JP2011181492 A JP 2011181492A JP 2011181492 A JP2011181492 A JP 2011181492A JP 5819138 B2 JP5819138 B2 JP 5819138B2
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JP
Japan
Prior art keywords
electrode
thin film
gate
drain electrode
gate electrode
Prior art date
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Expired - Fee Related
Application number
JP2011181492A
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English (en)
Japanese (ja)
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JP2013045835A5 (https=
JP2013045835A (ja
Inventor
哲史 河村
哲史 河村
内山　博幸
博幸 内山
裕紀 若菜
裕紀 若菜
太亮 尾崎
太亮 尾崎
孝徳 山添
孝徳 山添
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Hitachi Ltd
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Hitachi Ltd
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Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP2011181492A priority Critical patent/JP5819138B2/ja
Priority to PCT/JP2012/068167 priority patent/WO2013027512A1/ja
Publication of JP2013045835A publication Critical patent/JP2013045835A/ja
Publication of JP2013045835A5 publication Critical patent/JP2013045835A5/ja
Application granted granted Critical
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Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/471—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different architectures, e.g. having both top-gate and bottom-gate TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices

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  • Thin Film Transistor (AREA)
  • Electroluminescent Light Sources (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Dram (AREA)
JP2011181492A 2011-08-23 2011-08-23 半導体装置 Expired - Fee Related JP5819138B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011181492A JP5819138B2 (ja) 2011-08-23 2011-08-23 半導体装置
PCT/JP2012/068167 WO2013027512A1 (ja) 2011-08-23 2012-07-18 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011181492A JP5819138B2 (ja) 2011-08-23 2011-08-23 半導体装置

Publications (3)

Publication Number Publication Date
JP2013045835A JP2013045835A (ja) 2013-03-04
JP2013045835A5 JP2013045835A5 (https=) 2014-04-03
JP5819138B2 true JP5819138B2 (ja) 2015-11-18

Family

ID=47746263

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011181492A Expired - Fee Related JP5819138B2 (ja) 2011-08-23 2011-08-23 半導体装置

Country Status (2)

Country Link
JP (1) JP5819138B2 (https=)
WO (1) WO2013027512A1 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103943632B (zh) * 2013-12-31 2017-03-08 上海天马微电子有限公司 一种阵列基板及其制备方法、液晶显示器
KR102522888B1 (ko) 2017-11-02 2023-04-19 도레이 카부시키가이샤 집적 회로 및 그의 제조 방법 그리고 그것을 사용한 무선 통신 장치
KR102567380B1 (ko) * 2018-11-30 2023-08-16 엘지디스플레이 주식회사 트랜지스터, 패널 및 트랜지스터의 제조방법
KR102727524B1 (ko) * 2018-12-04 2024-11-08 엘지디스플레이 주식회사 트랜지스터, 패널 및 트랜지스터 제조방법
CN110717692B (zh) * 2019-10-23 2021-12-03 上海浦源科技有限公司 一种社会工业发展不均衡的饱和电力计算方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63301565A (ja) * 1987-05-30 1988-12-08 Matsushita Electric Ind Co Ltd 薄膜集積回路
JPH0494165A (ja) * 1990-08-09 1992-03-26 Fujitsu Ltd 半導体集積回路装置およびその製造方法
EP2515337B1 (en) * 2008-12-24 2016-02-24 Semiconductor Energy Laboratory Co., Ltd. Driver circuit and semiconductor device
KR101840622B1 (ko) * 2009-12-21 2018-05-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 박막 트랜지스터와 그 제작 방법

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Publication number Publication date
JP2013045835A (ja) 2013-03-04
WO2013027512A1 (ja) 2013-02-28

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