JP5778557B2 - 半導体装置の製造方法、半導体装置、及び半導体素子 - Google Patents

半導体装置の製造方法、半導体装置、及び半導体素子 Download PDF

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Publication number
JP5778557B2
JP5778557B2 JP2011259423A JP2011259423A JP5778557B2 JP 5778557 B2 JP5778557 B2 JP 5778557B2 JP 2011259423 A JP2011259423 A JP 2011259423A JP 2011259423 A JP2011259423 A JP 2011259423A JP 5778557 B2 JP5778557 B2 JP 5778557B2
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electrode
semiconductor element
pad
pads
center
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JP2013115205A5 (enExample
JP2013115205A (ja
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洋弘 町田
洋弘 町田
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2011259423A priority Critical patent/JP5778557B2/ja
Priority to US13/680,880 priority patent/US9087843B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Layout of the interconnection structure
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
JP2011259423A 2011-11-28 2011-11-28 半導体装置の製造方法、半導体装置、及び半導体素子 Active JP5778557B2 (ja)

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JP2011259423A JP5778557B2 (ja) 2011-11-28 2011-11-28 半導体装置の製造方法、半導体装置、及び半導体素子
US13/680,880 US9087843B2 (en) 2011-11-28 2012-11-19 Semiconductor device manufacturing method, semiconductor device, and semiconductor element

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JP2011259423A JP5778557B2 (ja) 2011-11-28 2011-11-28 半導体装置の製造方法、半導体装置、及び半導体素子

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JP2013115205A JP2013115205A (ja) 2013-06-10
JP2013115205A5 JP2013115205A5 (enExample) 2014-09-11
JP5778557B2 true JP5778557B2 (ja) 2015-09-16

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WO2015107871A1 (ja) * 2014-01-15 2015-07-23 パナソニックＩｐマネジメント株式会社 半導体装置
JP6123738B2 (ja) * 2014-06-06 2017-05-10 富士電機株式会社 半導体装置
TWI697058B (zh) * 2016-03-30 2020-06-21 胡志良 具堅實導電及導熱性銅質線路之電路元件封裝方法及其封裝體
JP7714291B2 (ja) * 2020-12-31 2025-07-29 インターナショナル・ビジネス・マシーンズ・コーポレーション 方法および装置（基板へのチップの組立て）
US11824037B2 (en) * 2020-12-31 2023-11-21 International Business Machines Corporation Assembly of a chip to a substrate

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JP3000975B2 (ja) * 1997-10-20 2000-01-17 富士通株式会社 半導体素子の実装構造
JP3420076B2 (ja) * 1998-08-31 2003-06-23 新光電気工業株式会社 フリップチップ実装基板の製造方法及びフリップチップ実装基板及びフリップチップ実装構造
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