JP5778557B2 - 半導体装置の製造方法、半導体装置、及び半導体素子 - Google Patents

半導体装置の製造方法、半導体装置、及び半導体素子 Download PDF

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Publication number
JP5778557B2
JP5778557B2 JP2011259423A JP2011259423A JP5778557B2 JP 5778557 B2 JP5778557 B2 JP 5778557B2 JP 2011259423 A JP2011259423 A JP 2011259423A JP 2011259423 A JP2011259423 A JP 2011259423A JP 5778557 B2 JP5778557 B2 JP 5778557B2
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Prior art keywords
electrode
semiconductor element
pad
pads
center
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JP2011259423A
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Japanese (ja)
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JP2013115205A (ja
JP2013115205A5 (enExample
Inventor
洋弘 町田
洋弘 町田
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2011259423A priority Critical patent/JP5778557B2/ja
Priority to US13/680,880 priority patent/US9087843B2/en
Publication of JP2013115205A publication Critical patent/JP2013115205A/ja
Publication of JP2013115205A5 publication Critical patent/JP2013115205A5/ja
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07231—Techniques
    • H10W72/07236—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H10W72/07254—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/231—Shapes
    • H10W72/232—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H10W72/248—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Wire Bonding (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
JP2011259423A 2011-11-28 2011-11-28 半導体装置の製造方法、半導体装置、及び半導体素子 Active JP5778557B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011259423A JP5778557B2 (ja) 2011-11-28 2011-11-28 半導体装置の製造方法、半導体装置、及び半導体素子
US13/680,880 US9087843B2 (en) 2011-11-28 2012-11-19 Semiconductor device manufacturing method, semiconductor device, and semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2011259423A JP5778557B2 (ja) 2011-11-28 2011-11-28 半導体装置の製造方法、半導体装置、及び半導体素子

Publications (3)

Publication Number Publication Date
JP2013115205A JP2013115205A (ja) 2013-06-10
JP2013115205A5 JP2013115205A5 (enExample) 2014-09-11
JP5778557B2 true JP5778557B2 (ja) 2015-09-16

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JP2011259423A Active JP5778557B2 (ja) 2011-11-28 2011-11-28 半導体装置の製造方法、半導体装置、及び半導体素子

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US (1) US9087843B2 (enExample)
JP (1) JP5778557B2 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2015107871A1 (ja) * 2014-01-15 2015-07-23 パナソニックＩｐマネジメント株式会社 半導体装置
JP6123738B2 (ja) * 2014-06-06 2017-05-10 富士電機株式会社 半導体装置
TWI697058B (zh) * 2016-03-30 2020-06-21 胡志良 具堅實導電及導熱性銅質線路之電路元件封裝方法及其封裝體
JP7714291B2 (ja) * 2020-12-31 2025-07-29 インターナショナル・ビジネス・マシーンズ・コーポレーション 方法および装置（基板へのチップの組立て）
US11824037B2 (en) 2020-12-31 2023-11-21 International Business Machines Corporation Assembly of a chip to a substrate

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3390664B2 (ja) 1997-10-16 2003-03-24 新光電気工業株式会社 フリップチップ実装用基板及びフリップチップ実装構造
JP3000975B2 (ja) * 1997-10-20 2000-01-17 富士通株式会社 半導体素子の実装構造
JP3420076B2 (ja) * 1998-08-31 2003-06-23 新光電気工業株式会社 フリップチップ実装基板の製造方法及びフリップチップ実装基板及びフリップチップ実装構造
US6624003B1 (en) * 2002-02-06 2003-09-23 Teravicta Technologies, Inc. Integrated MEMS device and package
JP3829325B2 (ja) * 2002-02-07 2006-10-04 日本電気株式会社 半導体素子およびその製造方法並びに半導体装置の製造方法
JP2005268346A (ja) * 2004-03-17 2005-09-29 Nagase & Co Ltd 半導体パッケージ基板とその製造方法
JP2006147620A (ja) * 2004-11-16 2006-06-08 Toshiba Corp フリップチップ実装半導体装置の製造方法及びフリップチップ実装半導体装置
JP2007012953A (ja) * 2005-07-01 2007-01-18 Yokogawa Electric Corp フリップチップ接合方法
JP2007061531A (ja) 2005-09-02 2007-03-15 Junya Saito 防災頭巾機能付きバッグ
JPWO2007069606A1 (ja) * 2005-12-14 2009-05-21 新光電気工業株式会社 チップ内蔵基板の製造方法
JP4971769B2 (ja) * 2005-12-22 2012-07-11 新光電気工業株式会社 フリップチップ実装構造及びフリップチップ実装構造の製造方法
JP4618260B2 (ja) * 2007-02-21 2011-01-26 日本テキサス・インスツルメンツ株式会社 導体パターンの形成方法、半導体装置の製造方法、並びに半導体装置
JP5050583B2 (ja) 2007-03-12 2012-10-17 富士通セミコンダクター株式会社 配線基板及び電子部品の実装構造
JP5172590B2 (ja) * 2008-10-14 2013-03-27 新光電気工業株式会社 積層配線基板の樹脂封止方法及び樹脂封止装置
DE102008063401A1 (de) * 2008-12-31 2010-07-08 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement mit einem kosteneffizienten Chipgehäuse, das auf der Grundlage von Metallsäuren angeschlossen ist
JP2010278318A (ja) * 2009-05-29 2010-12-09 Renesas Electronics Corp 半導体装置
JP5367523B2 (ja) * 2009-09-25 2013-12-11 新光電気工業株式会社 配線基板及び配線基板の製造方法
JP5789431B2 (ja) * 2011-06-30 2015-10-07 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

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Publication number Publication date
US20130134593A1 (en) 2013-05-30
JP2013115205A (ja) 2013-06-10
US9087843B2 (en) 2015-07-21

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