JP5730654B2 - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

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Publication number
JP5730654B2
JP5730654B2 JP2011094296A JP2011094296A JP5730654B2 JP 5730654 B2 JP5730654 B2 JP 5730654B2 JP 2011094296 A JP2011094296 A JP 2011094296A JP 2011094296 A JP2011094296 A JP 2011094296A JP 5730654 B2 JP5730654 B2 JP 5730654B2
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Prior art keywords
conductive layer
groove
layer
hole
insulating layer
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JP2011094296A
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English (en)
Japanese (ja)
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JP2012028735A5 (https=
JP2012028735A (ja
Inventor
昌宏 春原
昌宏 春原
孝幸 徳永
孝幸 徳永
坂口　秀明
秀明 坂口
昭仁 高野
昭仁 高野
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2011094296A priority Critical patent/JP5730654B2/ja
Priority to US13/164,129 priority patent/US8446013B2/en
Publication of JP2012028735A publication Critical patent/JP2012028735A/ja
Publication of JP2012028735A5 publication Critical patent/JP2012028735A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0261—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias characterised by the filling method or the material of the conductive fill
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H10W70/687—Shapes or dispositions thereof comprising multiple insulating layers characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/692—Ceramics or glasses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/036—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being within a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2011094296A 2010-06-24 2011-04-20 配線基板及びその製造方法 Active JP5730654B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011094296A JP5730654B2 (ja) 2010-06-24 2011-04-20 配線基板及びその製造方法
US13/164,129 US8446013B2 (en) 2010-06-24 2011-06-20 Wiring substrate and method for manufacturing the wiring substrate

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2010143876 2010-06-24
JP2010143876 2010-06-24
JP2011094296A JP5730654B2 (ja) 2010-06-24 2011-04-20 配線基板及びその製造方法

Publications (3)

Publication Number Publication Date
JP2012028735A JP2012028735A (ja) 2012-02-09
JP2012028735A5 JP2012028735A5 (https=) 2014-03-06
JP5730654B2 true JP5730654B2 (ja) 2015-06-10

Family

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JP2011094296A Active JP5730654B2 (ja) 2010-06-24 2011-04-20 配線基板及びその製造方法

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Country Link
US (1) US8446013B2 (https=)
JP (1) JP5730654B2 (https=)

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US8476704B2 (en) * 2011-08-19 2013-07-02 Nan Ya Technology Corporation Circuit structure with vertical double gate
SE538058C2 (sv) 2012-03-30 2016-02-23 Silex Microsystems Ab Metod att tillhandahålla ett viahål och en routing-struktur
US9673132B2 (en) * 2012-04-27 2017-06-06 Taiwan Semiconductor Manufacting Company, Ltd. Interconnection structure with confinement layer
US8772945B2 (en) * 2012-04-27 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via with embedded barrier pad
US9136160B2 (en) * 2012-06-29 2015-09-15 Institute of Microelectronics, Chinese Academy of Sciences Solid hole array and method for forming the same
JP5826782B2 (ja) * 2013-03-19 2015-12-02 株式会社東芝 半導体装置の製造方法
US20140306349A1 (en) * 2013-04-11 2014-10-16 Qualcomm Incorporated Low cost interposer comprising an oxidation layer
US9865523B2 (en) 2014-01-17 2018-01-09 Taiwan Semiconductor Manufacturing Company, Ltd. Robust through-silicon-via structure
US9659851B2 (en) * 2014-02-07 2017-05-23 Marvell World Trade Ltd. Method and apparatus for improving the reliability of a connection to a via in a substrate
KR102211741B1 (ko) * 2014-07-21 2021-02-03 삼성전기주식회사 인쇄회로기판 및 인쇄회로기판의 제조 방법
DE102014115105B4 (de) * 2014-10-09 2023-06-22 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitereinrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung
US10515884B2 (en) * 2015-02-17 2019-12-24 Advanced Semiconductor Engineering, Inc. Substrate having a conductive structure within photo-sensitive resin
US20190385718A1 (en) 2018-06-14 2019-12-19 Astrazeneca Uk Limited Methods for lowering triglyceride levels with a concentrated fish oil-based pharmaceutical composition
MY201172A (en) * 2018-09-19 2024-02-08 Intel Corp Stacked through-silicon vias for multi-device packages
CN110808229B (zh) * 2019-11-15 2022-02-01 北京航空航天大学 一种硅基上高深宽比微纳通孔的填充方法
US11315862B2 (en) * 2020-01-31 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US20230197646A1 (en) * 2021-12-21 2023-06-22 Intel Corporation Low loss microstrip and stripline routing with blind trench vias for high speed signaling on a glass core
US20250079243A1 (en) * 2023-08-30 2025-03-06 Absolics Inc. Packaging substrate and method of manufacturing the same

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JPS6235693A (ja) * 1985-08-09 1987-02-16 末広　照朗 回路基板
TW561803B (en) * 2002-10-24 2003-11-11 Advanced Semiconductor Eng Circuit substrate and manufacturing method thereof
JP4056854B2 (ja) 2002-11-05 2008-03-05 新光電気工業株式会社 半導体装置の製造方法
US7345350B2 (en) * 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
US7088003B2 (en) * 2004-02-19 2006-08-08 International Business Machines Corporation Structures and methods for integration of ultralow-k dielectrics with improved reliability
WO2005093827A1 (ja) * 2004-03-26 2005-10-06 Fujikura Ltd. 貫通配線基板及びその製造方法
JP4800585B2 (ja) * 2004-03-30 2011-10-26 ルネサスエレクトロニクス株式会社 貫通電極の製造方法、シリコンスペーサーの製造方法
JP4955935B2 (ja) * 2004-05-25 2012-06-20 キヤノン株式会社 貫通孔形成方法および半導体装置の製造方法
JP4443379B2 (ja) * 2004-10-26 2010-03-31 三洋電機株式会社 半導体装置の製造方法
JP4369348B2 (ja) * 2004-11-08 2009-11-18 新光電気工業株式会社 基板及びその製造方法
JP4667076B2 (ja) * 2005-03-04 2011-04-06 ソニーケミカル＆インフォメーションデバイス株式会社 機能素子実装モジュールの実装方法
JP2007201361A (ja) * 2006-01-30 2007-08-09 Shinko Electric Ind Co Ltd 半導体装置及び半導体装置の製造方法
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US20110316169A1 (en) 2011-12-29
JP2012028735A (ja) 2012-02-09
US8446013B2 (en) 2013-05-21

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