JP5730654B2 - 配線基板及びその製造方法 - Google Patents

配線基板及びその製造方法 Download PDF

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Publication number
JP5730654B2
JP5730654B2 JP2011094296A JP2011094296A JP5730654B2 JP 5730654 B2 JP5730654 B2 JP 5730654B2 JP 2011094296 A JP2011094296 A JP 2011094296A JP 2011094296 A JP2011094296 A JP 2011094296A JP 5730654 B2 JP5730654 B2 JP 5730654B2
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Japan
Prior art keywords
conductive layer
groove
layer
hole
insulating layer
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Active
Application number
JP2011094296A
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English (en)
Japanese (ja)
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JP2012028735A (ja
JP2012028735A5 (enExample
Inventor
昌宏 春原
昌宏 春原
孝幸 徳永
孝幸 徳永
坂口　秀明
秀明 坂口
昭仁 高野
昭仁 高野
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2011094296A priority Critical patent/JP5730654B2/ja
Priority to US13/164,129 priority patent/US8446013B2/en
Publication of JP2012028735A publication Critical patent/JP2012028735A/ja
Publication of JP2012028735A5 publication Critical patent/JP2012028735A5/ja
Application granted granted Critical
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/147—Semiconductor insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/15—Ceramic or glass substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
JP2011094296A 2010-06-24 2011-04-20 配線基板及びその製造方法 Active JP5730654B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011094296A JP5730654B2 (ja) 2010-06-24 2011-04-20 配線基板及びその製造方法
US13/164,129 US8446013B2 (en) 2010-06-24 2011-06-20 Wiring substrate and method for manufacturing the wiring substrate

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2010143876 2010-06-24
JP2010143876 2010-06-24
JP2011094296A JP5730654B2 (ja) 2010-06-24 2011-04-20 配線基板及びその製造方法

Publications (3)

Publication Number Publication Date
JP2012028735A JP2012028735A (ja) 2012-02-09
JP2012028735A5 JP2012028735A5 (enExample) 2014-03-06
JP5730654B2 true JP5730654B2 (ja) 2015-06-10

Family

ID=45351766

Family Applications (1)

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JP2011094296A Active JP5730654B2 (ja) 2010-06-24 2011-04-20 配線基板及びその製造方法

Country Status (2)

Country Link
US (1) US8446013B2 (enExample)
JP (1) JP5730654B2 (enExample)

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US8476704B2 (en) * 2011-08-19 2013-07-02 Nan Ya Technology Corporation Circuit structure with vertical double gate
SE538058C2 (sv) 2012-03-30 2016-02-23 Silex Microsystems Ab Metod att tillhandahålla ett viahål och en routing-struktur
US9673132B2 (en) * 2012-04-27 2017-06-06 Taiwan Semiconductor Manufacting Company, Ltd. Interconnection structure with confinement layer
US8772945B2 (en) * 2012-04-27 2014-07-08 Taiwan Semiconductor Manufacturing Company, Ltd. Through silicon via with embedded barrier pad
US9136160B2 (en) * 2012-06-29 2015-09-15 Institute of Microelectronics, Chinese Academy of Sciences Solid hole array and method for forming the same
JP5826782B2 (ja) * 2013-03-19 2015-12-02 株式会社東芝 半導体装置の製造方法
US20140306349A1 (en) * 2013-04-11 2014-10-16 Qualcomm Incorporated Low cost interposer comprising an oxidation layer
US9865523B2 (en) 2014-01-17 2018-01-09 Taiwan Semiconductor Manufacturing Company, Ltd. Robust through-silicon-via structure
US9659851B2 (en) * 2014-02-07 2017-05-23 Marvell World Trade Ltd. Method and apparatus for improving the reliability of a connection to a via in a substrate
KR102211741B1 (ko) * 2014-07-21 2021-02-03 삼성전기주식회사 인쇄회로기판 및 인쇄회로기판의 제조 방법
DE102014115105B4 (de) 2014-10-09 2023-06-22 Taiwan Semiconductor Manufacturing Company, Ltd. Halbleitereinrichtung und Verfahren zur Herstellung einer Halbleitereinrichtung
US10515884B2 (en) * 2015-02-17 2019-12-24 Advanced Semiconductor Engineering, Inc. Substrate having a conductive structure within photo-sensitive resin
WO2019241563A1 (en) 2018-06-14 2019-12-19 Astrazeneca Uk Limited Methods for lowering triglyceride levels with a concentrated fish oil-based pharmaceutical composition
MY201172A (en) * 2018-09-19 2024-02-08 Intel Corp Stacked through-silicon vias for multi-device packages
CN110808229B (zh) * 2019-11-15 2022-02-01 北京航空航天大学 一种硅基上高深宽比微纳通孔的填充方法
US11315862B2 (en) * 2020-01-31 2022-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
US20230197646A1 (en) * 2021-12-21 2023-06-22 Intel Corporation Low loss microstrip and stripline routing with blind trench vias for high speed signaling on a glass core

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JPS6235693A (ja) * 1985-08-09 1987-02-16 末広　照朗 回路基板
TW561803B (en) * 2002-10-24 2003-11-11 Advanced Semiconductor Eng Circuit substrate and manufacturing method thereof
JP4056854B2 (ja) 2002-11-05 2008-03-05 新光電気工業株式会社 半導体装置の製造方法
US7345350B2 (en) * 2003-09-23 2008-03-18 Micron Technology, Inc. Process and integration scheme for fabricating conductive components, through-vias and semiconductor components including conductive through-wafer vias
US7088003B2 (en) * 2004-02-19 2006-08-08 International Business Machines Corporation Structures and methods for integration of ultralow-k dielectrics with improved reliability
EP1739739A4 (en) * 2004-03-26 2010-02-24 Fujikura Ltd WINDING BOARD AND MANUFACTURING METHOD THEREFOR
JP4800585B2 (ja) * 2004-03-30 2011-10-26 ルネサスエレクトロニクス株式会社 貫通電極の製造方法、シリコンスペーサーの製造方法
JP4955935B2 (ja) * 2004-05-25 2012-06-20 キヤノン株式会社 貫通孔形成方法および半導体装置の製造方法
JP4443379B2 (ja) * 2004-10-26 2010-03-31 三洋電機株式会社 半導体装置の製造方法
JP4369348B2 (ja) * 2004-11-08 2009-11-18 新光電気工業株式会社 基板及びその製造方法
JP4667076B2 (ja) * 2005-03-04 2011-04-06 ソニーケミカル＆インフォメーションデバイス株式会社 機能素子実装モジュールの実装方法
JP2007201361A (ja) * 2006-01-30 2007-08-09 Shinko Electric Ind Co Ltd 半導体装置及び半導体装置の製造方法
JP2008028336A (ja) * 2006-07-25 2008-02-07 Shinko Electric Ind Co Ltd 電子部品の製造方法
JP5143382B2 (ja) * 2006-07-27 2013-02-13 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
US20080136038A1 (en) * 2006-12-06 2008-06-12 Sergey Savastiouk Integrated circuits with conductive features in through holes passing through other conductive features and through a semiconductor substrate
JP5154789B2 (ja) * 2006-12-21 2013-02-27 ルネサスエレクトロニクス株式会社 半導体装置並びに半導体装置の製造方法
JP5089336B2 (ja) 2007-10-29 2012-12-05 新光電気工業株式会社 パッケージ用シリコン基板
KR100928509B1 (ko) * 2007-12-24 2009-11-26 주식회사 동부하이텍 반도체 소자 및 그의 제조 방법
JP5000540B2 (ja) * 2008-01-31 2012-08-15 新光電気工業株式会社 スイッチング機能付配線基板

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Publication number Publication date
JP2012028735A (ja) 2012-02-09
US8446013B2 (en) 2013-05-21
US20110316169A1 (en) 2011-12-29

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