JP5723363B2 - 非対称なビルドアップ層を有する基板を製造する方法 - Google Patents

非対称なビルドアップ層を有する基板を製造する方法 Download PDF

Info

Publication number
JP5723363B2
JP5723363B2 JP2012521917A JP2012521917A JP5723363B2 JP 5723363 B2 JP5723363 B2 JP 5723363B2 JP 2012521917 A JP2012521917 A JP 2012521917A JP 2012521917 A JP2012521917 A JP 2012521917A JP 5723363 B2 JP5723363 B2 JP 5723363B2
Authority
JP
Japan
Prior art keywords
layers
layer
build
buildup
core
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2012521917A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013501345A5 (cg-RX-API-DMAC10.html
JP2013501345A (ja
Inventor
レオン アンドリュー
レオン アンドリュー
トーパシオ ローデン
トーパシオ ローデン
マルティネス リアン
マルティネス リアン
セン ロウ イップ
セン ロウ イップ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ATI Technologies ULC
Original Assignee
ATI Technologies ULC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ATI Technologies ULC filed Critical ATI Technologies ULC
Publication of JP2013501345A publication Critical patent/JP2013501345A/ja
Publication of JP2013501345A5 publication Critical patent/JP2013501345A5/ja
Application granted granted Critical
Publication of JP5723363B2 publication Critical patent/JP5723363B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/02—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by a sequence of laminating steps, e.g. by adding new layers at consecutive laminating stations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2309/00—Parameters for the laminating or treatment process; Apparatus details
    • B32B2309/08—Dimensions, e.g. volume
    • B32B2309/10—Dimensions, e.g. volume linear, e.g. length, distance, width
    • B32B2309/105—Thickness
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2310/00—Treatment by energy or chemical effects
    • B32B2310/08—Treatment by energy or chemical effects by wave energy or particle radiation
    • B32B2310/0806—Treatment by energy or chemical effects by wave energy or particle radiation using electromagnetic radiation
    • B32B2310/0843—Treatment by energy or chemical effects by wave energy or particle radiation using electromagnetic radiation using laser
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B2457/00—Electrical equipment
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09136—Means for correcting warpage
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2012521917A 2009-07-31 2010-07-28 非対称なビルドアップ層を有する基板を製造する方法 Active JP5723363B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/533,569 2009-07-31
US12/533,569 US20110024898A1 (en) 2009-07-31 2009-07-31 Method of manufacturing substrates having asymmetric buildup layers
PCT/CA2010/001174 WO2011011880A1 (en) 2009-07-31 2010-07-28 A method of manufacturing substrates having asymmetric buildup layers

Publications (3)

Publication Number Publication Date
JP2013501345A JP2013501345A (ja) 2013-01-10
JP2013501345A5 JP2013501345A5 (cg-RX-API-DMAC10.html) 2013-08-22
JP5723363B2 true JP5723363B2 (ja) 2015-05-27

Family

ID=43526212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012521917A Active JP5723363B2 (ja) 2009-07-31 2010-07-28 非対称なビルドアップ層を有する基板を製造する方法

Country Status (6)

Country Link
US (2) US20110024898A1 (cg-RX-API-DMAC10.html)
EP (1) EP2460393B1 (cg-RX-API-DMAC10.html)
JP (1) JP5723363B2 (cg-RX-API-DMAC10.html)
KR (1) KR101633839B1 (cg-RX-API-DMAC10.html)
CN (1) CN102656955B (cg-RX-API-DMAC10.html)
WO (1) WO2011011880A1 (cg-RX-API-DMAC10.html)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8598698B1 (en) * 2010-07-21 2013-12-03 Altera Corporation Package substrate with an embedded stiffener
RU2612572C2 (ru) 2011-04-08 2017-03-09 Конинклейке Филипс Н.В. Система обработки изображений и способ
US8945329B2 (en) * 2011-06-24 2015-02-03 Ibiden Co., Ltd. Printed wiring board and method for manufacturing printed wiring board
JP2013048205A (ja) * 2011-07-25 2013-03-07 Ngk Spark Plug Co Ltd 配線基板の製造方法
CN104160497B (zh) * 2011-12-20 2017-10-27 英特尔公司 微电子封装和层叠微电子组件以及包括该封装和组件的计算系统
US9059179B2 (en) 2011-12-28 2015-06-16 Broadcom Corporation Semiconductor package with a bridge interposer
US20130181359A1 (en) * 2012-01-13 2013-07-18 TW Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for Thinner Package on Package Structures
JP5941735B2 (ja) 2012-04-10 2016-06-29 新光電気工業株式会社 配線基板の製造方法及び配線基板
KR101921258B1 (ko) 2012-05-09 2018-11-22 삼성전자주식회사 배선 기판 및 이를 포함하는 반도체 패키지
JP2014086651A (ja) * 2012-10-26 2014-05-12 Ibiden Co Ltd プリント配線板及びプリント配線板の製造方法
KR101431911B1 (ko) * 2012-12-06 2014-08-26 삼성전기주식회사 인쇄회로기판 및 그 제조방법
US9299649B2 (en) 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8802504B1 (en) * 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
KR20150083278A (ko) * 2014-01-09 2015-07-17 삼성전기주식회사 다층기판 및 다층기판의 제조방법
KR102250997B1 (ko) 2014-05-02 2021-05-12 삼성전자주식회사 반도체 패키지
CN104883810B (zh) * 2015-05-15 2018-07-06 江门崇达电路技术有限公司 一种具有密集散热孔的pcb的制作方法
US11277922B2 (en) 2016-10-06 2022-03-15 Advanced Micro Devices, Inc. Circuit board with bridge chiplets
US11560465B2 (en) 2017-03-31 2023-01-24 Eneos Corporation Composition for curable resin, cured product of said composition, method of producing said composition and said cured product, and semiconductor device
US10510721B2 (en) 2017-08-11 2019-12-17 Advanced Micro Devices, Inc. Molded chip combination
EP3470681B1 (de) * 2017-10-10 2021-09-22 Pfeiffer Vacuum Gmbh Elektrische durchführung für ein vakuumgerät, in der form einer dichtungsplatine
US20190287872A1 (en) 2018-03-19 2019-09-19 Intel Corporation Multi-use package architecture
US10593628B2 (en) 2018-04-24 2020-03-17 Advanced Micro Devices, Inc. Molded die last chip combination
US10672712B2 (en) 2018-07-30 2020-06-02 Advanced Micro Devices, Inc. Multi-RDL structure packages and methods of fabricating the same
US10923430B2 (en) 2019-06-30 2021-02-16 Advanced Micro Devices, Inc. High density cross link die with polymer routing layer
GB202018676D0 (en) * 2020-11-27 2021-01-13 Graphcore Ltd Controlling warpage of a substrate for mounting a semiconductor die
US20230086356A1 (en) * 2021-09-21 2023-03-23 Intel Corporation Glass core substrate including buildups with different numbers of layers

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1999026458A1 (en) * 1997-11-19 1999-05-27 Ibiden Co., Ltd. Multilayer printed wiring board and method for manufacturing the same
JP4128649B2 (ja) * 1998-03-26 2008-07-30 富士通株式会社 薄膜多層回路基板の製造方法
JPH11340610A (ja) * 1998-05-26 1999-12-10 Ibiden Co Ltd スルーホール充填用樹脂組成物及び多層プリント配線板
KR100642167B1 (ko) * 1998-09-18 2006-11-02 훈츠만 어드밴스트 머티리얼스(스위처랜드)게엠베하 다층 회로의 제조방법
JP3577421B2 (ja) * 1999-01-25 2004-10-13 新光電気工業株式会社 半導体装置用パッケージ
WO2000079849A1 (en) * 1999-06-18 2000-12-28 Isola Laminate Systems Corp. High performance ball grid array substrates
TW512653B (en) * 1999-11-26 2002-12-01 Ibiden Co Ltd Multilayer circuit board and semiconductor device
US6720644B2 (en) * 2000-10-10 2004-04-13 Sony Corporation Semiconductor device using interposer substrate and manufacturing method therefor
JP2002290031A (ja) * 2001-03-23 2002-10-04 Ngk Spark Plug Co Ltd 配線基板およびその製造方法
JP4243117B2 (ja) * 2002-08-27 2009-03-25 新光電気工業株式会社 半導体パッケージとその製造方法および半導体装置
US20060289203A1 (en) * 2003-05-19 2006-12-28 Dai Nippon Printing Co., Ltd. Double-sided wiring board, double sided wiring board manufacturing method, and multilayer wiring board
CN1792126A (zh) * 2003-05-19 2006-06-21 大日本印刷株式会社 双面布线基板和双面布线基板的制造方法以及多层布线基板
JP2005159201A (ja) * 2003-11-28 2005-06-16 Ngk Spark Plug Co Ltd 配線基板およびその製造方法
KR20070086706A (ko) * 2004-12-28 2007-08-27 니뽄 도쿠슈 도교 가부시키가이샤 배선 기판 및 배선 기판의 제조 방법
US7355283B2 (en) * 2005-04-14 2008-04-08 Sandisk Corporation Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packaging
US20070020908A1 (en) * 2005-07-18 2007-01-25 Tessera, Inc. Multilayer structure having a warpage-compensating layer
JP4452222B2 (ja) * 2005-09-07 2010-04-21 新光電気工業株式会社 多層配線基板及びその製造方法
JP2008098570A (ja) * 2006-10-16 2008-04-24 Sharp Corp 多層プリント配線基板の製造方法
CN101869008B (zh) * 2007-12-26 2012-08-29 松下电器产业株式会社 半导体装置和多层配线基板

Also Published As

Publication number Publication date
US20110225813A1 (en) 2011-09-22
EP2460393A1 (en) 2012-06-06
JP2013501345A (ja) 2013-01-10
CN102656955A (zh) 2012-09-05
US20110024898A1 (en) 2011-02-03
WO2011011880A1 (en) 2011-02-03
KR101633839B1 (ko) 2016-06-27
KR20120036318A (ko) 2012-04-17
EP2460393A4 (en) 2015-03-04
CN102656955B (zh) 2015-04-15
EP2460393B1 (en) 2017-10-11
US8298945B2 (en) 2012-10-30

Similar Documents

Publication Publication Date Title
KR101633839B1 (ko) 비대칭 빌드업 층들을 가지는 기판의 제조 방법
JP5826532B2 (ja) 半導体装置及びその製造方法
CN103369816B (zh) 电路板及其制造方法
CN104428892B (zh) 用于基板核心层的方法和装置
US20100044845A1 (en) Circuit substrate, an electronic device arrangement and a manufacturing process for the circuit substrate
TWI594345B (zh) 超微細間距層疊封裝（ＰｏＰ）無核心封裝
JP2007142403A (ja) プリント基板及びその製造方法
KR101831643B1 (ko) 표면 상호 연결부 및 무전해 충진물을 포함하는 캐비티를 포함하는 패키지 기판
US6838314B2 (en) Substrate with stacked vias and fine circuits thereon, and method for fabricating the same
KR20150006686A (ko) 반도체 패키지 및 그 제조 방법
CN105321915A (zh) 嵌入式板及其制造方法
KR20150093032A (ko) 임베디드 기판, 인쇄회로기판 및 그 제조 방법
US20120152606A1 (en) Printed wiring board
CN101290888A (zh) 用于半导体封装的印刷电路板的制造方法
JP2007324559A (ja) ファインピッチを有するマルチレイヤー回路板及びその製作方法
JP5989329B2 (ja) プリント回路基板の製造方法
KR20150065029A (ko) 인쇄회로기판, 그 제조방법 및 반도체 패키지
KR100908986B1 (ko) 코어리스 패키지 기판 및 제조 방법
KR20040076165A (ko) 도금 인입선을 사용하지 않는 패키지 기판 및 그 제조 방법
KR100704911B1 (ko) 전자소자 내장형 인쇄회로기판 및 그 제조방법
KR20030011433A (ko) 다층 인쇄회로기판의 숨겨진 레이저 비아홀 제조방법
KR100477258B1 (ko) 범프의 형성방법 및 이로부터 형성된 범프를 이용한인쇄회로기판의 제조방법
KR20120026368A (ko) 인쇄회로기판 및 그 제조방법
KR200257974Y1 (ko) 숨겨진 레이저 비아홀을 갖는 다층 인쇄회로기판
KR20030011434A (ko) 다층 인쇄회로기판의 숨겨진 레이저 비아홀 제조방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130705

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20130705

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140307

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140312

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20140611

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20140618

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20140711

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20140718

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20140811

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20140818

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140911

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20150303

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20150327

R150 Certificate of patent or registration of utility model

Ref document number: 5723363

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250