JP5707018B2 - フローティングボディ素子及びバルクボディ素子を有する半導体素子及びその製造方法 - Google Patents
フローティングボディ素子及びバルクボディ素子を有する半導体素子及びその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 144
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 238000000034 method Methods 0.000 title description 43
- 239000000758 substrate Substances 0.000 claims description 159
- 239000000463 material Substances 0.000 claims description 53
- 238000002955 isolation Methods 0.000 claims description 46
- 238000005530 etching Methods 0.000 claims description 25
- 238000002161 passivation Methods 0.000 claims description 14
- 239000007769 metal material Substances 0.000 claims description 10
- 238000000206 photolithography Methods 0.000 claims description 6
- 238000000926 separation method Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 210000000746 body region Anatomy 0.000 claims description 3
- 239000012528 membrane Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 243
- 239000011229 interlayer Substances 0.000 description 70
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 30
- 229910052710 silicon Inorganic materials 0.000 description 30
- 239000010703 silicon Substances 0.000 description 30
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 25
- 229910052814 silicon oxide Inorganic materials 0.000 description 25
- 239000011232 storage material Substances 0.000 description 22
- 229920002120 photoresistant polymer Polymers 0.000 description 21
- 238000003860 storage Methods 0.000 description 13
- 238000005520 cutting process Methods 0.000 description 8
- 125000006850 spacer group Chemical group 0.000 description 7
- 230000006870 function Effects 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 6
- 230000000149 penetrating effect Effects 0.000 description 6
- 239000004020 conductor Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000002159 nanocrystal Substances 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
- H01L27/1207—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
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- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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Description
106a 第1活性パターン
106b 第2活性パターン
106c 第3活性パターン
112 素子分離膜
122a 第1埋込誘電膜
122b 第2埋込誘電膜
122c 第3埋込誘電膜
124a 第1埋込パターン
124b 第2埋込パターン
124c 第3埋込パターン
125b 第1連結部
125c 第2連結部
136a 第1ゲート構造体
136b 第2ゲート構造体
136c 第3ゲート構造体
147 下部層間絶縁膜
148 第1下部導電性パターン
149a 第2下部導電性パターン
149b 第2下部コンタクト構造体
150a 第3下部導電性パターン
150b 第3下部コンタクト構造体
151 上部層間絶縁膜
154a 第1ゲートコンタクト構造体
154b 第2上部コンタクト構造体
154c 第3上部コンタクト構造体
157a 第1上部導電性パターン
157b 第1下部ゲート配線
158a 第2上部導電性パターン
158b 第2下部ゲート配線
206b 活性パターン
212 第1素子分離膜
212a 活性領域
224 埋込パターン
224a 連結部
227 第2素子分離膜
236a 第1ゲート構造体
236b 第2ゲート構造体
500 第1領域
510 第2領域
520 第3領域
530 第4領域
540 第5領域
550 半導体素子
560 第1パッシベーション膜
600 集積回路基板
610 基板間配線
620 第2パッシベーション膜
A 第1素子領域
B 第2素子領域
C 第3素子領域
J フローティングボディ素子領域
K バルクボディ素子領域
Claims (14)
- バルクボディ素子領域及びフローティングボディ素子領域を有する基板と、
前記バルクボディ素子領域の前記基板の活性領域を画定するとともに、前記フローティングボディ素子領域のうち第1素子領域の前記基板上に順に積層された第1埋込パターン及び第1活性パターンを画定する素子分離膜と、
前記第1埋込パターンと前記基板の間に介在されるとともに、前記第1埋込パターンと前記第1活性パターン間に介在された第1埋込誘電膜と、を含み、
前記第1埋込パターンを互いに連結する少なくとも一つの第1連結部をさらに含み、前記第1連結部は、前記第1埋込パターンと同一レベルに位置して前記第1埋込パターンと同一厚さを含み、前記第1埋込誘電膜は前記第1連結部と前記基板との間に位置する
ことを特徴とする半導体素子。 - 前記第1活性パターンは、前記第1埋込パターン上に自己整列された
ことを特徴とする請求項1に記載の半導体素子。 - 前記第1連結部は、前記第1活性パターンの側壁を前記第1埋込誘電膜の厚さ分離隔されて覆う
ことを特徴とする請求項1に記載の半導体素子。 - 前記第1埋込パターンは、n型ドープ半導体物質膜、p型ドープ半導体物質膜、アンドープ半導体物質膜または金属物質膜からなる
ことを特徴とする請求項1に記載の半導体素子。 - それぞれの前記第1埋込パターン上に、複数個の前記第1活性パターンが位置する
ことを特徴とする請求項1に記載の半導体素子。 - 前記フローティングボディ素子領域のうち第2素子領域の前記基板上に順に積層されて前記素子分離膜により画定される第2埋込パターン及び第2活性パターンと、
前記第2埋込パターンと前記基板間に介在されるとともに、前記第2埋込パターンと前記第2活性パターン間に介在された第2埋込誘電膜と、
前記第2埋込パターンを互いに連結して前記第2埋込パターンと同一レベルに位置する少なくとも一つの第2連結部と、をさらに含む
ことを特徴とする請求項1に記載の半導体素子。 - 前記第2活性パターンは、前記第1活性パターンと異なる厚さを有する
ことを特徴とする請求項6に記載の半導体素子。 - 前記第2埋込パターンは、前記第1埋込パターンと異なる厚さを有する
ことを特徴とする請求項6に記載の半導体素子。 - 前記第2埋込パターンは、前記第1埋込パターンと異なる特性の物質膜を含む
ことを特徴とする請求項6に記載の半導体素子。 - 前記第1埋込パターンに電気的に接続された第1下部ゲートコンタクト構造体と、
前記第2埋込パターンに電気的に接続された第2下部ゲートコンタクト構造体と、をさらに含む
ことを特徴とする請求項6に記載の半導体素子。 - 前記フローティングボディ素子領域のうち第3素子領域の前記基板上に、順に積層されて前記素子分離膜により画定される第3埋込パターン及び第3活性パターンと、
前記第3埋込パターンを互いに連結して前記第3活性パターンの側壁を覆う少なくとも一つの第3連結部と、
前記第3埋込パターンと前記基板との間、前記第3埋込パターンと前記第3活性パターンとの間、前記第3連結部と前記基板との間、及び前記第3連結部と前記第3活性パターンとの間に介在された第3埋込誘電膜と、をさらに含む
ことを特徴とする請求項1に記載の半導体素子。 - 前記基板上のパッシベーション膜と、
前記パッシベーション膜上の集積回路基板と、をさらに含む
ことを特徴とする請求項1に記載の半導体素子。 - バルクボディ素子領域及びフローティングボディ素子領域を有する基板を準備する工程と、
前記バルクボディ素子領域の前記基板の活性領域を画定するとともに、前記フローティングボディ素子領域のうち第1素子領域の前記基板上に順に積層された第1犠牲パターン及び第1活性パターンを画定する素子分離膜を形成する工程と、
フォトリソグラフィ及びエッチング工程を用いて前記素子分離膜に前記第1犠牲パターンの一部分を露出させる第1リセス領域を形成する工程と、
前記第1犠牲パターンを除去して前記第1活性パターン下部に第1空間を形成する工程と、
前記第1空間の内壁及び前記第1リセス領域の内壁に第1埋込誘電膜を形成する工程と、
前記第1埋込誘電膜を有する基板上に少なくとも前記第1空間を埋め込む第1埋込パターンを形成する工程と、を含み、
前記第1埋込パターンを互いに連結する少なくとも一つの第1連結部をさらに含み、前記第1連結部は、前記第1埋込パターンと同一レベルに位置して前記第1埋込パターンと同一厚さを含み、前記第一埋込誘電膜は前記第1連結部と前記基板との間に位置する
ことを特徴とする半導体素子の製造方法。 - 前記素子分離膜を形成する間に、前記フローティングボディ領域のうち第2素子領域の前記基板上に順に積層された第2犠牲パターン及び第2活性パターンを画定し、前記第2活性パターンは前記第1活性パターンと異なる厚さを有していて、
前記素子分離膜に前記第2犠牲パターンの一部分を露出させる第2リセス領域を形成する工程と、
前記第2犠牲パターンを除去して前記第2活性パターン下部に第2空間を形成する工程と、
前記第2空間の内壁及び前記第2リセス領域の内壁に第2埋込誘電膜を形成する工程と、をさらに含む
ことを特徴とする請求項13に記載の半導体素子の製造方法。
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KR10-2007-0064532 | 2007-06-28 | ||
KR1020070064532A KR100843717B1 (ko) | 2007-06-28 | 2007-06-28 | 플로팅 바디 소자 및 벌크 바디 소자를 갖는 반도체소자 및그 제조방법 |
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CN (1) | CN101369578B (ja) |
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