JP5685012B2 - 半導体パッケージの製造方法 - Google Patents

半導体パッケージの製造方法 Download PDF

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Publication number
JP5685012B2
JP5685012B2 JP2010147950A JP2010147950A JP5685012B2 JP 5685012 B2 JP5685012 B2 JP 5685012B2 JP 2010147950 A JP2010147950 A JP 2010147950A JP 2010147950 A JP2010147950 A JP 2010147950A JP 5685012 B2 JP5685012 B2 JP 5685012B2
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Japan
Prior art keywords
support
semiconductor chip
semiconductor
semiconductor package
sealing resin
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Active
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JP2010147950A
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English (en)
Japanese (ja)
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JP2012015191A (ja
JP2012015191A5 (enExample
Inventor
翔太 三木
翔太 三木
孝治 山野
孝治 山野
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2010147950A priority Critical patent/JP5685012B2/ja
Priority to US13/170,319 priority patent/US8779573B2/en
Publication of JP2012015191A publication Critical patent/JP2012015191A/ja
Publication of JP2012015191A5 publication Critical patent/JP2012015191A5/ja
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Publication of JP5685012B2 publication Critical patent/JP5685012B2/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/014—Manufacture or treatment using batch processing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2010147950A 2010-06-29 2010-06-29 半導体パッケージの製造方法 Active JP5685012B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2010147950A JP5685012B2 (ja) 2010-06-29 2010-06-29 半導体パッケージの製造方法
US13/170,319 US8779573B2 (en) 2010-06-29 2011-06-28 Semiconductor package having a silicon reinforcing member embedded in resin

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010147950A JP5685012B2 (ja) 2010-06-29 2010-06-29 半導体パッケージの製造方法

Publications (3)

Publication Number Publication Date
JP2012015191A JP2012015191A (ja) 2012-01-19
JP2012015191A5 JP2012015191A5 (enExample) 2013-05-16
JP5685012B2 true JP5685012B2 (ja) 2015-03-18

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010147950A Active JP5685012B2 (ja) 2010-06-29 2010-06-29 半導体パッケージの製造方法

Country Status (2)

Country Link
US (1) US8779573B2 (enExample)
JP (1) JP5685012B2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI476841B (zh) * 2012-03-03 2015-03-11 矽品精密工業股份有限公司 半導體封裝件及其製法
US9768038B2 (en) * 2013-12-23 2017-09-19 STATS ChipPAC, Pte. Ltd. Semiconductor device and method of making embedded wafer level chip scale packages
JP6495692B2 (ja) * 2015-03-11 2019-04-03 東芝メモリ株式会社 半導体装置及びその製造方法
US9899285B2 (en) * 2015-07-30 2018-02-20 Semtech Corporation Semiconductor device and method of forming small Z semiconductor package
JP6992751B2 (ja) 2016-06-28 2022-01-13 日本ゼオン株式会社 半導体パッケージ製造用支持体、半導体パッケージ製造用支持体の使用、及び半導体パッケージの製造方法
US10811298B2 (en) * 2018-12-31 2020-10-20 Micron Technology, Inc. Patterned carrier wafers and methods of making and using the same
JP7409558B2 (ja) 2021-03-29 2024-01-09 味の素株式会社 回路基板の製造方法
WO2024190442A1 (ja) 2023-03-10 2024-09-19 味の素株式会社 回路基板の製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4013452B2 (ja) * 2000-05-24 2007-11-28 松下電器産業株式会社 樹脂封止型半導体装置の製造方法
JP2001345411A (ja) * 2000-05-31 2001-12-14 Matsushita Electric Ind Co Ltd リードフレームとそれを用いた半導体装置及びその生産方法
JP4934900B2 (ja) 2000-12-15 2012-05-23 イビデン株式会社 多層プリント配線板の製造方法
JP3609737B2 (ja) * 2001-03-22 2005-01-12 三洋電機株式会社 回路装置の製造方法
JP2003347741A (ja) * 2002-05-30 2003-12-05 Taiyo Yuden Co Ltd 複合多層基板およびそれを用いたモジュール
JP3951854B2 (ja) 2002-08-09 2007-08-01 カシオ計算機株式会社 半導体装置およびその製造方法
JP3888267B2 (ja) 2002-08-30 2007-02-28 カシオ計算機株式会社 半導体装置およびその製造方法
JP4199588B2 (ja) * 2003-04-25 2008-12-17 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路基板の製造方法、及び、この配線回路基板を用いた半導体集積回路装置の製造方法
JP4298559B2 (ja) * 2004-03-29 2009-07-22 新光電気工業株式会社 電子部品実装構造及びその製造方法
JP4592413B2 (ja) * 2004-12-27 2010-12-01 三洋電機株式会社 回路装置
JP5117692B2 (ja) * 2006-07-14 2013-01-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US20080142946A1 (en) * 2006-12-13 2008-06-19 Advanced Chip Engineering Technology Inc. Wafer level package with good cte performance
CN102106198B (zh) * 2008-07-23 2013-05-01 日本电气株式会社 半导体装置及其制造方法
JP4420965B1 (ja) 2008-10-30 2010-02-24 新光電気工業株式会社 半導体装置内蔵基板の製造方法

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Publication number Publication date
JP2012015191A (ja) 2012-01-19
US8779573B2 (en) 2014-07-15
US20110316152A1 (en) 2011-12-29

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