CN107301956A - 晶片封装制程 - Google Patents

晶片封装制程 Download PDF

Info

Publication number
CN107301956A
CN107301956A CN201710655919.8A CN201710655919A CN107301956A CN 107301956 A CN107301956 A CN 107301956A CN 201710655919 A CN201710655919 A CN 201710655919A CN 107301956 A CN107301956 A CN 107301956A
Authority
CN
China
Prior art keywords
chip
wafer encapsulation
sealing
supporting construction
loading plate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710655919.8A
Other languages
English (en)
Other versions
CN107301956B (zh
Inventor
张文远
陈伟政
吕学忠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Zhaoxin Semiconductor Co Ltd
Original Assignee
VIA Alliance Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from TW106115540A external-priority patent/TWI719205B/zh
Application filed by VIA Alliance Semiconductor Co Ltd filed Critical VIA Alliance Semiconductor Co Ltd
Publication of CN107301956A publication Critical patent/CN107301956A/zh
Application granted granted Critical
Publication of CN107301956B publication Critical patent/CN107301956B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568Temporary substrate used as encapsulation process aid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19Manufacturing methods of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/37Effects of the manufacturing process
    • H01L2924/37001Yield

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Micromachines (AREA)

Abstract

一种晶片封装制程,其包括以下步骤:提供支撑结构及承载板,其中支撑结构具有多个开口,支撑结构配置于承载板上;在承载板上配置多个晶片,多个晶片分别位于支撑结构的多个开口中;形成覆盖支撑结构与多个晶片的封胶,支撑结构与多个晶片位于封胶与承载板之间,封胶填充于多个开口与多个晶片之间;移除承载板;以及在支撑结构上配置重布线路结构,其中重布线路结构连接多个晶片。本发明能提升结构强度且降低其制程的生产成本。

Description

晶片封装制程
技术领域
本发明是有关于一种晶片封装结构,且特别是有关于一种晶片封装阵列以及晶片封装体。
背景技术
在半导体产业中,集成电路(Integrated Circuits,IC)的生产,主要可分为三个阶段:集成电路设计(IC design)、集成电路的制作(IC process)及集成电路的封装(ICpackage)等。因此,裸晶片(die)是经由晶圆(wafer)制作、电路设计、光罩制作以及切割晶圆等步骤而完成,而裸晶片则经由打线接合(wire bonding)或覆晶接合(flip chipbonding)等方式,将裸晶片电性连接至承载器,例如导线架或介电层等,使得裸晶片的接合垫将可重布线路至晶片的周缘或晶片的有源表面的下方。接着,再以封装胶体(moldingcompound)包覆裸晶片,以保护裸晶片。
发明内容
本发明提供一种晶片封装制程,能提升结构强度且降低其制程的生产成本。
本发明提出一种晶片封装制程,其包括以下步骤:提供支撑结构及承载板,支撑结构具有多个开口,且支撑结构配置于承载板上;配置多个晶片在承载板上,多个晶片分别位于支撑结构的多个开口中;形成封胶覆盖支撑结构与多个晶片,支撑结构与多个晶片位于封胶与承载板之间,封胶填充于多个开口与多个晶片之间;移除承载板;以及配置重布线路结构在支撑结构上,其中重布线路结构连接多个晶片。
基于上述,在本发明的晶片封装制程中,由于晶片封装阵列的各晶片封装体的外围区域配置有支撑结构,因此,能改善封装过程中发生的翘曲,并且能提升晶片封装阵列的结构强度且降低其制程的生产成本,进而增加晶片封装体的产量。除此之外,支撑结构的配置也可以改善各晶片封装体的整体结构强度。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附图式作详细说明如下。
附图说明
图1A至图1F依序为本发明的一实施例的晶片封装制程的俯视示意图。
图2A至图2F分别是图1A至图1F的结构沿图1A的线A-A’的剖面示意图。
图3A是图1A及图2A的结构于完整状态下的立体示意图。
图3B是图1B及图2B的结构于完整状态下的立体示意图。
图3C是图1E及图2E的结构于完整状态下的立体示意图。
图4A为本发明的另一实施例的晶片封装体的俯视示意图。
图4B为本发明的另一实施例的晶片封装体的剖面示意图。
图5为本发明的又一实施例的晶片封装体的剖面示意图。
图6为本发明的再一实施例的晶片封装体的剖面示意图。
其中,附图中符号的简单说明如下:
50:晶片封装阵列;100、100A、100B、100C:晶片封装体;102:侧面;110:承载板;120:支撑结构;122:开口;124:顶面;126、126C:内面;128:凹槽;130:晶片;130a:接垫;132:第一面;140:无源元件;150、150A:封胶;160:重布线路结构;170:焊球;P1:第一参考平面;P2:第二参考平面;L:切割线。
具体实施方式
请参考图1A、图2A及图3A,其中图1A及图2A的结构的完整状态如图3A所示,意即图3A的结构的局部呈现于图1A及图2A。在本实施例的晶体封装制程中,提供支撑结构120及承载板110。支撑结构120配置于承载板110上。支撑结构120具有多个开口122。详细而言,在本实施例中,支撑结构120为一个网状结构,例如是一个网状的加强支撑件。如此一来,通过具有多个开口的支撑结构及承载板可改善封装过程中发生的翘曲,特别是对于尺寸较大的扇出型晶圆级封装(Fan-out wafer level package,FOWLP)或扇出型面板级封装(Fan-outpanel level package,FOPLP),其效果更加明显。此外,通过具有多个开口122的支撑结构120及承载板110能提升晶片封装阵列50(见于图3C)的结构强度且降低其制程的生产成本,进而增加晶片封装体100(见于图1F及图2F)的产量。
请参考图1B、图2B及图3B,其中图1B及图2B的结构的完整状态如图3B所示,意即图3B的结构的局部呈现于图1B及图2B。在上述步骤之后,配置多个晶片130在承载板110上,其中这些晶片130分别位于支撑结构120的多个开口122中。在本实施例中,一开口122中配置一晶片130,本发明不以此为限。在其他实施例中,一开口中可以配置多个晶片,其是利用堆叠的方式,配置于对应的开口中。在本实施例中,配置晶片130在承载板110上的步骤还包括,配置多个无源元件140在承载板110上,且位于晶片130与支撑结构120之间。举例而言,可在每个开口122中配置一个或多个无源元件140,以符合电性需求。
请参考图1C及图2C,在上述步骤之后,形成封胶150覆盖支撑结构120与晶片130,支撑结构120与晶片130位于封胶150与承载板110之间,封胶150填充于开口122与晶片130之间。换句话说,在此步骤中,将封胶150填充在支撑结构120上并且完整地覆盖住支撑结构120及晶片130,以使得支撑结构120中的每一个开口122皆充满封胶150进而固定支撑结构120及晶片130。除此之外,封胶150也完整地覆盖住无源元件140。
请参考图1D及图2D,在上述步骤之后,移除承载板110。由于封胶150充满在每一个开口122,因此支撑结构120与晶片130通过封胶150彼此固定连接而不会分离。此时,支撑结构120、晶片130、无源元件140与封胶150构成一第一参考平面P1,即支撑结构120、晶片130、无源元件140与封胶150共平面。
请参考图1E、图2E及图3C,其中图1E及图2E的结构的完整状态如图3C所示,意即图3C的结构的局部呈现于图1E及图2E。在上述步骤之后,配置重布线路结构160在支撑结构120上并且直接地连接晶片130,通过重布线路结构160的配置,可将原本配置在晶片130上的信号扇出(fan-out)至重布线路结构160的晶片130投影区外,进而增加晶片130的信号配置的弹性。另外,重布线路结构160的导电层部分可直接与晶片130上的接垫130a电性连接,而不需要额外再配置凸块(bump)。换句话说,重布线路结构160配置位于第一参考平面P1上并且直接地连接晶片130。此外,还可以配置多个焊球170在重布线路结构160上,而重布线路结构160位于晶片130与这些焊球170之间。至此,完成一晶片封装阵列50,如图3C所示,其包含多个尚未切割的晶片封装体100。
请参考图1F及图2F,在上述步骤之后,沿着多个开口122彼此之间的多个切割线L切割晶片封装阵列50,以形成单一个晶片封装体100,如图1F及图2F所绘示。换句话说,每个沿着切割线L切割支撑结构120所形成的晶片封装体100中具有支撑结构120的一部分,而此支撑结构120对于单一个晶片封装体100而言即为一个环状的加强支撑件,其能提升晶片封装体100的整体结构强度。更进一步来说,由于环状的加强支撑件对齐于切割线L进行切割而形成,故加强支撑件会暴露于单一个晶片封装体100的侧面102,因此对于晶片封装体100外围区域来说,提供了较强的保护,同样地,封胶150以及重布线路结构160也对齐于切割线L被切割而使得封胶150的一部分以及重布线路结构160的一部分暴露于单一个晶片封装体100的侧面102。
请再参考图1E、图2E及图3C,具体而言,在本实施例中,晶片封装阵列50包括多个晶片封装体100,且晶片封装体100适于阵列排列以形成晶片封装阵列50,如图3C所呈现。各晶片封装体100包括重布线路结构160、支撑结构120、晶片130以及封胶150。支撑结构120配置于重布线路结构160并具有开口122。晶片130配置于重布线路结构160并位于开口122中。封胶150位于开口122与晶片130之间,其中封胶150填充于开口122与晶片130之间,晶片130与支撑结构120分别与重布线路结构160直接地连接。换句话说,晶片封装体100是由晶片封装阵列50切割而成,因此重布线路结构160、支撑结构120以及封胶150也被切割而形成于各晶片封装体100中。由于晶片封装阵列50的各晶片封装体100的外围区域配置有支撑结构120,因此,能改善晶片封装阵列50封装过程中发生的翘曲,并且能提升晶片封装阵列50的结构强度且降低其制程的生产成本,进而增加晶片封装体100的产量。除此之外,支撑结构120的配置也可以改善各晶片封装体100的整体结构强度。
请再参考图1F及图2F,具体而言,在本实施例中,晶片封装体100包括重布线路结构160、支撑结构120、晶片130以及封胶150。支撑结构120配置于重布线路结构160并具有开口122。晶片130配置于重布线路结构160并位于开口122中。封胶150位于开口122与晶片130之间,其中封胶150填充于开口122与晶片130之间,晶片130与支撑结构120分别与重布线路结构160直接地连接。其中晶片封装体100是由晶片封装阵列50(如图3C所绘示)切割而成,因此重布线路结构160、支撑结构120以及封胶150也被切割而形成于各晶片封装体100中。由于晶片封装体100的外围区域配置有支撑结构120,因此,能改善晶片封装体100的整体结构强度。
请参考图4A及图4B,本实施例的晶片封装体100A类似于图1F及图2F的晶片封装体100,两者之间主要差异在于封胶150A的配置。在切割晶片封装阵列50的步骤之前,移除封胶150的一部分以形成封胶150A进而使晶片130裸露。详细而言,在图2F的步骤之前,移除部分位于支撑结构120与晶片130上的封胶150,而保留位于支撑结构120与晶片130之间的封胶150A。本实施例的支撑结构120中远离重布线路结构160的一顶面124与晶片130远离重布线路结构160的一第一面132共面,即位于同一第二参考平面P2上。如此一来,晶片130可暴露于晶片封装体100A外以接触散热导体,进而使晶片封装体100A有更好的散热性。
请参考图5,本实施例的晶片封装体100B类似于图2F的晶片封装体100,两者之间主要差异例如在于本实施例的开口122具有一内面126,内面126具有至少一凹槽128,且封胶150充满凹槽128。如此一来,可通过封胶150充满在凹槽128中进而确保晶片封装体100B的整体结构强度。除此之外,在另一实施例中,可进一步移除部分封胶150,而使晶片130裸露,类似于图4A及图4B所绘示。
请参考图6,本实施例的晶片封装体100C类似于图2F的晶片封装体100,两者之间主要差异例如在于本实施例的开口122具有一内面126C,且内面126C朝向远离晶片130的方向倾斜,使得封胶150延伸至内面126C的上方。换句话说,由于内面126C的倾斜设计,可使得支撑结构120通过封胶150的延伸而覆盖,进而使支撑结构120与重布线路结构160更紧密连接而不易脱落。如此一来,可通过封胶150覆盖内面126C进而确保晶片封装体100C的整体结构强度。除此之外,在另一实施例中,可进一步移除部分封胶150,而使晶片130裸露,类似于图4A及图4B所绘示。
综上所述,在本发明的晶片封装制程中,由于晶片封装阵列的各晶片封装体的外围区域配置有支撑结构(此时加强支撑件会于单一个晶片封装体的侧面上暴露出来),因此,能改善封装过程中发生的翘曲,并且能提升晶片封装阵列的结构强度且降低其制程的生产成本,进而增加晶片封装体的产量。除此之外,支撑结构的配置也可以改善各晶片封装体的整体结构强度。
以上所述仅为本发明较佳实施例,然其并非用以限定本发明的范围,任何熟悉本项技术的人员,在不脱离本发明的精神和范围内,可在此基础上做进一步的改进和变化,因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。

Claims (10)

1.一种晶片封装制程,其特征在于,包括:
提供支撑结构及承载板,其中该支撑结构具有多个开口,该支撑结构配置于该承载板上;
在该承载板上配置多个晶片,其中该多个晶片分别位于该支撑结构的该多个开口中;
形成覆盖该支撑结构与该多个晶片的封胶,该支撑结构与该多个晶片位于该封胶与该承载板之间,该封胶填充于该多个开口与该多个晶片之间;
移除该承载板;以及
在该支撑结构上配置重布线路结构,其中该重布线路结构连接该多个晶片。
2.根据权利要求1所述的晶片封装制程,其特征在于,在移除该承载板的步骤中,该支撑结构、该多个晶片以及该封胶构成共平面。
3.根据权利要求1所述的晶片封装制程,其特征在于,于在该支撑结构上配置重布线路结构的步骤中,各该晶片包括至少一接垫,该重布线路结构直接地连接该接垫。
4.根据权利要求1所述的晶片封装制程,其特征在于,还包括:
移除该封胶的一部分,以使该多个晶片裸露。
5.根据权利要求1所述的晶片封装制程,其特征在于,还包括:
沿该多个开口彼此之间的多个切割线切割该支撑结构及该重布线路结构,以形成多个晶片封装体。
6.根据权利要求5所述的晶片封装制程,其特征在于,该支撑结构的一部分暴露于对应的该晶片封装体的侧面。
7.根据权利要求1所述的晶片封装制程,其特征在于,各该开口具有内面,该内面具有至少凹槽,且该封胶充满至少该凹槽。
8.根据权利要求1所述的晶片封装制程,其特征在于,各该开口具有内面,且该内面朝向远离该晶片的方向倾斜,使得该封胶延伸至该内面的上方。
9.根据权利要求1所述的晶片封装制程,其特征在于,在该承载板上配置多个晶片的步骤包括:
在该承载板上配置多个无源元件,其中该封胶完整地覆盖该多个无源元件。
10.根据权利要求1所述的晶片封装制程,其特征在于,该支撑结构为网状结构。
CN201710655919.8A 2016-08-29 2017-08-03 晶片封装制程 Active CN107301956B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662380960P 2016-08-29 2016-08-29
US62/380,960 2016-08-29
TW106115540 2017-05-11
TW106115540A TWI719205B (zh) 2016-08-29 2017-05-11 晶片封裝製程

Publications (2)

Publication Number Publication Date
CN107301956A true CN107301956A (zh) 2017-10-27
CN107301956B CN107301956B (zh) 2019-10-25

Family

ID=60134224

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710655919.8A Active CN107301956B (zh) 2016-08-29 2017-08-03 晶片封装制程

Country Status (2)

Country Link
US (1) US11081371B2 (zh)
CN (1) CN107301956B (zh)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110010505A (zh) * 2018-01-05 2019-07-12 群创光电股份有限公司 半导体组件的制作方法
US10504847B2 (en) 2017-11-09 2019-12-10 Shanghai Zhaoxin Semiconductor Co., Ltd. Chip package structure and chip package structure array
CN111081654A (zh) * 2019-11-25 2020-04-28 上海先方半导体有限公司 一种晶圆封装结构的封装方法及晶圆封装结构
US10756077B2 (en) 2017-11-09 2020-08-25 Shanghai Zhaoxin Semiconductor Co., Ltd. Chip packaging method
US11127604B2 (en) 2018-01-05 2021-09-21 Innolux Corporation Manufacturing method of semiconductor device

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101266934A (zh) * 2007-03-12 2008-09-17 英飞凌科技股份公司 制造多个半导体器件的方法和设备
CN101399248A (zh) * 2007-09-27 2009-04-01 新光电气工业株式会社 配线基板及其制造的方法
CN101834146A (zh) * 2009-03-13 2010-09-15 精材科技股份有限公司 电子元件封装体及其形成方法
CN102074514A (zh) * 2009-11-23 2011-05-25 三星半导体(中国)研究开发有限公司 封装件及其制造方法
CN102157401A (zh) * 2011-01-30 2011-08-17 南通富士通微电子股份有限公司 高密度系统级芯片封装方法
CN102214635A (zh) * 2011-05-27 2011-10-12 日月光半导体制造股份有限公司 半导体封装结构及其制作方法
CN103208431A (zh) * 2012-01-17 2013-07-17 南茂科技股份有限公司 半导体封装结构及其制作方法
CN105789173A (zh) * 2015-01-14 2016-07-20 钰桥半导体股份有限公司 整合中介层及双布线结构的线路板及其制作方法
CN105789058A (zh) * 2015-01-14 2016-07-20 钰桥半导体股份有限公司 中介层嵌置于加强层中的线路板及其制作方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8021930B2 (en) * 2009-08-12 2011-09-20 Stats Chippac, Ltd. Semiconductor device and method of forming dam material around periphery of die to reduce warpage
US9202769B2 (en) * 2009-11-25 2015-12-01 Stats Chippac, Ltd. Semiconductor device and method of forming thermal lid for balancing warpage and thermal management
US8884422B2 (en) * 2009-12-31 2014-11-11 Stmicroelectronics Pte Ltd. Flip-chip fan-out wafer level package for package-on-package applications, and method of manufacture
US10049964B2 (en) * 2012-03-23 2018-08-14 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units
US9048222B2 (en) * 2013-03-06 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating interconnect structure for package-on-package devices
KR101681360B1 (ko) * 2013-11-25 2016-11-30 삼성전기주식회사 전자부품 패키지의 제조방법
US9355997B2 (en) * 2014-03-12 2016-05-31 Invensas Corporation Integrated circuit assemblies with reinforcement frames, and methods of manufacture
US9595485B2 (en) * 2014-06-26 2017-03-14 Nxp Usa, Inc. Microelectronic packages having embedded sidewall substrates and methods for the producing thereof
US20160005679A1 (en) * 2014-07-02 2016-01-07 Nxp B.V. Exposed die quad flat no-leads (qfn) package
US9735130B2 (en) * 2014-08-29 2017-08-15 Taiwan Semiconductor Manufacturing Company, Ltd. Chip packages and methods of manufacture thereof
KR101830043B1 (ko) * 2014-09-18 2018-02-19 인텔 코포레이션 E-wlb 및 e-plb에 wlcsp 부품을 매립하는 방법

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101266934A (zh) * 2007-03-12 2008-09-17 英飞凌科技股份公司 制造多个半导体器件的方法和设备
CN101399248A (zh) * 2007-09-27 2009-04-01 新光电气工业株式会社 配线基板及其制造的方法
CN101834146A (zh) * 2009-03-13 2010-09-15 精材科技股份有限公司 电子元件封装体及其形成方法
CN102074514A (zh) * 2009-11-23 2011-05-25 三星半导体(中国)研究开发有限公司 封装件及其制造方法
CN102157401A (zh) * 2011-01-30 2011-08-17 南通富士通微电子股份有限公司 高密度系统级芯片封装方法
CN102214635A (zh) * 2011-05-27 2011-10-12 日月光半导体制造股份有限公司 半导体封装结构及其制作方法
CN103208431A (zh) * 2012-01-17 2013-07-17 南茂科技股份有限公司 半导体封装结构及其制作方法
CN105789173A (zh) * 2015-01-14 2016-07-20 钰桥半导体股份有限公司 整合中介层及双布线结构的线路板及其制作方法
CN105789058A (zh) * 2015-01-14 2016-07-20 钰桥半导体股份有限公司 中介层嵌置于加强层中的线路板及其制作方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10504847B2 (en) 2017-11-09 2019-12-10 Shanghai Zhaoxin Semiconductor Co., Ltd. Chip package structure and chip package structure array
US10756077B2 (en) 2017-11-09 2020-08-25 Shanghai Zhaoxin Semiconductor Co., Ltd. Chip packaging method
CN110010505A (zh) * 2018-01-05 2019-07-12 群创光电股份有限公司 半导体组件的制作方法
US11127604B2 (en) 2018-01-05 2021-09-21 Innolux Corporation Manufacturing method of semiconductor device
CN111081654A (zh) * 2019-11-25 2020-04-28 上海先方半导体有限公司 一种晶圆封装结构的封装方法及晶圆封装结构

Also Published As

Publication number Publication date
US20180061672A1 (en) 2018-03-01
CN107301956B (zh) 2019-10-25
US11081371B2 (en) 2021-08-03

Similar Documents

Publication Publication Date Title
CN107301956B (zh) 晶片封装制程
TWI423401B (zh) 在上側及下側具有暴露基底表面之半導體推疊封裝組件
TWI442520B (zh) 具有晶片尺寸型封裝及第二基底及在上側與下側包含暴露基底表面之半導體組件
US10734367B2 (en) Semiconductor package and method of fabricating the same
KR101581465B1 (ko) 반도체 장치 및 그 제조방법
US8183092B2 (en) Method of fabricating stacked semiconductor structure
US6841870B2 (en) Semiconductor device
TWI427754B (zh) 在鋸道上使用通孔晶粒之封裝中的封裝
KR101429344B1 (ko) 반도체 패키지 및 그 제조 방법
KR101538539B1 (ko) 반도체 디바이스 및 그 제조 방법
US20140124949A1 (en) Semiconductor device and method of manufacturing semiconductor device
TWI719205B (zh) 晶片封裝製程
US7977780B2 (en) Multi-layer package-on-package system
KR20060133496A (ko) 적층 칩 스케일 패키지를 구비한 모듈 및 그 제작 방법
US20090146285A1 (en) Fabrication method of semiconductor package
US11227848B2 (en) Chip package array, and chip package
CN101477956A (zh) 小片重新配置的封装结构及封装方法
US20140077387A1 (en) Semiconductor package and fabrication method thereof
US20070069355A1 (en) Package with barrier wall and method for manufacturing the same
CN112185903A (zh) 电子封装件及其制法
CN107464790A (zh) 晶片封装阵列以及晶片封装体
KR101096454B1 (ko) 반도체 패키지 및 그 제조방법
KR101142336B1 (ko) 반도체 칩 및 이를 이용한 스택 패키지
CN113345847B (zh) 芯片封装结构及其制作方法
KR20110078588A (ko) 웨이퍼 레벨 패키지의 제조방법

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: Room 301, 2537 Jinke Road, Zhangjiang High Tech Park, Pudong New Area, Shanghai 201203

Patentee after: Shanghai Zhaoxin Semiconductor Co.,Ltd.

Address before: Room 301, 2537 Jinke Road, Zhangjiang High Tech Park, Pudong New Area, Shanghai 201203

Patentee before: VIA ALLIANCE SEMICONDUCTOR Co.,Ltd.

CP01 Change in the name or title of a patent holder