CN101266934A - 制造多个半导体器件的方法和设备 - Google Patents

制造多个半导体器件的方法和设备 Download PDF

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CN101266934A
CN101266934A CNA2008100951552A CN200810095155A CN101266934A CN 101266934 A CN101266934 A CN 101266934A CN A2008100951552 A CNA2008100951552 A CN A2008100951552A CN 200810095155 A CN200810095155 A CN 200810095155A CN 101266934 A CN101266934 A CN 101266934A
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CN101266934B (zh
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B·-H·姜
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Infineon Technologies AG
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Infineon Technologies AG
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Abstract

本发明涉及制造多个半导体器件的方法和设备。一种方法，包括提供包括多个腔体的载体的步骤；在每个腔体内布置至少一个半导体元件；使用封装材料填充多个腔体；以及移除该载体。

Description

制造多个半导体器件的方法和设备
技术领域
本发明涉及制造多个半导体器件。
背景技术
封装，例如集成电路封装，是半导体器件制造的最后阶段。封装也可以提供从电路，例如IC(IC＝集成电路)或半导体元件到支撑体例如衬底或印刷电路板(PCB)的互连。而且，封装提供理想的机械保护，并且保护不受环境影响以确保器件的可靠性和性能。
发明内容
根据不同的实施例，方法包括：提供包括多个腔体的载体；在每个腔体内布置至少一个半导体元件；使用封装材料填充多个腔体；并且移除该载体。
附图说明
随后，将参照附图更加详细的解释实施例，其中：
图1A至1C示出了传统的半导体封装工艺；
图2A至2G示出了根据实施例的制造多个半导体器件的方法；
图3A至3M示出了根据形成TSLP的另一个实施例，制造多个半导体器件的方法；
图4示出了根据实施例制造多个半导体器件的设备的立体图；
图5A至5C示出了另一个实施例；
图6A至6C示出了由不同封装材料桥连接半导体器件的示意图；以及
图7至17描述了使用铜分离器托盘的另一个实施例。
具体实施方式
根据其它实施例，一种用于制造多个半导体器件的设备，可以包括第一高度，其包括多个腔体，每个腔体由侧壁确定，侧壁具有等于或大于第一高度的第二高度。
根据另一实施例，一种用于制造多个半导体器件的设备，可以包括第一高度，其包括多个腔体，每个腔体由具有第一高度的侧壁确定，其中侧壁的至少一部分具有低于第一高度的第二高度。
通常，集成半导体器件可以包括准备芯片步骤，在这个过程中切割晶片以得到单独的集成电路或芯片。准备芯片之后的步骤将随后参照示出制造半导体器件封装的传统工艺的图1进行描述。
该工艺包括芯片连接或键合步骤A，其中芯片102连接到在支撑体或载体结构106提供的芯片垫104，例如半导体器件的铜引线架上。铜引线框106上也提供接触垫108。该接触垫108提供与封装的电子端子的连接。下一个步骤是引线键合步骤B，其中在芯片104与接触垫108之间形成键合连接112，由此允许芯片104连接到外部。随后是封装步骤C，通常使用塑料模制，其提供用于物理和化学保护的半导体器件的封装的“主体”114。步骤C提到的模制也可以包括固化模制的封装。为了清楚起见，图1在各个步骤中仅示出一个芯片102。然而，在实际的封装工艺中，可以在引线架106上布置多个芯片。通常，这里所称的模块模制，与例如，在引线框带或引线框阵列上的芯片或半导体元件被封装在单个模制体中的多个芯片一致。更为具体地，为了制造多个半导体器件，常规方法需要向芯片键合机器提供引线框带。该芯片键合机器从晶片上提取芯片并将芯片连接到(参见步骤A)引导条(headrace strip)。在随后的步骤中芯片经历导线键合(参见步骤B)以及模制和固化(参见步骤C)。随后的步骤给出了封装的最终形式及外观，例如DTFS(DTFS＝去闪烁(Deflash)/微调(Trim)/形成(Form)/单个化(Singulation))，封装彼此不同。像标记和引线加工的工序使得产品具有识别性并提高可靠性。
图1的实例中，激光标记步骤D在步骤C之后，在模子(mold)114的外表面上设置识别标记、跟踪标记或区别标记116。除了激光标记还使用墨水标记。接下来，如步骤E中所示，制作有多个半导体器件的引线框106，其经历蚀刻以便移除引线框106。正如所看到的，通过移除引线框106，暴露出了芯片垫104和接触垫108的下表面104a和104b(如图1中所示)。之后，在步骤F中，在芯片垫104的暴露表面104a以及接触垫108的暴露表面108a上淀积金层124a和124b。在下一步骤G中模子114被倒置，并层压到叠置层或带126上，以备随后的切割或单个化。之后，例如通过切割模子114，在步骤H中单个化封装。图1中步骤H示出了切割后的情况，即，切割槽128a和128b延伸贯通模子114，但不贯通叠置带126。一旦如图1步骤H所示装配完，该封装的电路基本上准备好被使用。
然而，由于缺陷，装配的器件并不总能起作用。在生产过程中可发生多种问题，例如，与缺陷相关的晶片制造、或装配过程中芯片开裂、或引线键合连接欠佳或完全未连接。因此，半导体器件封装进一步通常经历目视检测、随后电子检测。更为具体地，步骤H中单体化之后，在步骤I中，例如通过照相机130进行可视检测。进一步，通过经由第一探针132a向芯片垫104施加激励信号，并通过接触垫108和第二探针132b接收响应信号，在步骤J中执行电子检测。通过外部检测电路估算响应，以确定被检测器件通过还是未通过测试。
步骤K中，被检查和测试的器件经历由UV灯134提供的UV辐射。该UV灯134辐照该叠置带126以移除相同形式的模子114，以便独立的单个化的半导体封装可通过在步骤L中向容器带或载体带138的各个凹穴136中载入它们而被封装。通过带装配半导体单元有利于在制造过程中，自动查找并在PCB上安装该半导体元件。
图1步骤C中描述的模制工艺通常模制整个引线框。结果，工艺流程需要步骤H中的切割工艺，例如，从芯片中切割出单个半导体器件封装。需要在步骤G中的层压工艺，因为层压的引线框带用于在步骤H中切割之后，支撑该单个的半导体封装。之后在步骤L带装配之前，需要步骤K中的UV辐射。
因此，考虑到工艺速度、工艺成本和工艺成品率，希望减少封装工艺的步骤数目。
实施例涉及一种封装半导体器件的方法，其不必为了得到多个封装的半导体器件而切割容纳有多个芯片的封装材料的模制模块。
现在参考图2，将描述根据一个实施例的用于制造多个半导体器件的方法。如图2A中所示，提供具有多个腔体202a至202c的载体200。尽管仅示出了三个腔体，但应注意到，通常可以提供两个或多于三个的腔体。可以以二维阵列腔体的形式提供腔体。该载体200包括底面部分200a，通过它多个侧壁部分200b朝上延伸以确定出腔体202a至202c。例如，侧壁部分200b可以通过传统生长工艺从底面部分200a生长。该载体200的底面部分200a可为铜引线框。该载体200也可以由铝、塑料、橡胶、纸卡片形成。该载体可以是柔性或刚性。
向腔体202a至202c内相应放置半导体元件204a至204c，如图2B所示。该半导体元件204a至204c可以通过胶或带附着到载体200的底面部分200a。另外，可以将半导体元件204a至204c电连接到导电部分。此外，虽然注意到图2中示出向各自腔体内提供单个半导体元件204a至204c，但是依据将形成的器件，也可以将多于一个的半导体元件204a至204c提供到一个或多个或全部的腔体内。
如图2C所示并由箭头210指示，容纳半导体元件204a至204c的多个邻近腔体202a至202c被填充有封装材料206，以便得到多个半导体器件。可以看出，封装材料被提供有第一高度hSC。该封装材料206可为传统模制材料，例如，聚合物，如树脂。通常模制材料被填充有SiO2以便根据半导体器件的CTE调整模制材料的热膨胀系数(CTE)。
如图2D所示，使用封装材料206填充腔体之后，并且固化之后，移除载体200以便获得各自分离的半导体器件208a至208c。上面描述的载体200可由可蚀刻材料制成，并且这种情况下，移除载体200可以包括蚀刻工艺。可选择地，该载体可以从填充的腔体剥离。用于移除载体200的技术与形成载体200的材料有关。进行模制材料的固体化与选择的材料有关，例如树脂通常通过热处理被固体化。
载体200可为由铜制成的刚性或柔性部件，例如铜柱、铝、塑料、橡胶、纸、卡片等。
橡胶类的载体200可以通过如图2E中所示的弯曲载体200而移除。通过如图2E中所示的弯曲柔性载体200的方式，各自的半导体器件208a至208c脱离载体200。在另外的封装工艺中可以再次使用该载体。
可以看到，该工艺不需要切割步骤。仅仅通过移除载体200，就可以分离封装的半导体器件。而且，省略切割可以避免封装的半导体器件上的机械应力，由此避免了封装的损坏。
如图2中所示，半导体元件204a至204c可以放置在载体200中，以至于填充了封装材料206且移除载体200之后，半导体元件204a至204c的一个表面212a、212b、212c(参见附图2D)暴露出来。这个表面可以承载各自的连接垫，用来允许电连接到半导体元件204a至204c。这样，半导体元件可以电连接到外部，例如通过键合引线或焊料凸起，将暴露表面上的接触垫连接到衬底或印刷电路板。
图2F示出了将半导体器件208a安装到衬底214上的实例。在暴露的表面212a上形成多个接触垫216a至216c。对应的垫218a至218c形成在衬底214上。这种布置允许通过在半导体器件的接触垫216a至216c与衬底的接触垫218a至218c之间提供的焊料球220a至220c，将半导体器件208a倒装键合到衬底214上。
图2G示出了将半导体器件208a安装到衬底214上的另一实例。在暴露的表面212a上形成多个接触垫216a和216b。接触垫218a和218b形成在衬底214上。半导体芯片208a放置在衬底214上并可以通过胶等固定。在半导体器件的接触垫216a和216b与衬底的接触垫218a和218b之间，提供各自的键合线222a和222b。
参考图3，将描述根据另一实施例的制造多个半导体器件的方法。这个实施例将以TSLP封装(薄小无引线封装)形式封装半导体芯片。
图3A中提供铜板300。该板也可由其它材料形成，例如Sn、Zn、Ni。如图3B所示，然后通过向铜板300上提供抗蚀剂层302，掩模该铜板300以用于选择性电镀。图案化该抗蚀剂层302以在铜板300上定义表面区域304a至304d，其将经过随后的电镀工艺而在表面区域304a至304d上生长金属凸起。之后，如图3c中所示，电镀生长可以构成芯片垫和接触垫的镍凸起306a至306d。该镍凸起306a至306d可生长为约50μm至约200μm的高度。完成镍凸起306a至306d之后，例如通过选择性刻蚀工艺移除抗蚀剂层，并如图3D所示在镍凸起306a至306d的顶表面上提供金层308a至308d。应该注意到，该凸起也可以为其它非镍的金属，只要凸起材料不同于该板300的材料即可。在随后的工艺步骤中，将相对于凸起306a至306d选择性蚀刻基板300。
之后，图3D中所示的结构经历用于确定腔体边界的进一步掩模步骤。正如可由图3E中看到的，提供并图案化另一抗蚀剂层310以在铜板300上限定表面区域312a至312c，其将经历随后的电镀工艺以生长确定边界的侧壁。图3E中所示的结构，经历电镀工艺而在铜板300上暴露的表面区域312a至312c上生长铜边界。于图3F中示出了电镀工艺之后形成有铜侧壁314a至314c的结构。铜侧壁314a至314c可以形成具有约100μm至约200μm的高度。正如将在随后详细描述的，图3G示出了图3F移除了抗蚀剂层310的结构，其限定了具有接收半导体元件用于封装的腔体316a和316b的载体。
图3A至3G示出了各自工艺步骤中结构的截面图。图3H示出了图3G中所示结构的顶视图。图3H中的线A-A′指示了图3A至3G截面图所选择的截面线。如所示，形成了多个腔体316a至316d，每一个包括芯片垫306b、306d、306f和306h以及接触垫306a、306c、306e和306g。每一个接触垫306a、306c、306e和306g可以包括多个(图3H中为三个)单垫部分。腔体316由具有外部壁部分318和多个内部壁部分320的铜侧壁314围绕，内部壁部分320限定的侧壁部分由两个或更多的腔体共用。如图3H中所示可以矩形栅格的形式布置腔体，并且侧壁可以构成矩形边界。可以如图H所示形成的载体，构成了随后步骤形成的封装的半导体器件的基础。
如图3I所示，将芯片322a和322b放入腔体316a和316b内。芯片322a和322b放置在芯片垫306b和306d上。该芯片可以胶粘或焊接到芯片垫306b和306d上，或通过其它方式固定。每一个芯片分别地包括一个或多个接触垫324a和324b。正如所示，芯片322a和322b布置在芯片垫306b和306d上以至于具有接触垫324a和324b的表面远离面向该铜板300。如图3J中所示，在腔体中设置芯片之后，芯片接触垫324a和324b通过键合引线326a和326b被导线键合到各自的垫306a和306c。
之后，如图3K中所示(参见箭头330)，向腔体316a和316b中填充封装材料328。该封装材料可为模制化合物，例如树脂，其可以包括用于根据Si调整CTE(热膨胀系数)的SiO2，Si可以是芯片322a和322b的主要组分。如图3L中所示，使用封装材料填充腔体之后，通过铜刻蚀工艺移除铜载体300、314，将多个半导体器件进行单个化为分离的半导体器件332a和332b。该蚀刻工艺相对于铜可以具有选择性，以便保留具有一个表面334a至334d的Ni凸起306，其目前暴露出来用于电连接。
图3M中示出了一个附加工艺，Ni凸起306的暴露表面334a至334d可以分别提供有金层336a至336d，以便提高接触特性。
图4示出了与图3H中所示相近的设备400的立体简化表示。该设备400可用于制造多个半导体器件并且也可表示为随后的“栅格分离器托盘”。该设备400包括以4×4阵列排布的16个腔体316，其中可以如前所述的方式接收半导体元件。示意性示出了填充有封装材料328的一个腔体。围绕腔体316的侧壁318(外部壁)和320(内部壁)全部具有相同的高度hB。填充到腔体中的封装材料328具有高度hSC，其基本上决定了生产的半导体器件的厚度。可以看到，在图4的实施例中，侧壁的高度hB高于高度hSC。侧壁的高度hB也可以等于高度hSC。
图4中示出的腔体316的数量、布局和几何形状仅仅是示例。可以选择其它的数量、布局和形式。图4中示出的布局可以生长在引线框上，例如通过电化学工艺，特别是电镀生长工艺。而且，可以使用铜刻蚀工艺或铜柱生长工艺。而且，载体和/或引线框可以由铜或其它可电镀生长的材料制成。
如上所述，通过移除栅格分离器托盘400的侧壁318、320，半导体器件自然地单个化。因此，不需要附加的例如切割的单个化步骤。
图5A示出了根据另一实施例，与图4相似的设备450的立体图。除了内部壁320的交叉部分460的设计外，设备450的基本结构与图4中的设备相同。可以看到，如附图标记460所示，在四个内部壁320交叉的周围的区域中，内部壁320的高度从高度hB降低到hCB，hCB小于半导体器件的高度hSC(参见图4)，所以公共壁320的至少一部分被降低。
为了制造多个半导体封装，用封装材料填充栅格分离器托盘450的腔体316(为了清楚起见，仅示出四个被填充的腔体)，以至于多个邻近的被填充的腔体316通过封装材料连接。尽管类似图4中封装材料328被填充至高度hSC，但是，由于交叉部分460具有低于hSC的高度，所以在被填充之后封装材料将连接邻近的腔体，如可以在图5A中示出的四个腔体的交叉部分处看到的。
图5B为图5A中示出的不具有被填充的腔体316的设备450的顶视图。图5B示出了腔体316的阵列，该阵列包括列方向布置的多个腔体和行方向布置的多个腔体。每个腔体包括具有hB高度的侧壁318、320，四个邻近腔体的交叉部分460除外，那里高度降低到如上所述的hCB。
在移除侧壁，即分离器450之后，多个半导体器件通过薄模子或封装材料桥480被保持在一起，因此移除侧壁之后该多个半导体器件没有完全单个化。图5C示出了四个半导体器件332a至332d如何通过封装材料的薄桥480被保持在一起的实例。
图6示出了移除使用不同结构桥的栅格分离器后，保持半导体器件的实例。得到桥的方法与图5中描述的类似，然而，邻近腔体的公共侧壁具有不同结构。
图6A为两个邻近半导体器件332a和332b的立体图，其通过封装材料桥500连接。图6A中示出的封装材料桥500，可以通过将邻近腔体之间的整个公共侧壁320(参见图4和5)的高度降低至高度hCB而得到，该高度hCB低于第一高度hB。因此，封装材料桥420的厚度近似由公式(hSC-hCB)给出。
图6B是两个邻近半导体器件332a和332b的立体图，其通过封装材料桥510连接。图6B中示出的封装材料桥510，可以通过将邻近腔体之间的公共侧壁320的第一部分的高度降低至高度hCB而得到。移除栅格分离器托盘的侧壁之后，邻近半导体器件332a、332b由穿孔方式的多个薄封装材料桥510保持。此外，该公共侧壁变形为具有低于高度hSC的第一量的一个或多个第一部分，以及低于高度hSC的第二量的一个或多个第二部分。因此，该邻近的半导体器件332a、332b由具有肋条的封装材料桥保持在一起。
图6C示出了三个邻近半导体器件332a至332c的顶视图，其通过封装材料桥520连接。如果在栅格分离器托盘的至少三个邻近腔体的公共侧壁320周围的预定区域，将至少三个邻近腔体的公共侧壁降低到第二高度hCB，那么图6C中示出的至少三个邻近半导体器件332a、332b、332c之间的封装材料桥530可以根据另一个实施例得到。
可以在例如铜引线框的引线框上预制栅格分离器托盘。栅格分离器托盘可以分开几千个芯片的封装单元，这取决于芯片的尺寸、晶片的尺寸以及铜引线框的尺寸。这些实施例，允许通过前述薄模子桥分离封装单元或半导体器件并且最终同时将它们保持在一起。
图7至17描述了另一个实施例。具体地说，图7至17描述了当参考图1中描述的传统工艺使用图5中铜分离器托盘450时的实施例的细节。
图7A示出了图5中预制在铜引线框300上的铜栅格分离器托盘450的部分截面图。铜栅格分离器托盘450中每个腔体具有根据图3描述的结构。图7A示出了具有定义腔体316的侧壁314的铜引线框300。引线框300上提供有Ni芯片垫306a和Ni接触垫306b。图7B示出了图7A中所示具有腔体316的完整铜栅格分离器托盘450的顶视图。
图8A示出了图7A中所示部分铜栅格分离器托盘450的截面图，具有固定(例如通过键合)到芯片垫306a的半导体元件322，例如芯片。该芯片322包括在芯片322表面上远离面向引线框300的接触垫324。图8B示出了完整铜栅格分离器托盘450的顶视图。
图9A示出了图8A中部分铜栅格分离器托盘450的截面图，具有连接到其芯片垫306a的半导体元件322，其具有用于连接到接触垫306b的键合引线326。图9B示出了完整铜栅格分离器托盘450的顶视图。键合线108可由金、铝或铜制成。
图10A示出了图9A所示的部分铜栅格分离器托盘450的截面图，具有通过注入模制或树脂分配而填充有封装材料328的腔体316。图10B示出了完整铜栅格分离器托盘450的顶视图，具有在四个邻近腔体之间的封装材料桥480。模制工艺不限于注入模制。也可以使用其它技术例如传输模制或压缩模制。图10C示出了注入模制机器的示意图。机器600包括用于分配各自封装材料流604的六个喷嘴602。机器600与栅格450彼此相对配置，以便喷嘴可以对准各自腔体316以向腔体316内提供材料605。
图11A示出了图10A中部分铜栅格分离器托盘450的截面图，具有例如应用激光标记工艺而提供有标记700的封装材料328。图11B示出了每个被填充的腔体均载有标记700的完整铜栅格分离器托盘450的顶视图。该标记可为半导体器件封装上的识别。
图12A示出了例如通过铜刻蚀工艺，移除图11A中所示的引线框300以及铜栅格分离器托盘450后，制造的多个半导体器件332中的一个器件的截面图。移除铜引线框300以暴露出Ni凸起306a和306b的表面334a和334b。图12B示出了蚀刻掉铜栅格分离器托盘的侧壁并通过薄模子桥480被保持在一起的多个半导体器件332的顶视图。图12C示出了蚀刻掉铜栅格分离器托盘的侧壁并由薄模子桥480保持在一起的多个半导体器件332的底视图。同样示出了Ni凸起306a和306b的暴露表面334a和334b。封装材料桥480可具有低于半导体封装332的高度hSC的厚度。
图13A示出了图12A中多个半导体器件332中的一个器件的截面图，在Ni凸起306a和306b的表面334a和334b上溅射有金层336a和336b。图13B示出了蚀刻掉铜栅格分离器托盘的侧壁并由薄模子桥480保持在一起的多个半导体器件332的顶视图。图13C示出了蚀刻掉铜栅格分离器托盘的侧壁并由薄模子桥480保持在一起的多个半导体器件332的底视图。同样示出了金层336a和336b。由模子桥480保持在一起的多个半导体器件332构成了半导体器件332的模块800。
为了进一步处理准备包括目视检测的半导体封装，将该模块800装配到金属环插槽板810上，如图14A和14B所示。金属环插槽板810包括多个金属矩形插槽8201至8206，以便接收多个模块8001至8006。可以看到，在金属环中布置模块8001至8006，以便暴露金层336a和336b。
图15A示出了与图1B中步骤I类似的方式，通过照相机130目视检测一个器件332，区别在于由于模子桥，叠置带不是必须的。图15B示出了在金属环插槽板810中的多个模块8001至8006，并且图15C示出了目视检测模块8001至8006中的多个半导体封装。
图16中示出了目视检测之后的电子测试步骤。图16A示出了与图1C中步骤J所示的相似的方式，使用两个探针132a和132b来电子测试一个器件332，仍不需要叠置带。图16B示出了在金属环插槽板810中的多个模块8001至8006，并且图16C示出了用于执行所需检测的检测设备830，并通过各自的线840a、840b连接到探针132a和132b，以便电子检测模块8001至8006中的多个半导体封装。大量半导体器件的电子检测需要快速且经济地完成。因此，检测设备830可以是用于大规模检测的自动检测系统。
图17中示出了制造半导体器件中最后带装配工艺。带装配是例如表面安装器件(SMD)，向带910的单个凹穴900内载入器件的封装器件工艺，图17A中示出了其的一部分。图17B示出了金属环插槽板810中的多个模块8001至8006，并且图17C示出了具有凹穴9001至900n的带910的长度。图17D示意地示出了从模块8001至8006中向带凹穴900内移动器件332。该单独的半导体器件332由拾取夹920从各自模块8001至8006上拾取。该拾取夹920以足以折断该模子桥的力量拾取各自器件332。将半导体器件332保持在一起的模子桥可以很薄，即它们的高度可为半导体器件332的高度hSC的5％至10％。最终，例如通过热或压力的方式，单个的半导体器件被密封在具有盖体带的带910中。之后载带910卷绕到滚筒上以方便传送及运输。
从上面参考图7至17的讨论中可以看到，可以省略步骤G、H和K，即图1中描述的传统制造工艺中必须的层压、切割、和UV辐照步骤。由于不需要对层压设备和切割及UV辐照设备进行投资，因此可以节省成本。同时，可以加快半导体器件封装的制造工序。而且，由于改进了最终的封装工艺，可以提高半导体器件封装的质量。例如，使用前面描述的方法，可以避免通过切割芯片引起的封装开裂或破碎。
该实施例可以同时分离并且最终保持多个半导体封装。根据该实施例，通过薄模子桥可以得到邻近半导体封装之间的连接。通过使用栅格分离器托盘可以得到薄模子桥。
该实施例可以进一步节约对层压、切割和/或UV辐照设备投资的需要。而且，该实施例允许加速半导体器件封装的生产工艺。而且，半导体封装的分离或单个化可以获得更高的质量和更好的完成。
虽然前面描述的实施例使用具有矩形腔体的栅格分隔器，但应理解腔体可以具有任意所需形式，例如由需封装的或其使用的元件所决定。腔体的形状可为多边形、椭圆形或圆形。本发明不限于使用铜作为侧壁材料。也可以使用相对于封装材料具有选择性蚀刻的任意材料。
虽然前面描述的实施例中在布置和接触半导体元件之前生长侧壁，但应理解也可以在引线框上布置和接触半导体元件之后形成侧壁。这种情况下，已经安装的元件也应例如通过抗蚀剂被掩蔽。
虽然已经结合特定优选模式描述了本发明，但应理解，本领域技术人员根据前面描述，可以明了很多替代方案、修正方案和变形方案。因此，意图涵盖落入权利要求包括范围内的所有替代方案、修正方案和变形方案。

Claims (41)

1、一种方法，包括：
提供包括多个腔体的载体；
在每个腔体内布置至少一个半导体元件；
使用封装材料填充多个腔体；以及
移除该载体。
2、权利要求1的方法，其中提供载体包括形成多个腔体。
3、权利要求2的方法，其中形成多个腔体包括生长侧壁材料。
4、权利要求3的方法，其中形成多个腔体包括从电镀工艺、沉积工艺和光刻工艺的组中选择的工艺。
5、权利要求1的方法，其中使用封装材料填充多个腔体包括填充该腔体以使得多个被填充的腔体通过封装材料连接。
6、权利要求5的方法，包括移除该载体之后，分离被填充的腔体。
7、权利要求5的方法，其中多个邻近的被填充的腔体通过封装材料连接。
8、权利要求5的方法，其中提供载体包括将侧壁材料选择地生长至第一高度和第二高度，该第二高度低于该第一高度。
9、权利要求8的方法，其中形成多个腔体包括从包括电镀工艺、沉积工艺和光刻工艺的组中选择的工艺。
10、权利要求5的方法，其中提供载体包括将侧壁材料生长至第一高度，并选择性地将该侧壁材料从该第一高度降低至第二高度。
11、权利要求5的方法，其中选择性地降低该侧壁材料包括从包括切割工艺、锻造工艺和刻蚀工艺的组中选择的工艺。
12、权利要求1的方法，其中移除该载体包括从包括刻蚀该载体、从被填充的腔体中剥离该载体、施加温度冲击和从该载体上折断该被填充的腔体的组中选择的工艺。
13、权利要求1的方法，其中该载体为刚性部件或柔性部件。
14、权利要求1的方法，其中该载体是由选自包括铜、铝、塑料、橡胶、纸和卡片的组中的材料形成的。
15、权利要求1的方法，进一步包括接触在每个腔体中都布置的至少一个半导体元件。
16、一种方法，包括：
提供包括多个腔体的载体；
在每个腔体内布置至少一个半导体元件；
使用封装材料填充多个腔体，以使得多个邻近的被填充的腔体通过封装材料连接；以及
移除该载体。
17、权利要求16的方法，进一步包括分离该被填充的腔体。
18、权利要求17的方法，其中提供载体包括将侧壁材料通过电镀工艺选择性地生长至第一高度和第二高度，该第二高度低于该第一高度。
19、权利要求17的方法，其中提供载体包括将侧壁材料生长至第一高度，并选择性地将该侧壁材料从该第一高度降低至第二高度。
20、权利要求17的方法，其中载体为由铜构成的刚性部件，并且其中移除载体包括刻蚀该载体。
21、权利要求17的方法，进一步包括接触在每个腔体内都布置的至少一个半导体元件。
22、一种用于制造包括第一高度的多个半导体器件的设备，该设备包括：
多个腔体，每个腔体由侧壁限定，该侧壁包括等于或大于该第一高度的第二高度。
23、一种制造多个半导体器件的设备，该设备包括：
多个腔体，每个腔体由包括第一高度的侧壁限定，其中该侧壁的至少一部分具有低于第一高度的第二高度。
24、权利要求23的设备，其中邻近的腔体通过公共侧壁被分隔。
25、权利要求24的设备，其中该公共侧壁的至少一部分具有第二高度。
26、权利要求25的设备，其中整个公共侧壁具有第二高度。
27、权利要求25的设备，其中公共侧壁的多个第一部分具有第二高度并在其间具有至少一个包括第一高度的第二部分。
28、权利要求24的设备，包括具有公共侧壁的至少三个邻近的腔体，其中在三个腔体的公共侧壁周围的预定区域中，侧壁的高度被降低至第二高度。
29、权利要求24的设备，其中每个腔体包括至少一个芯片垫。
30、权利要求29的设备，包括引线框，其中芯片垫由引线框支撑。
31、一种制造多个半导体器件的设备，该设备包括：
用于接收至少一个半导体元件的多个第一装置；以及
用在每个第一装置的周围限定具有第一高度的边界的第二装置，其中邻近于第一装置的公共边界的至少一部分具有低于第一高度的第二高度。
32、权利要求31的设备，其中整个公共边界具有第二高度。
33、权利要求31的设备，其中公共边界的多个第一部分具有第二高度，该公共边界的第二部分包括在第一部分之间布置的第一高度。
34、权利要求31的设备，包括至少三个第一装置，其中在该三个第一装置的公共边界周围的预定区域中，边界高度降低至第二高度。
35、权利要求31的设备，其中第一装置是由从包括铜、铝、塑料、橡胶、纸和卡片的组中选择的材料制成的。
36、权利要求31的设备，其中每个第一装置包括用于附着芯片的第三装置。
37、权利要求36的设备，其中第一装置包括支撑该第三装置的引线框。
38、一种制造多个半导体器件的设备，该设备包括：
腔体阵列，该阵列包括在列方向上布置的第一多个腔体，以及在行方向上布置的第二多个腔体，其中每个腔体包括侧壁，该侧壁包括第一高度，其中四个腔体的公共侧壁周围的四个腔体的侧壁的预定部分具有低于第一高度的第二高度。
39、权利要求38的设备，其中每个腔体包括至少一个芯片垫。
40、权利要求38的设备，包括支撑芯片垫的引线框。
41、权利要求40的设备，其中该引线框为铜引线框。
CN2008100951552A 2007-03-12 2008-03-12 制造多个半导体器件的方法和设备 Expired - Fee Related CN101266934B (zh)

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CN101916749A (zh) 2010-12-15
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