CN111092020B - 半导体器件封装件及其制造方法 - Google Patents

半导体器件封装件及其制造方法 Download PDF

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CN111092020B
CN111092020B CN201911003926.5A CN201911003926A CN111092020B CN 111092020 B CN111092020 B CN 111092020B CN 201911003926 A CN201911003926 A CN 201911003926A CN 111092020 B CN111092020 B CN 111092020B
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substrate
semiconductor device
cavity
device package
manufacturing
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CN111092020A (zh
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高永权
许埈荣
姜芸炳
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Samsung Electronics Co Ltd
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Abstract

一种用于制造半导体器件封装件的方法包括：将其上安装有半导体器件的衬底容纳在位于载体衬底的中心的腔中，所述载体衬底具有与所述腔的侧壁接触以形成所述侧壁的上表面并围绕所述腔的支撑部分，并且由透光材料形成；通过按压所述支撑部分和所述衬底的边缘区域来限定所述衬底的模制部分；以及对所述模制部分进行模制，以覆盖所述半导体器件。

Description

半导体器件封装件及其制造方法
相关申请的交叉引用
要求于2018年10月23日在韩国知识产权局提交的韩国专利申请No.10-2018-0126545的优先权，其公开内容以引用的方式全部合并于本文。
技术领域
本发明构思涉及半导体器件封装件及其制造方法。
背景技术
在制造半导体器件封装件的工艺中，为了保护安装在衬底上的半导体器件，通过模制工艺形成包封部分。在上述模制工艺中，夹具与衬底的表面接触以限定模制部分，并且液体的包封剂被注入到由夹具限定的模制部分中。通常，衬底受到与其接触的夹具的相对高的压力，这可能导致夹具区域中的衬底破裂。随着制造工艺的进步，衬底的厚度减小，这一问题更加严重。
发明内容
根据本发明构思的一个方面，一种用于制造半导体器件封装件的方法包括：将其上安装有半导体器件的衬底容纳在位于载体衬底的中心的腔中，所述载体衬底具有与所述腔的侧壁接触以形成所述侧壁的上表面并围绕所述腔的支撑部分，并且由透光材料形成；通过按压所述支撑部分和所述衬底的边缘区域来限定所述衬底的模制部分；以及对所述模制部分进行模制，以覆盖所述半导体器件。
根据本发明构思的一个方面，一种用于制造半导体器件封装件的方法包括：将其上安装有半导体器件的衬底容纳在位于载体衬底的中心的腔中，所述腔由沿着所述载体衬底的边缘突出的侧壁限定并且所述衬底容纳在所述腔中，所述载体衬底包括由透光材料形成的基体，所述侧壁的上表面形成与所述衬底的上表面基本平行的表面，并且所述侧壁的所述上表面的水平高度与所述衬底的水平高度相同或低于所述衬底的水平高度；通过使用限定要对所述衬底进行模制的区域的夹具，将所述侧壁的所述上表面和所述衬底的边缘区域按压成彼此共面，来限定所述衬底的模制部分；以及对所述模制部分进行模制，以覆盖所述半导体器件。
根据本发明构思的一个方面，一种半导体器件封装件包括：衬底，所述衬底的一个表面上安装有至少一个半导体器件；以及模制部分，所述模制部分设置在所述衬底的所述一个表面上以覆盖所述半导体器件，其中，所述衬底具有位于中心部分中的腔，与所述腔的侧壁接触以形成所述侧壁的上表面，具有围绕所述腔的支撑部分，并容纳在位于由透光材料形成的载体衬底的中心中的所述腔中，并且所述模制部分设置在将由夹具限定的区域中，所述夹具将与所述一个表面和所述支撑部分接触。
附图说明
根据随后结合附图进行的详细描述，将更清楚地理解本公开的以上和其他方面、特征以及其他优点，其中：
图1是示出了根据示例实施例的制造半导体器件封装件的方法的流程图；
图2至图7是示出了根据示例实施例的制造半导体器件封装件的方法的视图；
图8示出了示例实施例的比较示例；以及
图9至图12示出了根据示例实施例的在制造半导体器件封装件的方法中使用的载体衬底的各种修改。
具体实施方式
下文中，将参考附图详细描述本公开的示例实施例。
图1是示出了根据示例实施例的制造半导体器件封装件的方法的流程图，图2至图7是示出了根据示例实施例的制造半导体器件封装件的方法的视图。
参考图1，根据示例实施例的制造半导体器件封装件的方法包括：将衬底组件容纳在具有腔的载体衬底中(S100)；限定衬底组件的模制部分(S200)；对所容纳的衬底组件进行模制(S300)；以及将衬底组件与载体衬底分离(S400)。首先，可以执行将衬底组件200容纳在载体衬底100中的操作S100。图2示出了将衬底组件200容纳在载体衬底100中的工艺，图3示出了衬底组件200容纳在载体衬底100中。图4是沿着图3的线I-I'截取的视图。
根据示例实施例的载体衬底100附着有衬底组件200，以处理衬底组件200，特别地，载体衬底100用作在处理期间支撑衬底组件200的支撑件。例如，载体衬底100可以用于在模制工艺中支撑衬底组件200，在模制工艺中，使用模具来包封安装在衬底组件200的表面上的半导体芯片220。
通过在衬底210上安装或形成多个半导体芯片220来提供衬底组件200。衬底210可以是半导体晶片或印刷电路板(PCB)中的一种。然而，实施例不限于衬底210的这些示例，并且可以采用各种其他类型的衬底，只要它们能够在其上安装或形成半导体芯片220。同样，实施例不限于任何特定类型的半导体芯片220，只要这种类型的半导体芯片220能够安装或形成在衬底210上。
参考图4，衬底210可以具有其上安装有半导体芯片220的上表面211和附着到载体衬底100的下表面212。凸块230附着到下表面212。衬底组件200可以包括沿厚度方向穿过其内部的多个通路电极，并且安装在上表面211上的半导体芯片220和下表面212中的凸块230可以通过多个通路电极彼此电连接。衬底210的边缘区域213是在用于对安装在衬底210的表面上的半导体芯片220进行模制的模制工艺中夹具接触衬底210的区域。
在对安装在衬底组件200的表面上的半导体芯片220进行模制的模制工艺之前，衬底组件200附着到载体衬底100。这里，衬底组件200在执行模制工艺之前附着到载体衬底100，但是不必在紧接模制工艺之前的工艺中附着到载体衬底100。例如，衬底组件200可以在用于研磨衬底210以使得衬底组件200的厚度减小的较早的背研磨(back lap)工艺中附着到载体衬底100。衬底组件200可以通过设置在衬底210的下表面212上的粘合层G附着到载体衬底100。粘合层G可以通过将液体形式的粘合材料涂覆到腔120的底表面122上来形成，或者可以通过将膜形式的粘合材料附着到腔120的底表面122上来形成。粘合材料可以是可光降解的粘合剂，当光照射到其上时，其粘合力变弱。在示例实施例中，粘合层G可以通过涂覆可光降解的粘合剂来形成，当UV光照射到其上时，其粘合力变弱。因此，当UV光照射到粘合层G上时，粘合性变弱，因此衬底组件200可以从载体衬底100脱粘。
参考图2和图4，载体衬底100可以包括腔120和基体110，在腔120中，衬底组件200的衬底210容纳在载体衬底100的中心部分中，基体110具有围绕腔120的支撑部分113。
基体110具有第一表面111和与第一表面111相对的第二表面112，并且可以具有当从上方观察时为圆形的边缘115。如图3所示，边缘115可以具有圆形横截面130。基体110的第一表面111和第二表面112可以设置为平坦表面，并且第一表面111和第二表面112可以形成为基本上彼此平行。如图4所示，支撑部分113的高度H1可以布置成基本上等于衬底210和粘合层G的高度总和H2。
基体110可以由透光材料形成，并且可以由包含例如玻璃、熔融硅石和熔融石英中的至少一种的材料形成。因此，当衬底组件200通过可光降解的粘合材料附着到载体衬底100时，光照射穿过基体110的第二表面112，因此，衬底组件200可以从载体衬底100脱粘。
腔120设置在第一表面111的中心部分中，衬底组件200的衬底210容纳在腔120中。腔120的底表面122可以形成为具有平坦表面，并且第一表面111和第二表面112可以形成为基本上彼此平行。
腔120可以形成为具有足够的空间以容纳衬底210，并且可以设置为使得衬底210的侧表面214和腔120的侧壁121彼此隔开了隔离空间114。
形成侧壁121的上表面的支撑部分113可以设置在腔120周围。支撑部分113从侧壁121延伸以形成侧壁121的上表面，并且可以设置在基体110的第一表面111的一个区域中。支撑部分113的上表面可以设置为与衬底210的上表面211基本上共面。
这里，根据示例实施例，如图9所示，支撑部分113的高度H1可以设置为低于高度H3，其中，高度H3是衬底210'和粘合层G的高度之和。换句话说，支撑部分113可以设置为比衬底210'的上表面211'低W1。在此情况下，粘合层G的厚度W2设置为大于W1。鉴于此，当衬底210'的上表面211'在模制工艺中被夹具按压时，由于粘合层G的弹性，衬底210'的上表面211'和支撑部分113可以彼此共面。衬底210'的边缘区域213'是在用于对安装在衬底210'的表面上的半导体芯片220进行模制的模制工艺中夹具接触衬底210'的区域。
接下来，如图5所示，可以执行限定容纳在载体衬底100中的衬底组件200的模制部分的操作S200。
限定模制部分的操作可以是这样的操作：通过夹具300按压支撑部分113和衬底210的边缘区域213来限定在后续工艺中将对包封剂进行模制的区域。
支撑部分113是在对衬底组件200进行模制的模制工艺中(见图4)与夹具300直接接触的区域，并且可以防止衬底组件200在模制工艺中被夹具300损坏。对其上安装有半导体芯片的衬底组件执行使用包封剂对表面进行高压模制的模制工艺，以确保衬底组件上安装的半导体芯片的结构可靠性。在此情况下，如在图8的比较示例中，当在载体衬底1100中未形成腔时，对附着到载体衬底1100的第一表面1111的衬底组件1200执行模制工艺。夹具1300在载体衬底1100的上部升高和降低，并且与衬底1210接触，以限定要在衬底组件1200中模制的区域。此外，为了防止包封剂1400在高压模制期间在夹具1300与衬底1210之间泄漏，以预定压力P2按压衬底组件1200的衬底1210。因此，夹具1300按压衬底1210的抗冲击能力相对弱的边缘区域1213。在上述过程中，在衬底1210的边缘区域1213中出现裂纹CR。衬底1210的边缘区域1213是在将衬底组件200切割成单个元件的工艺中要去除的区域。然而，如果裂纹延伸到在切割工艺中不被去除的单个元件的区域中，则可能不完全地执行模制工艺。因此，可能出现模制失败和制造的单个元件的可靠性降低的问题。
另一方面，如图5所示，在示例实施例中，载体衬底100的支撑部分113在模制工艺中与夹具300接触，因此，夹具300所按压的压力P1可以分散到支撑部分133中。因此，与图8的比较示例相比，可以减小施加到衬底210的边缘区域213的压力。换句话说，支撑部分113由于夹具300的按压力与衬底210的上表面211共面，并且施加到衬底210的压力的一部分可以分散到载体衬底100中。
此外，载体衬底100的支撑部分113支撑夹具300的下部。鉴于此，可以防止夹具300降低了小于支撑部分113的高度H1的高度而按压衬底组件200的衬底210的情况。详细地，如果在研磨衬底210的背研磨工艺中衬底210的厚度发生偏差，则夹具300与衬底210之间的距离可能根据衬底210的区域而不均匀。如果衬底210的厚度出现偏差，并且衬底的厚度变得大于期望的厚度，则根据示例实施例的支撑部分113限制夹具300降低的高度。因此，可以防止夹具300对衬底210的过度按压。
因此，在示例实施例中，可以防止在衬底组件200的衬底210中发生破裂。此外，当衬底组件200通过可光降解的粘合材料附着到载体衬底100时，光(L)照射穿过载体衬底100，因此衬底组件200可以从载体衬底100脱粘。
接下来，如图6所示，可以执行形成衬底组件200的模制部分400以覆盖待模制区域215的模制操作S300。模制部分400可以通过在高压下注入包括环氧模塑化合物(EMC)的材料来形成。
接下来，如图7所示，可以执行将衬底组件200与载体衬底100分离的操作S400。关于衬底组件200的分离，光L通过载体衬底100照射到粘合层G上，因此粘合层G的粘合力变弱。因此，衬底组件200可以从载体衬底100脱粘。根据示例实施例，光L可以是UV光。
接下来，将参照图10至图12描述载体衬底的各种修改示例。图10至图12示出了图2的载体衬底的各种修改示例。由于图10至图12的载体衬底与前述实施例的载体衬底的不同之处仅在于腔的形状，因此以下描述主要针对载体衬底的腔的形状。
图10示出了腔2120的侧壁2121形成为在径向向外的方向上朝着载体衬底2100的边缘2115向下倾斜的示例。
如果用于将衬底组件附着到载体衬底的粘合材料的施加量超过所需量，则一部分粘合材料可能溢出到腔外部。如果在上述状态下执行模制工艺，则溢出到腔外部的粘合材料可能附着到夹具。如上所述的附着到夹具的粘合材料可能使得在模制另一载体衬底的工艺中在夹具和衬底相接触的表面中形成间隙。在此情况下，包封剂在模制工艺中通过间隙泄漏，因此可能发生模制失败。在示例实施例中，腔的侧壁形成为倾斜的。鉴于此，即使当粘合材料的涂覆量超过所需量时，也可以提供剩余粘合材料将被储存的空间。因此，可以避免粘合材料溢出到载体衬底的腔的外部的问题。
此外，对于图10的修改示例，如前所述，腔2120的侧壁2121形成为朝着载体衬底2100的基体的边缘2115在径向向外的方向上向下倾斜。因此，在照射以使衬底组件2200脱粘的光L1和L2中，光L2从衬底2210的边缘2115反射，并且可以通过腔2120的侧壁2121入射到腔2120中。因此，可以进一步改善照射用于脱粘的光的光降解效率。
图11的修改示例是载体衬底3100的腔3120的侧壁3121形成为在载体衬底3100的径向向内方向上向下倾斜的示例。
图12的修改示例是腔4120的侧壁4121具有台阶表面的示例，该台阶表面具有在径向向内的方向上向下延伸的台阶。即，侧壁4121可以设置为沿载体衬底100的径向向内的方向逐渐降低的阶梯形式。对于该示例实施例，侧壁4121形成为具有第一侧壁4121a和第二侧壁4121b。在此情况下，衬底组件4200的衬底4210可以设置为与第一侧壁4121a相邻，以从腔4120的底表面4122延伸以容纳在台阶区域中。
虽然上面已经示出并描述了示例实施例，但是对于本领域技术人员来说显而易见的是，在不脱离由所附权利要求限定的本公开的范围的情况下，可以进行修改和变化。

Claims (20)

1.一种用于制造半导体器件封装件的方法，所述方法包括：
将其上安装有半导体器件的衬底容纳在位于载体衬底的中心的腔中，所述载体衬底具有与所述腔的侧壁接触以形成所述侧壁的上表面并围绕所述腔的支撑部分，并且由透光材料形成；
通过按压所述支撑部分和所述衬底的边缘区域来限定所述衬底的模制部分；以及
对所述模制部分进行模制，以覆盖所述半导体器件。
2.根据权利要求1所述的用于制造半导体器件封装件的方法，其中，将其上安装有半导体器件的衬底容纳在位于载体衬底的中心的腔中包括：
将粘合层涂覆到所述腔的底表面；以及
利用所述粘合层将所述衬底附着到所述腔的所述底表面。
3.根据权利要求2所述的用于制造半导体器件封装件的方法，其中，附着所述衬底包括：
将所述支撑部分的高度设置为等于或高于所述衬底的高度与所述粘合层的高度之和。
4.根据权利要求1所述的用于制造半导体器件封装件的方法，其中，限定所述模制部分包括：
将所述支撑部分的上表面和所述衬底的所述边缘区域按压成彼此共面。
5.根据权利要求2所述的用于制造半导体器件封装件的方法，其中，所述衬底具有一个表面和与所述一个表面相对的另一表面，
所述一个表面通过所述粘合层附着到所述腔的底表面，并且
所述另一表面上安装有所述半导体器件。
6.根据权利要求2所述的用于制造半导体器件封装件的方法，所述方法还包括：在对所述模制部分进行模制之后，使所述衬底脱粘以与所述载体衬底分离。
7.根据权利要求6所述的用于制造半导体器件封装件的方法，其中，所述粘合层由可光降解的材料形成，并且
在所述脱粘中，光通过所述载体衬底照射到所述粘合层上。
8.根据权利要求5所述的用于制造半导体器件封装件的方法，其中，所述衬底的所述模制部分被限定在所述另一表面上。
9.根据权利要求1所述的用于制造半导体器件封装件的方法，其中，所述透光材料包括玻璃、熔融硅石和熔融石英中的至少一种。
10.根据权利要求1所述的用于制造半导体器件封装件的方法，其中，所述侧壁与所述衬底的侧表面间隔开。
11.根据权利要求1所述的用于制造半导体器件封装件的方法，其中，所述衬底是晶片和印刷电路板中的至少一种。
12.根据权利要求1所述的用于制造半导体器件封装件的方法，其中，所述侧壁具有在所述载体衬底的径向向外的方向上向下倾斜的表面。
13.根据权利要求1所述的用于制造半导体器件封装件的方法，其中，所述侧壁具有在所述载体衬底的径向向内的方向上向下倾斜的表面。
14.根据权利要求1所述的用于制造半导体器件封装件的方法，其中，所述侧壁具有台阶表面。
15.根据权利要求14所述的用于制造半导体器件封装件的方法，其中，所述侧壁具有在所述载体衬底的径向向内的方向上逐渐降低的阶梯形式的台阶部分，并且
所述衬底被容纳在从所述腔的底表面延伸并呈台阶状的区域中。
16.一种用于制造半导体器件封装件的方法，所述方法包括：
将其上安装有半导体器件的衬底容纳在位于载体衬底的中心的腔中，所述腔由沿着所述载体衬底的边缘突出的侧壁限定并且所述衬底容纳在所述腔中，所述载体衬底包括由透光材料形成的基体，所述侧壁的上表面与所述衬底的上表面基本平行，并且所述侧壁的所述上表面的水平高度与所述衬底的所述上表面的水平高度相同或低于所述衬底的所述上表面的水平高度；
通过使用限定要对所述衬底进行模制的区域的夹具，将所述侧壁的所述上表面和所述衬底的边缘区域按压成彼此共面，来限定所述衬底的模制部分；以及
对所述模制部分进行模制，以覆盖所述半导体器件。
17.根据权利要求16所述的用于制造半导体器件封装件的方法，其中，所述衬底的一个表面通过粘合层附着到所述腔，并且所述衬底的与所述一个表面相对的另一表面上安装有所述半导体器件。
18.根据权利要求17所述的用于制造半导体器件封装件的方法，其中，所述粘合层被涂覆到所述腔的底表面。
19.一种半导体器件封装件，所述半导体器件封装件包括：
衬底，所述衬底的一个表面上安装有至少一个半导体器件；以及
模制部分，所述模制部分设置在所述衬底的所述一个表面上以覆盖所述半导体器件，
其中，所述衬底具有位于中心部分中的腔，与所述腔的侧壁接触以形成所述侧壁的上表面，具有围绕所述腔的支撑部分，并容纳在位于由透光材料形成的载体衬底的中心中的腔中，并且
其中，所述模制部分设置在将由夹具限定的区域中，所述夹具将与所述一个表面和所述支撑部分接触。
20.根据权利要求19所述的半导体器件封装件，其中，所述支撑部分的水平高度与所述衬底的所述一个表面的水平高度相同或低于所述衬底的所述一个表面的水平高度。
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