CN111081654A - 一种晶圆封装结构的封装方法及晶圆封装结构 - Google Patents

一种晶圆封装结构的封装方法及晶圆封装结构 Download PDF

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CN111081654A
CN111081654A CN201911165206.9A CN201911165206A CN111081654A CN 111081654 A CN111081654 A CN 111081654A CN 201911165206 A CN201911165206 A CN 201911165206A CN 111081654 A CN111081654 A CN 111081654A
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wafer
package body
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金国庆
孙鹏
曹立强
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National Center for Advanced Packaging Co Ltd
Shanghai Xianfang Semiconductor Co Ltd
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Shanghai Xianfang Semiconductor Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561Batch processing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

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Abstract

本发明涉及芯片封装领域,具体涉及一种晶圆封装结构的封装方法及晶圆封装结构,封装方法包括以下步骤:将芯片贴装在临时载片上,并以其为载体塑封所述芯片,得到塑封体;解键合以从所述塑封体上除去所述临时载片;在塑封体上开设填充槽,并在填充槽内填充用于降低塑封体内应力的填充材料;在填充有填充材料的塑封体上进行重新布线制备再布线层,得到晶圆塑封结构。通过对拆键合后的塑封体进行机械切割,材料填充,从而从结构上减弱了芯片和塑封胶热膨胀系数之间的差额,进而从结构上降低了塑封晶圆的结构应力,减少了晶圆翘曲,矫正效果稳定。

Description

一种晶圆封装结构的封装方法及晶圆封装结构
技术领域
本发明涉及芯片封装领域,具体涉及一种晶圆封装结构的封装方法及晶圆封装结构。
背景技术
随着IC封装技术的发展,对芯片封装在轻、小、薄方面的要求也越来越高。晶圆扇出型封装作为先进封装中的一种重要类型,因其具有支持10nm以下工艺制程芯片、互连路径短、高集成度、超薄厚度、高可靠性、高散热能力等优势而被广泛应用。
扇出型封装的基本工序为:在临时载板上覆盖临时键合胶,安装芯片后进行注塑并固化,然后再移除临时载板和临时键合胶,最后覆盖介电层和再布线层。因为其封装后的颗粒不需要常规的载板,故可以实现较薄厚度的封装。但是由于塑封胶、硅及金属等材料的热膨胀系数的差别会使得晶圆在拆键合后发生翘曲,从而导致拆键合之后的后续制成(如切筋、成型等)的难度加大。
目前解决晶圆翘曲的主要方式是通过热机械矫正,即在加热条件下,通过刚性外力来对晶圆的翘曲进行矫正。但是由于结构和材料特性问题,采用热机械矫正的方法无法完全解决晶圆翘曲的问题,且翘曲矫正效果不稳定,当晶圆再次经过高温工艺时,翘曲容易反复。
发明内容
因此,本发明要解决的技术问题在于克服现有技术中的通过热机械矫正的方法无法完全解决晶圆翘曲的问题,且翘曲矫正效果不稳定的缺陷,从而提供一种晶圆封装结构的封装方法及晶圆封装结构。
为解决上述技术问题,本发明采用的技术方案为:
一种晶圆封装结构的封装方法,包括以下步骤:
将芯片贴装在临时载片上,并以其为载体塑封所述芯片,得到塑封体;
解键合以从所述塑封体上除去所述临时载片;
在塑封体上开设填充槽,并在填充槽内填充用于降低塑封体内应力的填充材料;
在填充有填充材料的塑封体上进行重新布线制备再布线层,得到晶圆塑封结构。
进一步的,所述填充材料为光敏性材料。
进一步的,所述填充材料为聚酰亚胺和聚对苯撑苯并二噁唑中的至少一种。
进一步的,所述填充槽的开口位于塑封体上的芯片所在的一侧。
进一步的,在制备重布线层后还包括在所述重布线层上植球的步骤。
进一步的,所述芯片至少有两块,在植球步骤后还包括对塑封体进行切割的步骤。
进一步的,沿所述填充槽的纵向对所述塑封体进行切割。
进一步的,切割宽度大于或等于所述填充槽的宽度,以去除所述填充材料。
一种晶圆封装结构,其按照上述所有方案中任一项所述的封装方法制备得到。
本发明技术方案,具有如下优点:
1.本发明提供的晶圆封装结构封装方法,通过对拆键合后的塑封体进行机械切割,材料填充,从而从结构上减弱了芯片和塑封胶热膨胀系数之间的差额,进而从结构上降低了塑封晶圆的结构应力,减少了晶圆翘曲,矫正效果稳定。
2.本发明提供的晶圆封装结构,通过采用能减少晶圆翘曲的方法进行制备,使得得到的晶圆封装结构更加平整,从而可以提高晶圆封装结构在后续成型加工中的成品率。
附图说明
为了更清楚地说明本发明具体实施方式或现有技术中的技术方案,下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施方式,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本发明实施例1中的晶圆封装结构的结构示意图;
图2是本发明实施例1中临时载片、热剥离膜以及芯片的装配示意图;
图3是本发明实施例1中临时载片、热剥离膜、芯片以及塑封胶的装配示意图;
图4是本发明实施例1中塑封体的结构示意图;
图5是本发明实施例1中填充完填充材料后的塑封体的结构示意图;
图6是本发明实施例1中塑封体、填料、再布线层以及焊球的装配示意图;
图7是本发明实施例1中的切割步骤的切割位置示意图;
图8是本发明实施例1中的多个晶圆塑封结构的结构示意图。
附图标记:
1、临时载片;2、热剥离膜;3、芯片;4、塑封胶;5、塑封体;6、填充材料;7、再布线层;8、焊球;9、切割刀片;10、晶圆封装结构。
具体实施方式
提供下述实施例是为了更好地进一步理解本发明,并不局限于所述最佳实施方式,不对本发明的内容和保护范围构成限制,任何人在本发明的启示下或是将本发明与其他现有技术的特征进行组合而得出的任何与本发明相同或相近似的产品,均落在本发明的保护范围之内。
实施例中未注明具体实验步骤或条件者,按照本领域内的文献所描述的常规实验步骤的操作或条件即可进行。所用试剂或仪器未注明生产厂商者,均为可以通过市购获得的常规试剂产品。
实施例1
如图1所示,本实施例涉及一种晶圆封装结构,包括芯片3、塑封胶4、再布线层7以及焊球8。
塑封胶4用于包裹芯片3,对芯片3进行塑封从而得到塑封体5,芯片3上具有有源层,再布线层7布设在塑封体5上,且再布线层7与芯片3的有源层抵接并电连通,焊球8设置在再布线层7上,焊球8与再布线层7电连接,焊球8用于供塑封体5与其他元器件电连接。
结合图2-8,晶圆封装结构10按照如下步骤制备而成:
S1、提供临时载片1,并在临时载片1上贴附热剥离膜2;
S2、将多块芯片3倒装贴附在热剥离膜2上,芯片3的有源层与热剥离膜2抵接;
S3、以临时载片1为载体,对芯片3注塑塑封胶4进行塑封并固化,得到塑封体5;
S4、对塑封体5以及临时载片1进行解键合以从塑封体5上去除临时载片1;
S5、在塑封体5的芯片3所在的一侧上开设填充槽,并在填充槽内填充填充材料6;
S6、对填充有填充材料6的塑封体5进行重新布线制备得到再布线层7;
S7、在再布线层7上进行植球,得到焊球8;
S8、利用切割刀片9对S7得到的塑封结构进行机械切割,切割方向为沿填充槽的纵向进行切割,切割的宽度与填充槽的宽度一致,以去除填充材料6并完成塑封晶圆单颗元件的分离,得到晶圆封装结构10。
其中,填充材料6为光敏性材料,在本实施例中,填充材料6为聚酰亚胺(PI),在其他实施例中,填充材料6也可以是聚对苯撑苯并二噁唑(PBO)或聚酰亚胺与聚对苯撑苯并二噁唑的混合料。
由于芯片3的有源层是设置在与热剥离膜2抵接的,故将填充槽开设在塑封体5的芯片3所在的一侧上,一方面,可以对芯片3进行保护,另一方面也可以方便后续重新布线或植球等步骤的操作。
在其他实施例中,切割宽度也可以设置为大于填充槽的宽度,切割宽度只需满足在切割时能将填充材料6进行去除即可。
本实施例涉及的晶圆封装结构,通过采用能减少晶圆翘曲的方法进行制备,使得得到的晶圆封装结构更加平整,从而可以提高晶圆封装结构在后续成型加工中的成品率。
显然,上述实施例仅仅是为清楚地说明所作的举例,而并非对实施方式的限定。对于所属领域的普通技术人员来说,在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本发明创造的保护范围之中。

Claims (9)

1.一种晶圆封装结构的封装方法,其特征在于,包括以下步骤:
将芯片(3)贴装在临时载片(1)上,并以其为载体塑封所述芯片(3),得到塑封体(5);
解键合以从所述塑封体(5)上除去所述临时载片(1);
在塑封体(5)上开设填充槽,并在填充槽内填充用于降低塑封体(5)内应力的填充材料(6);
在填充有填充材料(6)的塑封体(5)上进行重新布线制备再布线层(7),得到晶圆塑封结构。
2.根据权利要求1所述的封装方法,其特征在于,所述填充材料(6)为光敏性材料。
3.根据权利要求2所述的封装方法,其特征在于,所述填充材料(6)为聚酰亚胺和聚对苯撑苯并二噁唑中的至少一种。
4.根据权利要求1或2所述的封装方法,其特征在于,所述填充槽的开口位于塑封体(5)上的芯片(3)所在的一侧。
5.根据权利要求1-4中任一项所述的封装方法,其特征在于,在制备重布线层后还包括在所述重布线层上植球的步骤。
6.根据权利要求5所述的封装方法,其特征在于,所述芯片(3)至少有两块,在植球步骤后还包括对塑封体(5)进行切割的步骤。
7.根据权利要求6所述的封装方法,其特征在于,沿所述填充槽的纵向对所述塑封体(5)进行切割。
8.根据权利要求7所述的封装方法,其特征在于,切割宽度大于或等于所述填充槽的宽度,以去除所述填充材料(6)。
9.一种晶圆封装结构,其特征在于,其按照权利要求1-8中任一项所述的封装方法制备得到。
CN201911165206.9A 2019-11-25 2019-11-25 一种晶圆封装结构的封装方法及晶圆封装结构 Pending CN111081654A (zh)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140217597A1 (en) * 2013-02-05 2014-08-07 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Stress Relieving Vias for Improved Fan-Out WLCSP Package
CN105355569A (zh) * 2015-11-05 2016-02-24 南通富士通微电子股份有限公司 封装方法
CN107301956A (zh) * 2016-08-29 2017-10-27 上海兆芯集成电路有限公司 晶片封装制程
CN110010505A (zh) * 2018-01-05 2019-07-12 群创光电股份有限公司 半导体组件的制作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140217597A1 (en) * 2013-02-05 2014-08-07 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Stress Relieving Vias for Improved Fan-Out WLCSP Package
CN105355569A (zh) * 2015-11-05 2016-02-24 南通富士通微电子股份有限公司 封装方法
CN107301956A (zh) * 2016-08-29 2017-10-27 上海兆芯集成电路有限公司 晶片封装制程
CN110010505A (zh) * 2018-01-05 2019-07-12 群创光电股份有限公司 半导体组件的制作方法

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