JP5623080B2 - チップ実装 - Google Patents

チップ実装 Download PDF

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Publication number
JP5623080B2
JP5623080B2 JP2009540834A JP2009540834A JP5623080B2 JP 5623080 B2 JP5623080 B2 JP 5623080B2 JP 2009540834 A JP2009540834 A JP 2009540834A JP 2009540834 A JP2009540834 A JP 2009540834A JP 5623080 B2 JP5623080 B2 JP 5623080B2
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Japan
Prior art keywords
solder
chip
buffer layers
buffer
layer
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Expired - Fee Related
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Japanese (ja)
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JP2010514148A (ja
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サイモン、ジョナサン、ステイシー
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ケンブリッジシリコン ラジオ リミテッド
ケンブリッジ シリコン ラジオ リミテッド
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
JP2009540834A 2006-12-13 2007-11-26 チップ実装 Expired - Fee Related JP5623080B2 (ja)

Applications Claiming Priority (3)

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GB0624888A GB2444775B (en) 2006-12-13 2006-12-13 Chip mounting
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JP2010514148A (ja) 2010-04-30
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US9177885B2 (en) 2015-11-03
US20100013093A1 (en) 2010-01-21
WO2008071905B1 (en) 2008-08-21
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US20160086907A1 (en) 2016-03-24
JP2014112694A (ja) 2014-06-19
US9659894B2 (en) 2017-05-23
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GB2444775A (en) 2008-06-18
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