TWI237858B - Electrical device with elastic bumps and method for forming the elastic bumps - Google Patents

Electrical device with elastic bumps and method for forming the elastic bumps Download PDF

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Publication number
TWI237858B
TWI237858B TW091105393A TW91105393A TWI237858B TW I237858 B TWI237858 B TW I237858B TW 091105393 A TW091105393 A TW 091105393A TW 91105393 A TW91105393 A TW 91105393A TW I237858 B TWI237858 B TW I237858B
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Taiwan
Prior art keywords
elastic
item
scope
conductive material
electronic device
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TW091105393A
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Chinese (zh)
Inventor
John Liu
Yau-Rung Li
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Chipmos Technologies Inc
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Publication of TWI237858B publication Critical patent/TWI237858B/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods

Abstract

An electrical device with elastic bumps and a method for forming the elastic bumps are provided. The electrical device comprises a plurality of elastic bumps formed on contact pads of a substrate. Each elastic bump includes an electrically insulated elastic body and conductive material(s). The elastic body has at least one through hole connecting to the corresponding contact pad. The conductive material is filled in the through hole and extended to top of the elastic body. Thus, the elastic bumps enable absorb the stress on mounting interface of the electrical device and improve outer electrical connection of electrical device.

Description

1237858 五、發明說明(1) 【發明領域】 本發明係有關於一種具彈性凸塊之電子裝置及其彈性 凸塊之形成方法,特別係有關於一種具有彈性凸塊之晶片 尺寸封裝結構,以減少填充材之填充〔under f i 1 1 ing〕步 驟。 【先前技術】 習知電子裝置之電性連接方式係有外引腳插合、外引 腳焊接及凸塊表面接合等,其中以凸塊表面接合具有較小 之結合面積與較高之端子密度分佈,特別適用於微小化與 咼密度化之晶片尺寸封裝〔Ch i p Sea 1 e Package〕,其係 - 在晶片之接合表面形成呈矩陣排列之金屬凸塊,以供電性舞 連接。1237858 V. Description of the Invention (1) [Field of the Invention] The present invention relates to an electronic device with elastic bumps and a method for forming the elastic bumps, and particularly relates to a chip size package structure with elastic bumps. Reduce the filling [under fi 1 1 ing] step. [Prior art] The conventional electrical connection methods of electronic devices include external pin mating, external pin soldering, and bump surface bonding. Among them, bump surface bonding has a smaller bonding area and a higher terminal density. The distribution is particularly suitable for miniaturized and chirped chip size packages [Ch ip Sea 1 e Package], which is-forming metal bumps arranged in a matrix on the bonding surface of the wafer to connect them with power supply.

當晶片翻轉以其金屬凸塊結合至一外部印刷電路板, 由於半導體之晶片與印刷電路板具有相當差異之熱膨脹係 數〔CTE〕 ’導致在晶片與印刷電路板之接合界面產生熱 應力’金屬凸塊易於機械性熱疲勞〔therma 1 fatigue〕,故通常在晶片與印刷電路板結合後,兩者之 間填充一填充材、〔underfiHing material〕,以吸收熱 應力’一種習知之填充材填充方法請參考美國專利第 710, 071號’然而習知填充材之填充方法係在溫度昇高 與毛細作用〔capi i lari ty〕下,使填充材自然流入晶片 與印刷電路板之間,此一填充材填充過程需要足夠之流動 時間與準確的均溫控制,故生產效率將受影響地降低。 在美國專利第6, 075, 290號中,揭示一種不需要填充When the wafer is flipped and bonded to an external printed circuit board with its metal bumps, the thermal expansion coefficient [CTE] of the semiconductor wafer and the printed circuit board is quite different, which results in thermal stress at the bonding interface between the wafer and the printed circuit board. The block is prone to mechanical thermal fatigue [therma 1 fatigue], so usually after the wafer and the printed circuit board are combined, a filler material and an [underfiHing material] are filled between the two to absorb thermal stress. Reference is made to U.S. Patent No. 710, 071 'However, the conventional filling method of filling material is to allow the filling material to naturally flow between the wafer and the printed circuit board under a temperature rise and capillarity. The filling process requires sufficient flow time and accurate temperature control, so production efficiency will be affected. In U.S. Patent No. 6,075,290, a method is disclosed that does not require filling

1237858 . --_______ 五、發明說明(2) 填充材之電子裝置,其係為一種積體電路封裝結構〔j c Package〕,其包含之晶片係具有鈍態保護層 〔passivation layer〕以及裸露於該鈍態防護層之導接 墊’在該鈍態保護層上形成有一彈性保護層〔resilien1: protective layer〕,彈性保護層在對應於導接墊處形成 開孔,並在開孔形成凸塊底座〔under bump pad〕,而金 屬凸塊即結合於該凸塊底座,如錫鉛合金〔tin—lead a 11 〇y〕,利用該屋胜保護層啄收晶片與外部印刷電路板 之間的熱應力,然而金屬凸塊本身之彈性並未提昇,產生 在金屬凸塊之熱應力仍有可能使金屬凸塊熱疲勞。 【發明目的及概要】 電絕緣性之 彈性塊具有 外部電路板 具有增進電 之次一目的 電絕緣性之 彈性塊具有 彈性凸塊利 力’達到減 之主要目的在於提供一 彈性塊作為 通孔,其填 具有非實質 子裝置之外 在於提供一 彈性塊作為 通孔,其填 用凸塊本身 少填充材填 之電子裝 而提供良 以供電性 良好之表 功效。 之電子裝 而提供良 以供電性 子裝置結 1ing 〕步 本發明 置,利用一 好之彈性, 導通,即使 面接合,故 本發明 置,利用一 好之彈性, 導通,該些 合界面之應 驟之功效。 種具彈性凸塊 凸塊之本體, 充有導電材, 平面亦能達到 部電性連接之 種具彈性凸塊 凸塊之本體, 充有導電材, 之彈性吸收電 充〔underf i 11237858. --_______ V. Description of the invention (2) The electronic device of the filling material is a integrated circuit package structure [jc Package], and the contained wafer has a passivation layer and is exposed on the substrate. The conductive pad of the passive protective layer has an elastic protective layer [resilien1: protective layer] formed on the passive protective layer. The elastic protective layer forms an opening corresponding to the conductive pad and forms a bump base in the opening. [Under bump pad], and a metal bump is bonded to the bump base, such as tin-lead alloy [tin-lead a 11 〇y], using the housing protection layer to pick up the heat between the chip and the external printed circuit board However, the elasticity of the metal bump itself has not been improved, and the thermal stress generated in the metal bump may still thermally fatigue the metal bump. [Objective and Summary of the Invention] An electrically insulating elastic block having an external circuit board having a second purpose to improve electrical insulation. An elastic block having an elastic bump has the advantage of reducing the main purpose of providing an elastic block as a through hole. Its filling with non-essential sub-devices is to provide an elastic block as a through hole. It fills the electronic device filled with the bump itself with less filling material to provide a table function with good power supply. The electronic device provides a good power-supplying sub-device junction.] According to the present invention, a good flexibility is used to conduct, even if the surfaces are joined, so the present invention uses a good elasticity, to conduct, the interface of these interfaces Effect. Kind of elastic bumps The body of the bumps, filled with conductive material, can also be electrically connected on the plane. Kinds of elastic bumps, the body of the bumps, filled with conductive materials, elastically absorbs the electricity [underf i 1

I 本發明之再— 性凸塊之方法,先 目的在於提供— 在基板上形成_ 種在電子裝置上形成彈 電絕緣性彈 1237858I Another method of the present invention is to provide a bump method, the first purpose of which is to provide a method for forming a substrate on an electronic device.

五、發明說明(3) 具有通孔之彈性塊,再填充導電材於通孔,以達 到大!製作在同一平面之多個彈性凸塊之功效。以達 H务,之另一目的在於提供一種晶片尺 在曰曰片之連接墊上形成有一彈性 ::構 =塊係覆蓋對應連接墊,彈性塊具=V. Description of the invention (3) An elastic block with a through hole, and then filled with a conductive material in the through hole, so as to be large! The effect of making multiple elastic bumps on the same plane. In order to achieve H service, another purpose is to provide a wafer ruler. An elasticity is formed on the connection pads of the film: structure = block covers the corresponding connection pad, and the elastic block has =

Πΐ:::導通,故該些彈性凸塊係能吸收電K 充材填充r Η 具有增進凸塊本身彈性,達到減少填 充材填充〔underfilling〕步驟之功效。 ^具 % 本發明之具彈性凸塊之電子裝4,其係包含有複數 ::性凸&,其係形成於基板之連接墊 :Πΐ ::: conduction, so these elastic bumps can absorb the electric K filling material filling r Η has the effect of improving the elasticity of the bump itself and reducing the effect of the filling step. ^ The electronic device 4 with elastic bumps of the present invention, which includes a plurality of :: sexual projections &, is a connection pad formed on a substrate:

:有;彈性塊及導電材,該彈性塊係為LI 物,:二彈對ΓΓ膠等高分子有機 少-通孔,、表Ϊ : ’彈性塊具有至 ^ ^ . k至對應連接墊,而導電材係填充於該通孔 f伸至该彈性塊之頂面,在該通孔内之導電材係為鎳、 ^ ;鈀錫鉛、銀膠或異方性導電膠等等,而在 忒弹性塊頂面之導電材係為鎳、金、銀、銅、鈀、 =或異方性導電膠’故本發明之具彈性凸塊之電子^置 =適用於晶片、晶圓、印刷電路板、陶究基板或薄膜等產 =本發明之在電子裝置上形成彈性凸塊之方法,其步 :以3:=共一基板,如晶圓、印刷電路板、㈣基板或 2 ’違基板之-表面具有複數個連接塾;以印刷、旋塗 艺,膜黏貼等方式形成—電絕緣性彈性層於該基板表面,: Yes; elastic block and conductive material, the elastic block is a LI object: two elastic pairs of polymer organic oligo-through holes such as ΓΓ glue, table Ϊ: 'the elastic block has to ^ ^. K to the corresponding connection pad, The conductive material is filled in the through hole f extending to the top surface of the elastic block. The conductive material in the through hole is nickel, ^; palladium tin lead, silver glue or anisotropic conductive glue, etc.导电 The conductive material on the top surface of the elastic block is nickel, gold, silver, copper, palladium, or anisotropic conductive glue. Therefore, the electronic device with elastic bumps of the present invention is suitable for wafers, wafers, and printed circuits. Production of boards, ceramic substrates or films = the method of forming elastic bumps on electronic devices of the present invention, the steps of which are: 3: = a common substrate, such as a wafer, a printed circuit board, a substrate or a 2 'substrate -The surface has a plurality of connection pads; formed by printing, spin-coating, film adhesion, etc.-an electrically insulating elastic layer on the surface of the substrate,

第7頁 1237858 五、發明說明(4) 以覆蓋該些連接墊;蝕刻該彈性 、^ 上之彈性塊,該些彈性塊並具有^小j形成設置於連接墊 對應連接墊;及利用深孔電鍍、^:通孔,其係連通至 成一導電材於該些通孔。 乇、,田填充或印刷等方式形 【發明詳細說明】 請參閱所附圖式’本發明將 依本發明之-具體實施例,如H下之貫施例說明: 塊之電子裝置係主要包含一基板广苐1圖所示’具彈性凸 板10之彈性凸塊20,該基板10係為K複:個結合:該基 〔wafer〕、印刷電路板〔PCB〕: ; C lp〕 圓 , 丨间尤I板〔ceram 1 c :薄膜’η⑴™〕,在本實施例中,該具 弹丨生凸塊之電子裝置係為一種晶片尺寸封結構〔 S^cale Package〕,故基板1〇 係為如DRAM、flash 或⑽R 等 纪憶體、微處裡器、微控制器或特殊應用積體電路之晶 片,在基板10之一表面11 〔即主動面active surface〕上 形成有連接墊12,如鋁墊〔A1 pad〕或銅墊〔Cu pad〕。 每一彈性凸塊2 0係形成於對應連接墊1 2上,彈性凸塊 20具有一電絕緣性彈性塊2!〔electrically insulated elastic body〕及導電材23〔conductive material〕, 該彈性塊2 1係為一種電絕緣性並具有高彈性之高分子有機 物〔organic polymer〕,如聚亞酿胺〔polyimide〕、笨 環丁稀〔benezo cyclobutene〕、聚丙稀酸脂 〔polyacrylates〕、橡膠〔rubber〕或矽膠 〔s i 1 i c ο n e〕,在本實施例中,該彈性塊2 1係呈半圓錐 feciPage 7 1237858 V. Description of the invention (4) Cover the connection pads; etch the elastic blocks on the elastic pads, and the elastic pads have a small j to form the corresponding connection pads provided on the connection pads; and use deep holes Plating, ^: through holes, which are connected to form a conductive material in the through holes.乇 ,, field filling or printing, etc. [Detailed description of the invention] Please refer to the attached drawings' The present invention will be based on the specific embodiments of the present invention, such as the description of the following embodiments: The electronic device of the block mainly contains A substrate is shown in FIG. 1 with an elastic bump 20 having an elastic convex plate 10. The substrate 10 is a K complex: a combination: the base [wafer], the printed circuit board [PCB]:; C lp] round,丨 You I board [ceram 1 c: thin film 'η⑴ ™]. In this embodiment, the electronic device with spring bumps is a wafer size package structure [S ^ cale Package], so the substrate 1 It is a chip such as DRAM, flash or ⑽R, such as memory, micro processor, microcontroller, or special application integrated circuit. A connection pad 12 is formed on one surface 11 of the substrate 10 (ie, active surface). , Such as aluminum pad [A1 pad] or copper pad [Cu pad]. Each of the elastic bumps 20 is formed on the corresponding connection pad 12. The elastic bump 20 has an electrically insulated elastic body 2! And a conductive material 23. The elastic block 2 1 It is an organic polymer with high electrical insulation and high elasticity, such as polyimide, benezo cyclobutene, polyacrylates, rubber or rubber. Silicone [si 1 ic ο ne], in this embodiment, the elastic block 21 is a semi-conical feci

mm

第8頁 1237858 五、發明說明(5) 狀,彈性塊21形成有一通孔22,其連通至連接墊丨2,以 導^材23之填充,而導電材23係填充於該通孔22並延伸^ 該彈性塊21之頂面,在通孔22之導電材23係為鎳〔η〕、 金〔Au〕銀〔Ag〕、銅〔Cu〕、I巴〔Pd〕、錫錯 〔SkPb alloy〕、銀膠〔silver gel〕或異方性導電膠 〔anisotropic conductive adhesive〕,必要時,可在 feci 該彈性塊21頂面形成另一導電材24,其係為含有鎳、金、 銀、銅、鈀或錫鉛之複合金屬層〔c〇mp〇site layers〕,或是鎳、金、銀、銅、鈀、錫鉛、銀膠或 性導電膠,依製程需要,在通孔22之導電材23與在該彈性 塊21頂面之導電材24係可為相同或不相同材質,由於彈性 塊2 1之良好彈性與呈細線狀之導電材23之良好可彎折性, 使付上述之彈性凸塊2 〇具有良好之勃性,故具有彈性凸塊 20之電子裝置係能表面接合至非完全平面之外部電路板, 也就是說,即使外部電路板存在著非實質平面之硬質表 面,如軟板或稱不規則水平之印刷電路板,該具有彈性凸 塊2 0之電子裝置亦能與其達到良好之電性結合,再者,在 電子裝置表面接合於外部電路板後,該些彈性凸塊2〇係能 吸收電子裝置結合界面之應力並具有增進凸塊之本身彈 性’達到減少填充材填充〔uncjer f i 1 1 i ng〕步驟之功效。 關於本發明之在電子裝置上形成彈性凸塊之方法 如下: 。 如第2a及3圖所示,提供一基板10,如晶圓、晶片、 印刷電路板、陶瓷基板或薄膜,在基板丨〇之表面丨丨形成有Page 8 1237858 V. Description of the invention (5), the elastic block 21 is formed with a through hole 22, which communicates with the connection pad 2 and is filled with the conductive material 23, and the conductive material 23 is filled in the through hole 22 and Extending ^ On the top surface of the elastic block 21, the conductive material 23 in the through hole 22 is nickel [η], gold [Au] silver [Ag], copper [Cu], Ibar [Pd], tin tin [SkPb alloy ], Silver gel or anisotropic conductive adhesive, if necessary, another conductive material 24 can be formed on the top surface of the elastic block 21, which contains nickel, gold, silver, and copper. , Palladium or tin-lead composite metal layer [c0mp〇site layers], or nickel, gold, silver, copper, palladium, tin-lead, silver paste or conductive paste, according to the needs of the process, conductive in the through hole 22 The material 23 and the conductive material 24 on the top surface of the elastic block 21 may be the same or different materials. Due to the good elasticity of the elastic block 21 and the good bendability of the thin linear conductive material 23, the above-mentioned The elastic bump 20 has good robustness, so the electronic device having the elastic bump 20 can be surface-bonded to a non-complete plane. That is, even if the external circuit board has a non-substantially flat hard surface, such as a flexible board or a printed circuit board with an irregular level, the electronic device with the elastic bump 20 can also achieve a good quality with it. The electrical bonding, and after the surface of the electronic device is bonded to the external circuit board, the elastic bumps 20 can absorb the stress of the bonding interface of the electronic device and have the flexibility of the bumps to increase the filling of the filling material [uncjer fi 1 1 i ng] step. The method of forming an elastic bump on an electronic device according to the present invention is as follows:. As shown in FIGS. 2a and 3, a substrate 10, such as a wafer, a wafer, a printed circuit board, a ceramic substrate, or a thin film, is provided on the surface of the substrate.

1237858 五、發明說明(6) " 複數個連接墊1 2,較佳地,該些連接墊丨2係呈格狀陣列, 或亦可呈直線或周邊排列。 之後,如第2b及4圖所示,以印刷〔printing〕、旋 塗〔spin coat ing〕或膠膜黏貼〔fi lm adhering〕技術 形成一電絕緣性彈性層2 5於該基板表面丨丨,其係覆蓋該些 連接墊12,必要地,在彈性層25形成之後,適當研磨該^ 板10之者面〔即上述表面11之對應表面〕,由於連接墊 已被彈性層2 5覆蓋,故可避免在研磨時對連接墊丨2之 染。 之後,如第2c及5圖所示,利用微影成像 〔Phenol i thograthy〕與乾/溼蝕刻技術,蝕刻該彈性層 25,形成設置於連接墊12上之彈性塊21,該些彈性塊21係 覆蓋對應連接墊12並形成有至少一通孔22,其係連通至對 應連接墊1 2。1237858 V. Description of the invention (6) " A plurality of connection pads 12, preferably, the connection pads 2 are in a grid-like array, or they may be arranged in a straight line or a periphery. After that, as shown in FIG. 2b and FIG. 4, an electrically insulating elastic layer 25 is formed on the surface of the substrate by printing, spin coating, or film adhering techniques. It covers the connection pads 12. Necessarily, after the elastic layer 25 is formed, the surface of the plate 10 (that is, the corresponding surface of the above-mentioned surface 11) is appropriately polished. Since the connection pads have been covered by the elastic layer 25, It can avoid staining the connection pads 2 during grinding. Afterwards, as shown in FIGS. 2c and 5, the elastic layer 25 is etched by using lithography [Phenol i thograthy] and dry / wet etching techniques to form elastic blocks 21 provided on the connection pads 12. The elastic blocks 21 The cover covers the corresponding connection pad 12 and is formed with at least one through hole 22, which is connected to the corresponding connection pad 12.

之後’如第2 d圖所示, 充之方法形成一導電材2 3於 材2 3係呈細線狀,故具有良 如第2 e圖所示,另以無電極 塊2 1之頂面形成一導電材2 4 後’切割該基板1 〇,以製得 裝置。 利用深孔電鏟、印刷或毛細填 上述通孔22,在通孔22之導電 好之韌性與延伸性,較佳地, 電鐘、印刷或沾黏方法在彈性 ,以增進焊接之結合性,最 多個上述具彈性凸塊20之電子 、时依本發明之具彈性凸塊之電子裝置,彈性塊並不局限 於單一通孔,如第6圖所示,在另一具體實施例中,具彈 ^凸塊之電子裝置係包含有一基板30及在基板30上之複數 1237858 五、發明說明(7) 個彈性凸塊4 0,在本實施例中,基板3 0係為印刷電路板, 具有形成於多層電路層之導接線路3 3與在上、下表面之防 焊層34〔solder resist layer〕,其中在一表面31之防 焊層34係顯露出連接墊32,而彈性凸塊40則形成於該些連 接墊3 2,每一彈性凸塊4 0具有電絕緣性之彈性塊4 1及導電 材4 3、44,該彈性塊41係呈圓柱狀並形成有複數個通孔 42,以填充形成複數個細線狀之導電材43,在彈性塊41之 頂面另形成有導電材4 4,以供表面接合,故彈性凸塊4 〇本 身即具備有良好之彈性,具有較佳之熱應力吸收力,且呈 有接合非實質平面之外部電路板之功效。 〃 故本發明之保護範圍當視後附之申請 者為準,任何熟知此項技藝者, 摩色圍内所作之任何變化與修改, 圍0 在不脫離本發明 均屬於本發明之 土丸淮,紅化劫i λ ^匕社心 . g % w丹r界疋 月之精神和 之保護範 1237858 圖式簡單說明 【圖式說明】 第 1 圖 :依 as 本 發 明 之 具 片 尺 寸 封 裝 結 構 第2a至2e 丨圖 ••依 03 本 發 明 之 在 方 法 1 在 形 成 該 截 面 示 意 圖 9 第 3 圖 :依 昭 本 發 明 之 在 方 法 5 所 提供 基 第 4 圖 :依 昭 / Ό 本發 明 之 在 方 法 , 具 有 彈 性 第 5 圖 :依 昭 本 發 明 之 在 方 法 5 具 有 彈 性 第 6 圖 :依 昭 本 發 明 之 具 具 彈 性 凸 塊 之 電 彈性凸塊之電子裝置,一晶 之截面示意圖; 電子裝置上形成彈性凸塊之 些彈性凸塊之過程中基板之 電子裝置上形成彈性凸塊之 板之正向不意圖, 電子裝置上形成彈性凸塊之 層之基板之正向示意圖; 電子裝置上形成彈性凸塊之 塊之基板之正向示意圖;及 彈性凸塊之電子裝置,另一 子裝置之截面示意圖。 [ 圖號 說 明 ] 10 基 板 11 表 面 12 連 接 墊 20 彈 性 凸 塊 21 彈 性 塊 22 通 孔 23 導 電 材 24 導 電 材 25 彈 性 層 30 基 板 31 表 面 32 連 接 墊 33 導 接 線 路 34 防 焊 層 40 彈 性 凸 塊 41 彈 性 塊 42 通 孔 43 導 電 材 44 導 電 材Afterwards, as shown in Fig. 2d, the method of forming a conductive material 2 3 and the material 2 3 are thin lines, so it has a good shape as shown in Fig. 2 e, and the top surface of the electrodeless block 21 is formed. A conductive material 24 is used to cut the substrate 10 to obtain a device. The deep-hole electric shovel, printing or capillary is used to fill the above-mentioned through-holes 22, and the conductive holes 22 have good toughness and extensibility. Preferably, the electric clock, printing or sticking method is elastic to improve the bonding of welding. For the most of the above-mentioned electronic device with elastic bumps 20, and the electronic device with elastic bumps according to the present invention, the elastic block is not limited to a single through hole. As shown in FIG. 6, in another specific embodiment, the The electronic device with elastic bumps includes a substrate 30 and a plurality of 1237858 on the substrate 30. V. Description of the invention (7) Elastic bumps 40. In this embodiment, the substrate 30 is a printed circuit board having The conductive lines 33 formed on the multilayer circuit layer and the solder resist layers 34 on the upper and lower surfaces, among which the solder resist layer 34 on one surface 31 exposes the connection pads 32, and the elastic bumps 40 Then, the connecting pads 32 are formed. Each of the elastic bumps 40 has an electrically insulating elastic block 41 and a conductive material 4 3 and 44. The elastic block 41 is cylindrical and is formed with a plurality of through holes 42. To form a plurality of thin linear conductive materials 43 on top of the elastic block 41 The other is formed with a conductive material 44, for surface engagement, so that the resilient bumps 4 square itself i.e. have good of elasticity, having preferably in thermal stress absorption, and showed an engaging effect external circuit board insubstantial plane. 〃 Therefore, the scope of protection of the present invention shall be subject to the applicants attached. Any changes and modifications made by anyone who is familiar with this technology, Mosewei, are within the scope of this invention without departing from the invention. , 红 化 劫 i λ ^ 社 社 社 心. G% w Dan rjie the spirit of the moon and the protection range 1237858 Schematic illustration [Schematic description] Figure 1: According to the present invention, the size of the package structure 2a to 2e 丨 Figure •• According to the present invention, the method 1 is formed in the cross-sectional schematic diagram 9 Figure 3: According to the present invention in the method 5 provided by the fourth figure: according to the present method of the present invention, Figure 5 with elasticity: Method 5 according to the invention according to the invention Figure 6: Elastic electronic device with elastic bumps according to the invention according to the invention, a schematic cross-sectional view of a crystal; elasticity is formed on the electronic device In the process of some elastic bumps of the bumps, the forward direction of the plate forming the elastic bumps on the electronic device of the substrate is not intended. Forward of the substrate layers schematic bumps; forward block schematic diagram of the substrate of elastomeric bumps formed on an electronic device; and an electronic device the resilient bumps, a cross-sectional schematic view of another sub-unit. [Illustration of drawing number] 10 substrate 11 surface 12 connection pad 20 elastic bump 21 elastic block 22 through hole 23 conductive material 24 conductive material 25 elastic layer 30 substrate 31 surface 32 connection pad 33 conductive line 34 solder resist layer 40 elastic bump 41 Elastic block 42 Through hole 43 Conductive material 44 Conductive material

Claims (1)

1237858 六、申請專利範圍 、一種具彈性凸塊之電子裝置,其包含: 一基板,其一表面具有複數個連接墊;及 複數個彈性凸塊,形成於該些連接墊,每一彈性凸塊 係具有一電絕緣性之彈性塊及導電材,該彈性塊形成有 至少一通孔,其連通至對應連接墊,而導電材係填充於 該通孔並延伸至該彈性塊之頂面。 、如申睛專利範圍第1項所述之具彈性凸塊之電子裝 置’其中該彈性塊係為高分子有機物。 、如申請專利範圍第1項所述之具彈性凸塊之電子裝1237858 6. Scope of patent application, an electronic device with elastic bumps, comprising: a substrate having a plurality of connection pads on one surface thereof; and a plurality of elastic bumps formed on the connection pads, each of the elastic bumps An elastic block and a conductive material having electrical insulation are formed in the elastic block. The elastic block is formed with at least one through hole that communicates with the corresponding connection pad. The conductive material is filled in the through hole and extends to the top surface of the elastic block. 2. The electronic device with elastic bumps as described in item 1 of the patent scope of Shenyan, wherein the elastic block is a polymer organic substance. Electronic equipment with elastic bumps as described in item 1 of the scope of patent application 置’其中該彈性塊係選自聚亞醯胺、苯環丁烯、聚丙烯 酸脂、橡膠及矽膠。 士申明專利範圍第1項所述之具彈性凸塊之電子裝 置’其中該些彈性塊係覆蓋對應之連接墊。 、如申請專利範圍第1項所述之具彈性凸塊之電子裝 f 〔、中ό亥基板係為晶片、晶圓、印刷電路板、陶瓷基 板或薄膜。 如申請專利範圍第1項所述之具彈性凸塊之電子裝 ,其中在該通孔内之導電材係為鎳、金、銀、鋼广 、錫鉛、銀膠或異方性導電膠。 置 銀 置Wherein the elastic block is selected from the group consisting of polyimide, phenylcyclobutene, polyacrylate, rubber, and silicone. The electronic device with elastic bumps described in Item 1 of the scope of the patent claims, wherein the elastic blocks cover the corresponding connection pads. The electronic device with elastic bumps as described in item 1 of the scope of the patent application. [, The substrate is a wafer, wafer, printed circuit board, ceramic substrate or film. According to the electronic device with elastic bumps described in item 1 of the scope of patent application, the conductive material in the through hole is nickel, gold, silver, steel, tin lead, silver glue or anisotropic conductive glue. Set silver 如申請專刊範圍第i項所述之具彈性凸塊之電子裝 ,其中在該彈性塊頂面之導電材係為含有鎳、金、 、銅、把或錫錯之複合金屬層。 如申請專利範㈣1帛所述之具彈性凸塊之電 ’其中在該彈性塊頂面之導電材係為鎳、金、銀凌The electronic device with elastic bumps as described in item i of the scope of the application, wherein the conductive material on the top surface of the elastic block is a composite metal layer containing nickel, gold, copper, copper or tin. Electricity with elastic bumps as described in the patent application ㈣1 帛, where the conductive material on the top surface of the elastic block is nickel, gold, silver 第13頁 1237858 六、申請專利範圍 銅、鈀、錫鉛、銀膠或異方性導電膠。 9、一種在電子裝置上形成彈性凸塊之方法,其步驟包 含: 提供一基板,其一表面具有複數個連接墊; 形成一電絕緣性彈性層於該基板表面,以覆蓋該些連 接墊; _ 鍅刻該彈性層,以形成設置於連接墊上之彈性塊,該 些彈性塊並形成有至少一通孔,其係連通至對應連接 墊;及 U 形成一導電材於該些通孔。 圖 1 〇、如申請專利範圍第9項所述之在電子裝置上形成彈 性凸塊之方法,其另包含之步驟有:形成一導電材於 該些彈性塊之頂面。 11、如申請專利範圍第9項所述之在電子裝置上形成彈 性凸塊之方法,其中形成該電絕緣性彈性層之方式係 為印刷、旋塗或膠膜黏貼。 1 2、如申請專利範圍第9項所述之在電子裝置上形成彈 性凸塊之方法,其中形成導電材之方式係為電鍍 刷。 1Page 13 1237858 6. Scope of patent application Copper, palladium, tin-lead, silver glue or anisotropic conductive glue. 9. A method for forming elastic bumps on an electronic device, comprising the steps of: providing a substrate having a plurality of connection pads on one surface; forming an electrically insulating elastic layer on the surface of the substrate to cover the connection pads; _ Engraving the elastic layer to form elastic blocks provided on the connection pads, the elastic blocks are formed with at least one through hole, which is connected to the corresponding connection pads; and U forms a conductive material in the through holes. Figure 10. The method for forming elastic bumps on an electronic device as described in item 9 of the scope of the patent application, further comprising the steps of: forming a conductive material on the top surfaces of the elastic blocks. 11. The method for forming an elastic bump on an electronic device as described in item 9 of the scope of the patent application, wherein the method of forming the electrically insulating elastic layer is printing, spin coating or adhesive film sticking. 1 2. The method of forming elastic bumps on an electronic device as described in item 9 of the scope of the patent application, wherein the method of forming the conductive material is an electroplating brush. 1 1 3、如申請專利範圍第9項所述之在電子裝置上形成彈 性凸塊之方法,其中所提供之基板係為晶圓、印刷電 路板、陶瓷基板或薄膜。 1 4、如申請專利範圍第9項所述之在電子裝置上形成彈 性凸塊之方法,在形成電絕緣性彈性層之後,另包 I237858 ^-__ 六、申請專利範圍1 3. The method for forming elastic bumps on an electronic device as described in item 9 of the scope of the patent application, wherein the substrate provided is a wafer, a printed circuit board, a ceramic substrate or a thin film. 1 4. The method for forming elastic bumps on an electronic device as described in item 9 of the scope of patent application, after forming the electrically insulating elastic layer, the additional package is I237858 ^ -__ 15 含:研磨該基板之另一表面。 、一種晶片尺寸封裝結構,其包含 一晶片,其主動表面係具有複數個連接墊;及 16 17 18 19 20 21 複數個彈性凸塊,形成於該些連接墊,每一彈性凸 塊係具有一電絕緣性之彈性塊及導電材,該彈性塊形 成有至少一通孔,其連通至對應連接墊,而導電材^ 填充於該通孔並延伸至該彈性塊之頂面。 “ 、如申請專利範圍第1 5項所述之晶片尺寸封裝結構 其中該彈性塊係為高分子有機物。 、如申請專利範圍第1 5項所述之晶片尺寸封裝結構 其中該彈性塊係選自聚亞醯胺、苯環丁烯、聚兩缚妒 脂、橡膠及矽膠。 久 、如申請專利範圍第丨5項所述之晶片尺寸封裝沾 其中該些彈性塊係覆蓋對應之連接墊。 、如申請專利範圍第1 5項所述之晶片尺寸封裝結 其中在該通孔内之導電材係為鎳、金、銀、鋼、、 錫雜、銀膠或異方性導電膠。 、如申請專利範圍第1 5項所述之晶片尺寸封裝結 其中在該彈性塊頂面之導電材係為含有鎳、金、 銅、鈀或錫鉛之複合金屬層。 1、 、如申請專利範圍第1 5項所述之晶片尺寸封裝結 其中在該彈性塊頂面之導電材係為鎳、金、銀、σ 紀、錫錯、銀膠或異方性導電膠。15 Includes: grinding the other surface of the substrate. A chip-size package structure comprising a chip having an active surface with a plurality of connection pads; and 16 17 18 19 20 21 a plurality of elastic bumps formed on the connection pads, each of which has a An electrically insulating elastic block and a conductive material. The elastic block is formed with at least one through hole that communicates with a corresponding connection pad, and a conductive material is filled in the through hole and extends to a top surface of the elastic block. “” The chip size package structure described in item 15 of the scope of patent application, wherein the elastic block is a polymer organic substance. The chip size package structure described in item 15 of the scope of patent application, wherein the elastic block is selected from Polyimide, phenylcyclobutene, polyisocyanate, rubber, and silicone. For a long time, the chip-size package described in item 5 of the patent application scope has these elastic blocks covering the corresponding connection pads. The chip size package according to item 15 of the scope of the patent application, wherein the conductive material in the through hole is nickel, gold, silver, steel, tin, silver glue or anisotropic conductive glue. The chip size package described in item 15 of the patent scope, wherein the conductive material on the top surface of the elastic block is a composite metal layer containing nickel, gold, copper, palladium, or tin-lead. The chip size package according to item 5, wherein the conductive material on the top surface of the elastic block is nickel, gold, silver, sigma, tin tin, silver glue or anisotropic conductive glue. 第15頁Page 15
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Publication number Priority date Publication date Assignee Title
US7595631B2 (en) 2006-06-09 2009-09-29 Visera Technologies Company Limited Wafer level assemble chip multi-site testing solution
US7885079B2 (en) 2006-08-18 2011-02-08 Industrial Technology Research Institute Flexible electronic assembly
US8215969B2 (en) 2008-03-27 2012-07-10 Taiwan Tft Lcd Association Contact structure and forming method thereof and connecting structure thereof
CN112180128A (en) * 2020-09-29 2021-01-05 西安微电子技术研究所 Interconnection substrate with elastic conductive micro-bumps and KGD socket based on interconnection substrate

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7595631B2 (en) 2006-06-09 2009-09-29 Visera Technologies Company Limited Wafer level assemble chip multi-site testing solution
US7915903B2 (en) 2006-06-09 2011-03-29 Visera Technologies Company Limited Batch-test method using a chip tray
US7885079B2 (en) 2006-08-18 2011-02-08 Industrial Technology Research Institute Flexible electronic assembly
US8215969B2 (en) 2008-03-27 2012-07-10 Taiwan Tft Lcd Association Contact structure and forming method thereof and connecting structure thereof
CN112180128A (en) * 2020-09-29 2021-01-05 西安微电子技术研究所 Interconnection substrate with elastic conductive micro-bumps and KGD socket based on interconnection substrate
CN112180128B (en) * 2020-09-29 2023-08-01 珠海天成先进半导体科技有限公司 Interconnection substrate with elastic conductive micro-bumps and KGD socket based on interconnection substrate

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