JP2000150557A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a manufacturing cost by connecting an external terminal to a plurality of electrode pads formed on a first main surface of a semiconductor chip, respectively, before a resin sealing film is formed on the first main surface, and allowing the end surface of the external terminal to be exposed from the resin sealing film. SOLUTION: Related to an IC 10, a protective film 12 formed of insulator is coated on a first main surface with an integrated circuit formed of a chip 11 where an integrated circuit comprising a semiconductor element is formed, while a plurality of electrodes pads 13 are formed at the protective film 12 while electrically connected to the integrated circuit. To each of electrode pads 13, an external terminal 14 formed of gold plating coat is connected mechanically and electrically, respectively. A resin sealing film 15 of potting resin is formed on the protective film 12, and the end surface of the external terminal 14 is exposed from the resin sealing film 15. Thus, a manufacturing cost is suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a technology for reducing the size of a package, and more particularly to a technology effective for use in a semiconductor integrated circuit device (hereinafter referred to as IC).

[0002]

2. Description of the Related Art As electronic devices using ICs have become smaller and thinner, there has been a demand for smaller IC packages. Therefore, a chip size package (Chi) having a size equal to or substantially equal to the size of a semiconductor chip (hereinafter, referred to as a chip) in which an integrated circuit including a semiconductor element is fabricated.
p Size Package or Chip Sca
le Package. Hereinafter, it is called CSP. ) Has been developed.

[0003] CSPs can be roughly divided into the following two types. In the first type of CSP, a printed wiring board and a film carrier are electrically and mechanically connected to a chip, and solder balls are protruded from the printed wiring board and the film carrier as external terminals. In the second type of CSP, bumps are protruded from electrode pads of a chip without using a printed wiring board, a film carrier, or the like, and the chip is resin-sealed with the bumps exposed.

[0004] As an example describing the CSP, a press release from Press Journal Inc., May 1995, "Monthly Se
Micon conductor World "P103-P1
There are 31. As an example describing the second type of CSP, "NIKKEIMICRODVICES"
There are April 1998 P164 to P167.

[0005]

However, in the first type of CSP, since a printed wiring board and a film carrier are used, the material cost and the manufacturing cost increase by that much, and the manufacturing cost becomes extremely high. There is a problem. Further, the second type CSP has a problem that a process of resin-sealing for each chip in a state where the bumps are exposed becomes special.

An object of the present invention is to provide a semiconductor device manufacturing technique capable of reducing the manufacturing cost.

[0007] The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0008]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, in a semiconductor device, external terminals are mechanically and electrically connected to a plurality of electrode pads formed on a first main surface of a semiconductor chip, respectively. A resin sealing film is formed, and an end face of the external terminal is exposed from the resin sealing film.

In the method of manufacturing a semiconductor device described above, an external terminal forming step of forming external terminals on a plurality of electrode pads of each chip portion in a state of a semiconductor wafer; A resin sealing film forming step in which a liquid resin is applied to the surface and the resin sealing film is formed so as to seal the external terminal group, and an end surface of the external terminal is exposed from the resin sealing film; A dicing step in which the semiconductor wafer is diced for each chip portion.

In the above-described semiconductor device, since the resin sealing film corresponding to the resin sealing body is formed on the first main surface of the semiconductor chip, the package has the same size as the semiconductor chip. In addition, since no printed wiring board or film carrier is used to form the resin sealing film and the external terminals, the manufacturing cost is reduced.

According to the method of manufacturing a semiconductor device described above,
External terminals can be formed without using a special process, and a resin sealing film corresponding to a resin sealing body can be formed without using a special process. Together with this, the manufacturing cost of the semiconductor device can be reduced.

[0013]

1A and 1B show a semiconductor device according to an embodiment of the present invention, wherein FIG. 1A is a front sectional view, and FIG.
Is a plan view. FIG. 2 is an explanatory view of each step showing a method for manufacturing a semiconductor device according to one embodiment of the present invention.

In this embodiment, a semiconductor device according to the present invention is an IC having a CSP (hereinafter referred to as a CSP IC).
That. ). As shown in FIG. 1, the CSP IC 10 includes a chip 11 in which an integrated circuit (not shown) including a semiconductor element is built.
The chip 11 is formed in a small square plate shape. A protection film 12 made of an insulator is applied to a main surface (hereinafter, referred to as a first main surface) of the chip 11 on the active area side on which the integrated circuit is formed.
Is formed with a plurality of electrode pads 13 electrically connected to the integrated circuit. Each electrode pad 13 has gold (A
u) The external terminals 14 formed by the plating film are mechanically and electrically connected. On the protective film 12, a resin sealing film 15 made of a potting resin is provided.
The external terminals 14 are formed so as to be resin-sealed.
A solder bump 16 is mechanically and electrically connected to each external terminal 14.

[0015] A CSP, which is an embodiment of the present invention, will now be described.
A method for manufacturing an IC will be described. By this explanation, C
Details of the configuration of the SP IC will be clarified.

First, in a so-called pre-process in an IC manufacturing method, as shown in FIG. 2A, an integrated circuit including a semiconductor element is formed on a wafer 20 in a section corresponding to a desired chip 11. It is formed for each chip portion 21. A protection film 12 made of an insulator such as a polyimide resin is provided on a first main surface of the wafer 20 on the active area side where the integrated circuit is formed, as shown in FIG.
As shown in (b), it is applied uniformly over the whole. An electrode pad 13 is provided on the protection film 12 for each chip portion 2.
A plurality of the light-emitting elements are arranged in an array with a predetermined interval and are exposed.

For convenience of illustration, the electrode pad 13 is 9
Although only the number is shown, in practice, a large number of 100 or more is provided. The same applies to the external terminals 14 formed on the electrode pads 13 and the corresponding solder bumps and lands.

On the wafer 20 on which the electrode pads 13 are formed at predetermined positions as described above, the adhesion metal film 22 and the power supply film 23 are formed as shown in FIG. The adhesion metal film 22 is formed of, for example, nickel (Ni), and is formed by electroless plating (electroless plating,
The thin film is uniformly and entirely applied on the protective film 12 and the electrode pads 13 by a chemical plating) process. The power supply film 23 is formed of copper (Cu), and is uniformly deposited to a predetermined thickness on the adhesion metal film 22 by electrolytic plating. At this time, since the adhesion metal film 22 is applied to the entire surface of the first main surface of the wafer 20, the power supply film 23 can be formed on the entire first main surface of the wafer 20 by electrolytic plating. The power supply film 23 may be formed by an electroless plating process.

Thereafter, an external terminal forming film 24 formed of a resist film on the first main surface of the wafer 20 is patterned by lithography as shown in FIG. 3B. That is, the external terminal forming film 24
A through hole 24a is formed at a portion corresponding to each of the electrode pads 13 so as to expose the electrode pad 13.

Next, Au is placed on the first main surface of the wafer 20.
3 is formed by electrolytic plating.
It is formed as shown in FIG. That is, by using the power supply film 23 as an electrode required for the electrolytic plating process, the external terminals 14 are respectively formed in the through holes 24a where the electrode pads 13 are exposed. At this time, since the surface of the power supply film 23 excluding the electrode pads 13 is covered with the external terminal formation film 24 formed of a resist film, an Au plating film is not formed.

Thereafter, the external terminal forming film 24 and the power feeding film 23 are formed.
When the contact metal film 22 is removed as shown in FIG. 3D, the external terminals 14 are respectively provided on the electrode pads 13 of the chip portions 21 on the first main surface of the wafer 20. It is in a formed state.

On the first main surface of the wafer 20 on which the external terminals 14 are formed as described above, a resin sealing film 15 for covering the external terminals 14 is formed by a spinner coating technique as shown in FIG. As shown in FIG. That is, the spin chuck 25 of the spinner coating device is used.
When the wafer 20 is held by vacuum suction with the first main surface side facing upward, the wafer 20 is rotated by the spin chuck 25. When a liquid resin 26 having an insulating property, such as a potting resin, is dropped onto the wafer 20 from the dripping nozzle 27 of the spinner coating device, the liquid resin 26 is diffused outward by centrifugal force. The surface of the liquid resin 26 is uniformly coated on the entire surface.

Thereafter, when the liquid resin 26 is thermally cured,
On the first main surface of the wafer 20, a resin sealing film 15 covering the group of external terminals 14 is attached as shown in FIG. 4B. In this state, the external terminals 14
The group is buried inside the resin sealing film 15.

The resin sealing film 15 thickly applied on the wafer 20 is polished by a polishing technique so that the external terminals 14 are exposed, as shown in FIG. That is, when the wafer 20 is held on the polishing table 28 of the polishing apparatus with the resin sealing film 15 side facing upward, the polishing tool 2
9 is rubbed against the resin sealing film 15 so that the resin sealing film 15 is polished. When the resin sealing film 15 is polished by a predetermined amount, the top of the external terminal 14 is also polished.
As shown in (b), the top surface of the external terminal 14 polished and flattened is exposed from the upper surface of the resin sealing film 15.

As shown in FIG. 6A, a solder ball 30 is provided on the first main surface of the wafer 20 where the external terminals 14 are exposed from the resin sealing film 15 as described above. The solder bumps 16 are supplied on the terminals 14 and soldered on the external terminals 14 as shown in FIG.

The wafer 20 on which the solder bumps 16 are formed as described above is placed in the chip 1 in the dicing process.
1 is diced as shown in FIG. That is, as shown in FIG. 7A, the wafer sheet 31 is adhered to the back surface of the wafer 20 and the wafer sheet 3
A wafer ring 32 is adhered to the outer peripheral portion of the wafer 1. In this state, as shown in FIG. 7B, the wafer 20 is diced by the dicer 33 for each chip portion 21. Since the external terminals 14, the resin sealing film 15 and the solder bumps 16 have already been formed in the state of the wafer 20, the CSP / IC 10 shown in FIG. Become.

CSP / IC manufactured as described above
10 is mounted on the mounting board as shown in FIG. That is, the mounting substrate 40 shown in FIG. 8 includes a main body 41 formed of an insulating substrate such as a glass-impregnated epoxy resin substrate or a ceramic substrate. A plurality of lands 42 are arranged on the upper surface of the main body 41 so as to correspond to the solder bumps 16 in the CSP / IC 10.

When the CSP / IC 10 is mounted on the mounting substrate 40, a flux (not shown) is applied to the lands 42 of the mounting substrate 40 in advance by a screen printing method or the like. Next, the CSP / IC 10
The solder bumps 16 are opposed to the mounting board 40 with the group side facing down, and the solder bumps 16 are respectively adhered to the lands 42 by flux and temporarily fixed.

In this state, when the CSP / IC 10 is passed through the heating furnace together with the mounting substrate 40, the solder bumps 16 are provided between the external terminals 14 and the lands 42 by the solder bumps 16.
Is formed, and as shown in FIG.
The IC 10 is in a state of being reflow soldered to the mounting board 40. That is, the CSP IC 10 is flip-chip connected to the mounting substrate 40.

According to the above embodiment, the following effects can be obtained.

1) External terminals are formed by gold plating on a plurality of electrode pads formed on the first main surface of the chip, and a resin sealing film is formed on the first main surface. By exposing the upper surface of the external terminals by polishing the upper part of the package, the package can be configured to be the same size as the chip, and the printed wiring board and film carrier can be used to form the resin sealing film and the external terminals. Since it does not need to be used, manufacturing costs can be reduced.

2) By forming the solder bumps on the external terminals, the mounting can be performed on the mounting substrate by flip-chip connection, so that the mounting operation can be easily performed.

3) By forming the external terminals using the gold plating process, it is not necessary to use a special process, so that the manufacturing cost of the CSP / IC can be reduced.

4) A liquid resin is applied to the external terminal group side main surface of the wafer to form a resin sealing film so as to seal the external terminal group with the resin, and the surface layer of the resin sealing film is removed. By exposing the external terminals, it is not necessary to use a special process, so that the manufacturing cost of the CSP / IC can be reduced in combination with the above 3).

FIG. 9 shows a CSP according to another embodiment of the present invention.
-It is each enlarged partial front sectional view which shows the manufacturing method of IC,
(A) shows the state after the underfill film forming step, (b) shows the state after the resin sealing film forming step, and (c) shows the state after the dicing.

This embodiment is different from the above embodiment in that
The underfill film 17 is formed to protect the external terminals 14 before the resin sealing film is formed.

According to the present embodiment, since the external terminals 14 are protected by the underfill film 17, the external terminals 14 are protected.
Can increase the mechanical strength.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, a solder bump 18 may be formed on the external terminals as shown in FIG. The solder coating 18 can be formed very easily by a solder dipping method.

The external terminals are not limited to those made of Au, but may be made of a conductive material such as copper.

Further, the external terminals are not limited to being formed by the electrolytic plating method, but may be formed by using an electroless plating method or other thick film forming methods and thin film forming methods. In that case, a lift-off method can be used.

The bump is not limited to being formed by soldering.
It may be formed by using another conductive material such as copper or the like, and may be formed not only by supplying solder balls and projecting but also by plating.

[0043]

The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows.

By forming external terminals on a plurality of electrode pads formed on the first main surface of the semiconductor chip, forming a resin sealing film on the first main surface, and exposing the external terminals,
The package can be configured to have the same size as the chip, and the manufacturing cost can be suppressed because a printed wiring board and a film carrier are not required to form the resin sealing film and the external terminals.

[Brief description of the drawings]

FIGS. 1A and 1B show a semiconductor device according to an embodiment of the present invention, wherein FIG. 1A is a front sectional view and FIG. 1B is a plan view.

FIGS. 2A and 2B show an electrode pad forming step in a method of manufacturing a semiconductor device according to an embodiment of the present invention, wherein FIG. 2A is a plan view and FIG.

3A and 3B are enlarged partial front cross-sectional views showing an external terminal forming step, wherein FIG. 3A is a metal film forming step, FIG. 3B is an external terminal forming film forming step, FIG. 3C is an external terminal forming step, d) shows a film removal step, respectively.

4A and 4B show a resin sealing film forming step, wherein FIG. 4A is a front view, and FIG. 4B is an enlarged partial front sectional view.

5A and 5B show a resin sealing film polishing step, wherein FIG. 5A is a front view, and FIG. 5B is an enlarged partial front sectional view.

6A and 6B show a solder bump forming step, in which FIG. 6A is an enlarged partial front sectional view showing a solder ball supplying operation, and FIG. 6C is an enlarged partial front sectional view showing a state after the solder bump forming step.

FIG. 7 shows a wafer dicing step, and FIG.
Is a plan view, and (b) is a front sectional view.

FIG. 8 is a partially cutaway front view showing a mounted state of the CSP IC.

FIGS. 9A and 9B are enlarged partial front sectional views showing a method of manufacturing a CSP / IC according to another embodiment of the present invention, wherein FIG. 9A shows an underfill film forming step, and FIG. After the step, (c) shows the state after dicing.

FIG. 10 shows a CSP I according to another embodiment of the present invention.
It is each enlarged partial front sectional view which shows the manufacturing method of C,
(A) shows the state after the formation of the solder film, and (b) shows the state after the dicing.

[Explanation of symbols]

10: CSP / IC (semiconductor device), 11: chip, 1
2 ... Protective film, 13 ... Electrode pad, 14 ... External terminal, 15
... resin sealing film, 16 ... solder bump, 17 ... underfill film, 18 ... solder coating, 20 ... wafer, 21 ... chip part,
22: adhesion metal film, 23: power supply film, 24: external terminal formation film, 24a: through hole, 25: spin chuck, 2
6 liquid resin, 27 dripping nozzle, 28 polishing table, 29
... polishing tool, 30 ... solder ball, 31 ... wafer sheet,
Reference numeral 32 denotes a wafer ring, 33 denotes a dicer, 40 denotes a mounting board, 41 denotes a main body, 42 denotes a land, and 43 denotes a soldering portion.

Claims (11)

[Claims] An external terminal is mechanically and electrically connected to a plurality of electrode pads formed on a first main surface of a semiconductor chip, and a resin sealing film is formed on the first main surface. And an end face of the external terminal is exposed from the resin sealing film. 2. The semiconductor device according to claim 1, wherein said external terminals are formed by plating. 3. The semiconductor device according to claim 2, wherein said external terminals are formed by gold plating. 4. The semiconductor device according to claim 1, wherein a solder bump is electrically and mechanically projected on said external terminal. 5. The semiconductor device according to claim 1, wherein a solder coating is formed on the external terminal. 6. The semiconductor device according to claim 1, wherein the external terminal is protected by an underfill film.
6. The semiconductor device according to 4 or 5. 7. The method of manufacturing a semiconductor device according to claim 1, wherein an external terminal is formed on each of a plurality of electrode pads of each chip portion in a state of a semiconductor wafer; A liquid resin is applied to the external terminal group side main surface of the semiconductor wafer to form a resin sealing film so as to resin seal the external terminal group, and an end face of the external terminal is exposed from the resin sealing film. A resin sealing film forming step, and a dicing step in which the semiconductor wafer is diced for each chip portion. 8. The method according to claim 7, wherein a solder bump is provided on the external terminal. 9. The method according to claim 7, wherein a solder coating is formed on the external terminals. 10. The method according to claim 7, wherein the external terminals are formed by gold plating. 11. Before forming the resin sealing film,
11. The semiconductor device according to claim 7, wherein a liquid resin is applied to an external terminal group side main surface of the semiconductor wafer to form an underfill film so as to protect the external terminal group. A method for manufacturing a semiconductor device.