JP5608430B2 - 配線基板及び配線基板の製造方法 - Google Patents

配線基板及び配線基板の製造方法 Download PDF

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Publication number
JP5608430B2
JP5608430B2 JP2010130421A JP2010130421A JP5608430B2 JP 5608430 B2 JP5608430 B2 JP 5608430B2 JP 2010130421 A JP2010130421 A JP 2010130421A JP 2010130421 A JP2010130421 A JP 2010130421A JP 5608430 B2 JP5608430 B2 JP 5608430B2
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Japan
Prior art keywords
layer
film
electrode
copper
wiring pattern
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JP2010130421A
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English (en)
Japanese (ja)
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JP2011258663A5 (https=
JP2011258663A (ja
Inventor
昌宏 春原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2010130421A priority Critical patent/JP5608430B2/ja
Priority to US13/153,579 priority patent/US8895868B2/en
Publication of JP2011258663A publication Critical patent/JP2011258663A/ja
Publication of JP2011258663A5 publication Critical patent/JP2011258663A5/ja
Application granted granted Critical
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/30—Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17
    • H05K2203/308—Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2010130421A 2010-06-07 2010-06-07 配線基板及び配線基板の製造方法 Active JP5608430B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2010130421A JP5608430B2 (ja) 2010-06-07 2010-06-07 配線基板及び配線基板の製造方法
US13/153,579 US8895868B2 (en) 2010-06-07 2011-06-06 Wiring substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010130421A JP5608430B2 (ja) 2010-06-07 2010-06-07 配線基板及び配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2011258663A JP2011258663A (ja) 2011-12-22
JP2011258663A5 JP2011258663A5 (https=) 2013-05-16
JP5608430B2 true JP5608430B2 (ja) 2014-10-15

Family

ID=45063594

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010130421A Active JP5608430B2 (ja) 2010-06-07 2010-06-07 配線基板及び配線基板の製造方法

Country Status (2)

Country Link
US (1) US8895868B2 (https=)
JP (1) JP5608430B2 (https=)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013191658A (ja) 2012-03-13 2013-09-26 Micronics Japan Co Ltd 配線基板及びその製造方法
JP6497306B2 (ja) * 2015-06-29 2019-04-10 株式会社デンソー 電子装置及びその製造方法
JP6805633B2 (ja) * 2016-08-24 2020-12-23 富士通株式会社 電子デバイスおよびその製造方法
JP7287455B2 (ja) * 2019-03-26 2023-06-06 三菱マテリアル株式会社 絶縁回路基板の製造方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11220023A (ja) * 1998-02-02 1999-08-10 Sharp Corp 半導体装置及びその製造方法
US6319825B1 (en) * 1999-05-12 2001-11-20 Dongbu Electronics Co., Ltd. Metallization process of semiconductor device
US6617681B1 (en) * 1999-06-28 2003-09-09 Intel Corporation Interposer and method of making same
JP2004014848A (ja) * 2002-06-07 2004-01-15 Murata Mfg Co Ltd 薄膜回路基板及びその製造方法
JP4533283B2 (ja) * 2005-08-29 2010-09-01 新光電気工業株式会社 半導体装置の製造方法
JP5231733B2 (ja) * 2006-11-27 2013-07-10 パナソニック株式会社 貫通孔配線構造およびその形成方法
JP2009238957A (ja) * 2008-03-26 2009-10-15 Panasonic Electric Works Co Ltd 基板へのビアの形成方法
JP5343245B2 (ja) 2008-05-15 2013-11-13 新光電気工業株式会社 シリコンインターポーザの製造方法
JP2009295859A (ja) * 2008-06-06 2009-12-17 Oki Semiconductor Co Ltd 半導体装置および半導体装置の製造方法
JP5498864B2 (ja) * 2010-06-07 2014-05-21 新光電気工業株式会社 配線基板及び配線基板の製造方法

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Publication number Publication date
US8895868B2 (en) 2014-11-25
JP2011258663A (ja) 2011-12-22
US20110297430A1 (en) 2011-12-08

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