JP5607758B2 - 半導体をパッケージングする方法 - Google Patents

半導体をパッケージングする方法 Download PDF

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Publication number
JP5607758B2
JP5607758B2 JP2012548940A JP2012548940A JP5607758B2 JP 5607758 B2 JP5607758 B2 JP 5607758B2 JP 2012548940 A JP2012548940 A JP 2012548940A JP 2012548940 A JP2012548940 A JP 2012548940A JP 5607758 B2 JP5607758 B2 JP 5607758B2
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Japan
Prior art keywords
leads
lead frame
die
dies
lower lead
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Japanese (ja)
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JP2013517624A5 (https=
JP2013517624A (ja
Inventor
ジャウネイ サージ
ベラーニ スレシュ
クオ フランク
マオ セン
ワン ピーター
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ヴィシェイ−シリコニックス
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/60—Strap connectors, e.g. thick copper clips for grounding of power devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/481—Leadframes for devices being provided for in groups H10D8/00 - H10D48/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/076—Connecting or disconnecting of strap connectors
    • H10W72/07631—Techniques
    • H10W72/07636—Soldering or alloying
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/726—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/761—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors
    • H10W90/766—Package configurations characterised by the relative positions of pads or connectors relative to package parts of strap connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2012548940A 2010-01-19 2010-12-07 半導体をパッケージングする方法 Active JP5607758B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US29647110P 2010-01-19 2010-01-19
US61/296,471 2010-01-19
US12/730,230 2010-03-24
US12/730,230 US8586419B2 (en) 2010-01-19 2010-03-24 Semiconductor packages including die and L-shaped lead and method of manufacture
PCT/US2010/059326 WO2011090574A2 (en) 2010-01-19 2010-12-07 Semiconductor package and method

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2014173498A Division JP2015057823A (ja) 2010-01-19 2014-08-28 半導体パッケージおよび方法

Publications (3)

Publication Number Publication Date
JP2013517624A JP2013517624A (ja) 2013-05-16
JP2013517624A5 JP2013517624A5 (https=) 2013-11-21
JP5607758B2 true JP5607758B2 (ja) 2014-10-15

Family

ID=44276982

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2012548940A Active JP5607758B2 (ja) 2010-01-19 2010-12-07 半導体をパッケージングする方法
JP2014173498A Pending JP2015057823A (ja) 2010-01-19 2014-08-28 半導体パッケージおよび方法

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2014173498A Pending JP2015057823A (ja) 2010-01-19 2014-08-28 半導体パッケージおよび方法

Country Status (6)

Country Link
US (1) US8586419B2 (https=)
EP (1) EP2526565B1 (https=)
JP (2) JP5607758B2 (https=)
KR (1) KR101534463B1 (https=)
CN (1) CN102714201B (https=)
WO (1) WO2011090574A2 (https=)

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TWI453831B (zh) 2010-09-09 2014-09-21 台灣捷康綜合有限公司 半導體封裝結構及其製造方法
JP5333402B2 (ja) * 2010-10-06 2013-11-06 三菱電機株式会社 半導体装置の製造方法
CN102394232A (zh) * 2011-11-29 2012-03-28 杭州矽力杰半导体技术有限公司 一种引线框架及应用其的芯片倒装封装装置
US9589929B2 (en) 2013-03-14 2017-03-07 Vishay-Siliconix Method for fabricating stack die package
US9966330B2 (en) 2013-03-14 2018-05-08 Vishay-Siliconix Stack die package
CN105378917B (zh) * 2013-03-14 2018-09-25 维西埃-硅化物公司 堆叠芯片封装
CN103395735B (zh) * 2013-08-05 2015-12-02 天津大学 微机电系统器件的封装结构
CN103646930B (zh) * 2013-12-05 2016-02-24 江苏长电科技股份有限公司 二次先蚀后镀金属框减法埋芯片倒装平脚结构及工艺方法
CN103646938B (zh) * 2013-12-05 2016-02-24 江苏长电科技股份有限公司 一次先镀后蚀金属框减法埋芯片倒装凸点结构及工艺方法
CN103646931B (zh) * 2013-12-05 2016-06-29 江苏长电科技股份有限公司 一次先镀后蚀金属框减法埋芯片倒装平脚结构及工艺方法
CN103646937B (zh) * 2013-12-05 2016-02-24 江苏长电科技股份有限公司 二次先蚀后镀金属框减法埋芯片倒装凸点结构及工艺方法
CN103681582B (zh) * 2013-12-05 2016-03-30 江苏长电科技股份有限公司 一次先蚀后镀金属框减法埋芯片正装凸点结构及工艺方法
JP2015176871A (ja) * 2014-03-12 2015-10-05 株式会社東芝 半導体装置及びその製造方法
US9425304B2 (en) 2014-08-21 2016-08-23 Vishay-Siliconix Transistor structure with improved unclamped inductive switching immunity
CN104952737B (zh) * 2015-06-30 2017-12-26 通富微电子股份有限公司 一种具有铝带或l脚或凸起的封装框架结构及生产方法
KR101734712B1 (ko) * 2015-12-09 2017-05-11 현대자동차주식회사 파워모듈
US9870985B1 (en) * 2016-07-11 2018-01-16 Amkor Technology, Inc. Semiconductor package with clip alignment notch
JP6892796B2 (ja) * 2017-07-07 2021-06-23 新光電気工業株式会社 電子部品装置及びその製造方法
DE102019103281B4 (de) * 2019-02-11 2023-03-16 Infineon Technologies Ag Verfahren zum bilden eines die-gehäuses
CN111725173A (zh) * 2020-06-05 2020-09-29 杰群电子科技（东莞）有限公司 一种堆叠封装结构及堆叠封装结构的制造方法
DE112021005639T5 (de) * 2020-12-23 2023-08-03 Rohm Co., Ltd. Verfahren zur herstellung eines halbleiterbauteils und halbleiterbauteils
US12142548B2 (en) * 2021-12-30 2024-11-12 Alpha And Omega Semiconductor International Lp Semiconductor package having mold locking feature
CN219123228U (zh) * 2023-01-06 2023-06-02 上海凯虹科技电子有限公司 引线框架及封装结构

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JPH11177007A (ja) * 1997-12-15 1999-07-02 Hitachi Ltd トランジスタパッケージ
JP4450800B2 (ja) * 1999-02-17 2010-04-14 株式会社ルネサステクノロジ 半導体装置の製造方法
JP3314768B2 (ja) * 1999-10-26 2002-08-12 サンケン電気株式会社 半導体装置及びその製造方法
US6734536B2 (en) 2001-01-12 2004-05-11 Rohm Co., Ltd. Surface-mounting semiconductor device and method of making the same
JP2002222890A (ja) * 2001-01-25 2002-08-09 Rohm Co Ltd 半導体装置およびその製造方法
US6777800B2 (en) * 2002-09-30 2004-08-17 Fairchild Semiconductor Corporation Semiconductor die package including drain clip
US7132734B2 (en) * 2003-01-06 2006-11-07 Micron Technology, Inc. Microelectronic component assemblies and microelectronic component lead frame structures
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US7238551B2 (en) * 2004-11-23 2007-07-03 Siliconix Incorporated Method of fabricating semiconductor package including die interposed between cup-shaped lead frame having mesas and valleys
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Also Published As

Publication number Publication date
KR20120125462A (ko) 2012-11-15
CN102714201A (zh) 2012-10-03
EP2526565A4 (en) 2014-03-05
WO2011090574A3 (en) 2011-09-22
EP2526565A2 (en) 2012-11-28
CN102714201B (zh) 2015-12-09
JP2013517624A (ja) 2013-05-16
JP2015057823A (ja) 2015-03-26
KR101534463B1 (ko) 2015-07-07
US20110175217A1 (en) 2011-07-21
EP2526565B1 (en) 2019-02-20
WO2011090574A2 (en) 2011-07-28
US8586419B2 (en) 2013-11-19

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