JP5581519B2 - 半導体パッケージとその製造方法 - Google Patents

半導体パッケージとその製造方法 Download PDF

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Publication number
JP5581519B2
JP5581519B2 JP2009276270A JP2009276270A JP5581519B2 JP 5581519 B2 JP5581519 B2 JP 5581519B2 JP 2009276270 A JP2009276270 A JP 2009276270A JP 2009276270 A JP2009276270 A JP 2009276270A JP 5581519 B2 JP5581519 B2 JP 5581519B2
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Prior art keywords
sealing resin
layer
pad
semiconductor package
resin layer
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JP2009276270A
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English (en)
Japanese (ja)
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JP2011119502A (ja
JP2011119502A5 (https=
Inventor
規良 清水
昭雄 六川
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Priority to JP2009276270A priority Critical patent/JP5581519B2/ja
Priority to US12/951,509 priority patent/US8378492B2/en
Publication of JP2011119502A publication Critical patent/JP2011119502A/ja
Publication of JP2011119502A5 publication Critical patent/JP2011119502A5/ja
Priority to US13/736,470 priority patent/US8785256B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/141—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being on at least the sidewalls of the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H10W74/019—Manufacture or treatment using temporary auxiliary substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/142—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations exposing the passive side of the semiconductor body

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2009276270A 2009-12-04 2009-12-04 半導体パッケージとその製造方法 Active JP5581519B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2009276270A JP5581519B2 (ja) 2009-12-04 2009-12-04 半導体パッケージとその製造方法
US12/951,509 US8378492B2 (en) 2009-12-04 2010-11-22 Semiconductor package
US13/736,470 US8785256B2 (en) 2009-12-04 2013-01-08 Method of manufacturing semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009276270A JP5581519B2 (ja) 2009-12-04 2009-12-04 半導体パッケージとその製造方法

Publications (3)

Publication Number Publication Date
JP2011119502A JP2011119502A (ja) 2011-06-16
JP2011119502A5 JP2011119502A5 (https=) 2012-11-22
JP5581519B2 true JP5581519B2 (ja) 2014-09-03

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Family Applications (1)

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Country Status (2)

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US (2) US8378492B2 (https=)
JP (1) JP5581519B2 (https=)

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JP5977051B2 (ja) 2012-03-21 2016-08-24 新光電気工業株式会社 半導体パッケージ、半導体装置及び半導体パッケージの製造方法
JP6152254B2 (ja) 2012-09-12 2017-06-21 新光電気工業株式会社 半導体パッケージ、半導体装置及び半導体パッケージの製造方法
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JP6136413B2 (ja) * 2013-03-18 2017-05-31 富士通株式会社 部品内蔵基板の製造方法
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JP2016093874A (ja) * 2014-11-17 2016-05-26 株式会社ディスコ パッケージ基板の加工方法
US10388608B2 (en) * 2015-08-28 2019-08-20 Hitachi Chemical Company, Ltd. Semiconductor device and method for manufacturing same
US10361121B2 (en) * 2016-05-13 2019-07-23 Intel Corporation Aluminum oxide for thermal management or adhesion
US10128193B2 (en) * 2016-11-29 2018-11-13 Taiwan Semiconductor Manufacturing Co., Ltd. Package structure and method for forming the same
WO2018125094A1 (en) * 2016-12-28 2018-07-05 Intel Corporation Methods of forming barrier structures in high density package substrates
US10325786B1 (en) * 2017-12-07 2019-06-18 Sj Semiconductor (Jiangyin) Corporation Double-sided plastic fan-out package structure having antenna and manufacturing method thereof
US10665522B2 (en) 2017-12-22 2020-05-26 Intel IP Corporation Package including an integrated routing layer and a molded routing layer
US12062700B2 (en) 2018-04-04 2024-08-13 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US12046505B2 (en) * 2018-04-20 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
WO2020009759A1 (en) 2018-07-02 2020-01-09 Qorvo Us, Inc. Rf semiconductor device and manufacturing method thereof
US11114359B2 (en) * 2018-09-13 2021-09-07 Dialog Semiconductor (Uk) Limited Wafer level chip scale package structure
US10867939B2 (en) * 2018-11-27 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating the same
US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
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US12057374B2 (en) 2019-01-23 2024-08-06 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
DE102019202721B4 (de) 2019-02-28 2021-03-25 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. 3d-flexfolien-package
DE102019202715A1 (de) 2019-02-28 2020-09-03 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Folienbasiertes package mit distanzausgleich
DE102019202718B4 (de) 2019-02-28 2020-12-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Dünnes Dual-Folienpackage und Verfahren zum Herstellen desselben
DE102019202716B4 (de) 2019-02-28 2020-12-24 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Flex-folien-package mit coplanarer topologie für hochfrequenzsignale und verfahren zum herstellen eines derartigen flex-folien-packages
DE102019202720B4 (de) * 2019-02-28 2021-04-01 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Dünnes Chip-Folienpackage für Halbleiter-Chips mit indirekter Kontaktierung und Verfahren zum Herstellen Desselben
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Also Published As

Publication number Publication date
US20130122657A1 (en) 2013-05-16
US20110133341A1 (en) 2011-06-09
US8785256B2 (en) 2014-07-22
JP2011119502A (ja) 2011-06-16
US8378492B2 (en) 2013-02-19

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