JP5607086B2 - 半導体パッケージの製造方法 - Google Patents
半導体パッケージの製造方法 Download PDFInfo
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- JP5607086B2 JP5607086B2 JP2012015077A JP2012015077A JP5607086B2 JP 5607086 B2 JP5607086 B2 JP 5607086B2 JP 2012015077 A JP2012015077 A JP 2012015077A JP 2012015077 A JP2012015077 A JP 2012015077A JP 5607086 B2 JP5607086 B2 JP 5607086B2
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- 239000004065 semiconductor Substances 0.000 title claims description 192
- 238000004519 manufacturing process Methods 0.000 title claims description 54
- 239000000758 substrate Substances 0.000 claims description 140
- 239000010410 layer Substances 0.000 claims description 136
- 239000012212 insulator Substances 0.000 claims description 55
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- 230000001681 protective effect Effects 0.000 claims description 52
- 238000000034 method Methods 0.000 claims description 30
- 230000000149 penetrating effect Effects 0.000 claims description 13
- 238000010030 laminating Methods 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 description 18
- 230000017525 heat dissipation Effects 0.000 description 9
- 239000010408 film Substances 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 7
- 239000000463 material Substances 0.000 description 7
- 230000008054 signal transmission Effects 0.000 description 7
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
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- 238000005452 bending Methods 0.000 description 3
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- 239000011241 protective layer Substances 0.000 description 3
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- 230000001070 adhesive effect Effects 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
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- 238000007772 electroless plating Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 230000035515 penetration Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
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- 230000005855 radiation Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
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Description
110 保護部材
120 絶縁体
130 受動素子
140 能動素子
150 ビルドアップ層
160 パッド
170 ソルダレジスト層
180 外部接続手段
200、400 キャリア基板
300 放熱部材
Claims (6)
- 支持層、該支持層の両面にそれぞれ配置された離型層及び該離型層上に配置された接着層を含むキャリア基板を提供する段階と、
前記キャリア基板の両面に第1及び第2開口部を具備する絶縁体をそれぞれ積層する段階と、
前記第1開口部に対応した前記キャリア基板の両面に配置された能動素子、前記第2開口部に対応した前記キャリア基板の両面に配置された受動素子、前記能動素子と電気的に連結される少なくとも一層以上のビルドアップ層、及び前記絶縁体を含む半導体パッケージをそれぞれ形成する段階と、
前記離型層から前記接着層を分離して前記半導体パッケージの下部面に配置される前記接着層を除去して、前記キャリア基板から前記半導体パッケージを分離し、前記受動素子を含んだ前記半導体パッケージの下部に保護部材を形成する段階と、
前記半導体パッケージ上に外部接続手段を形成する段階と、
を含むことを特徴とする半導体パッケージの製造方法。 - 支持層、前記支持層の両面にそれぞれ配置された離型層及び該離型層上に配置された接着層を含むキャリア基板を提供する段階と、
前記キャリア基板の両面に第1及び第2開口部を具備する絶縁体をそれぞれ積層する段階と、
前記第1開口部に対応した前記キャリア基板の両面に配置された能動素子、前記第2開口部に対応した前記キャリア基板の両面に配置された受動素子、前記能動素子と電気的に連結される少なくとも一層以上のビルドアップ層及び前記絶縁体を含む半導体パッケージをそれぞれ形成する段階と、
前記離型層から前記接着層を分離する段階と、
前記半導体パッケージ上に外部接続手段を形成する段階と、
を含み、
前記接着層を残存させて、前記保護部材で利用することを特徴とする半導体パッケージの製造方法。 - キャリア基板を提供する段階と、
前記キャリア基板の両面に貫通部を具備する保護部材を形成する段階と、
前記保護部材上に、前記貫通部に対応した前記第1開口部、該第1開口部の周辺に配置された前記第2開口部を含んだ絶縁体を積層する段階と、
前記第1開口部に対応する前記キャリア基板の両面に配置された能動素子、前記第2開口部に対応する前記キャリア基板の両面に配置された受動素子、前記能動素子と電気的に連結される少なくとも一層以上のビルドアップ層、前記保護部材及び前記絶縁体を含む半導体パッケージをそれぞれ形成する段階と、
前記キャリア基板から前記半導体パッケージを分離する段階と、
前記半導体パッケージ上に外部接続手段を形成する段階と、
を含むことを特徴とする半導体パッケージの製造方法。 - 支持層、前記支持層の両面にそれぞれ配置された離型層及び該離型層上に配置された接着層を含むことをキャリア基板を提供する段階と、
前記キャリア基板の両面に貫通部を具備する保護部材及び該保護部材上に配置されて、第1及び第2開口部を含んだ絶縁体を形成する段階と、
前記第1開口部に対応した前記キャリア基板の両面に配置された能動素子、前記第2開口部に対応した前記キャリア基板の両面に配置された受動素子、前記能動素子と電気的に連結される少なくとも一層以上のビルドアップ層、前記保護部材及び前記絶縁体を含む半導体パッケージをそれぞれ形成する段階と、
前記離型層から前記接着層を分離する段階と、
前記半導体パッケージ上に外部接続手段を形成する段階と、
を含むことを特徴とする半導体パッケージの製造方法。 - 前記接着層を除去する段階をさらに含むことを特徴とする請求項4に記載の半導体パッケージの製造方法。
- 前記接着層を除去する段階以後に、前記貫通部によって露出した前記能動素子上に放熱部材を付着する段階をさらに含むことを特徴とする請求項5に記載の半導体パッケージの製造方法。
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