JP5566623B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
- Publication number
- JP5566623B2 JP5566623B2 JP2009090443A JP2009090443A JP5566623B2 JP 5566623 B2 JP5566623 B2 JP 5566623B2 JP 2009090443 A JP2009090443 A JP 2009090443A JP 2009090443 A JP2009090443 A JP 2009090443A JP 5566623 B2 JP5566623 B2 JP 5566623B2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- sense amplifier
- write
- memory cell
- bit line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 52
- 230000005669 field effect Effects 0.000 claims description 25
- 239000003990 capacitor Substances 0.000 claims description 20
- 238000012546 transfer Methods 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 14
- 238000012544 monitoring process Methods 0.000 claims description 12
- 230000001419 dependent effect Effects 0.000 claims description 11
- 230000003071 parasitic effect Effects 0.000 claims description 10
- 230000006870 function Effects 0.000 claims description 4
- 238000012937 correction Methods 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 12
- 238000013461 design Methods 0.000 description 10
- 230000003321 amplification Effects 0.000 description 9
- 238000006243 chemical reaction Methods 0.000 description 9
- 238000003199 nucleic acid amplification method Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 7
- 230000008859 change Effects 0.000 description 4
- 230000007704 transition Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 3
- 108091006146 Channels Proteins 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010365 information processing Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
- Read Only Memory (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2009090443A JP5566623B2 (ja) | 2008-04-04 | 2009-04-02 | 半導体記憶装置 |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008098246 | 2008-04-04 | ||
| JP2008098246 | 2008-04-04 | ||
| JP2009090443A JP5566623B2 (ja) | 2008-04-04 | 2009-04-02 | 半導体記憶装置 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014125646A Division JP2014197447A (ja) | 2008-04-04 | 2014-06-18 | 半導体記憶装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2009266364A JP2009266364A (ja) | 2009-11-12 |
| JP2009266364A5 JP2009266364A5 (enExample) | 2011-03-31 |
| JP5566623B2 true JP5566623B2 (ja) | 2014-08-06 |
Family
ID=41133108
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009090443A Expired - Fee Related JP5566623B2 (ja) | 2008-04-04 | 2009-04-02 | 半導体記憶装置 |
| JP2014125646A Withdrawn JP2014197447A (ja) | 2008-04-04 | 2014-06-18 | 半導体記憶装置 |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2014125646A Withdrawn JP2014197447A (ja) | 2008-04-04 | 2014-06-18 | 半導体記憶装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7933141B2 (enExample) |
| JP (2) | JP5566623B2 (enExample) |
| KR (1) | KR101050699B1 (enExample) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6928026B2 (en) * | 2002-03-19 | 2005-08-09 | Broadcom Corporation | Synchronous global controller for enhanced pipelining |
| KR101046556B1 (ko) * | 2008-03-17 | 2011-07-05 | 엘피다 메모리 가부시키가이샤 | 단일 종단 감지 증폭기를 갖는 반도체 디바이스 |
| KR101434400B1 (ko) * | 2008-07-09 | 2014-08-27 | 삼성전자주식회사 | 불휘발성 메모리 장치 및 메모리 시스템 및 그것의 관리방법 |
| JP5433187B2 (ja) * | 2008-08-28 | 2014-03-05 | ピーエスフォー ルクスコ エスエイアールエル | 半導体記憶装置及びそのテスト方法 |
| JP2011159365A (ja) * | 2010-02-02 | 2011-08-18 | Elpida Memory Inc | 半導体装置及び半導体装置を含む情報処理システム |
| US8254195B2 (en) * | 2010-06-01 | 2012-08-28 | Qualcomm Incorporated | High-speed sensing for resistive memories |
| JP2012123893A (ja) * | 2010-11-19 | 2012-06-28 | Elpida Memory Inc | 半導体装置 |
| US8406073B1 (en) * | 2010-12-22 | 2013-03-26 | Intel Corporation | Hierarchical DRAM sensing |
| US8605528B2 (en) | 2011-11-03 | 2013-12-10 | International Business Machines Corporation | Sense amplifier having an isolated pre-charge architecture, a memory circuit incorporating such a sense amplifier and associated methods |
| JP2013235624A (ja) * | 2012-05-07 | 2013-11-21 | Ps4 Luxco S A R L | 半導体装置 |
| US9310420B2 (en) * | 2013-01-24 | 2016-04-12 | Finisar Corporation | Pixel test in a liquid crystal on silicon chip |
| US9093175B2 (en) | 2013-03-27 | 2015-07-28 | International Business Machines Corporation | Signal margin centering for single-ended eDRAM sense amplifier |
| JP2015185179A (ja) | 2014-03-20 | 2015-10-22 | 株式会社東芝 | 抵抗変化メモリ |
| KR102217243B1 (ko) | 2014-10-28 | 2021-02-18 | 삼성전자주식회사 | 저항성 메모리 장치, 저항성 메모리 시스템 및 저항성 메모리 장치의 동작방법 |
| KR20160117222A (ko) * | 2015-03-30 | 2016-10-10 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 반도체 장치의 검사 방법 |
| US9589604B1 (en) * | 2015-09-17 | 2017-03-07 | International Business Machines Corporation | Single ended bitline current sense amplifier for SRAM applications |
| US9792967B1 (en) | 2016-06-13 | 2017-10-17 | International Business Machines Corporation | Managing semiconductor memory array leakage current |
| US9786345B1 (en) | 2016-09-16 | 2017-10-10 | Micron Technology, Inc. | Compensation for threshold voltage variation of memory cell components |
| CN109756204B (zh) * | 2019-03-05 | 2023-11-14 | 广东合微集成电路技术有限公司 | 一种滤波器、振荡产生电路和电子器件 |
| US10796734B1 (en) * | 2019-05-24 | 2020-10-06 | Micron Technology, Inc. | Apparatuses including temperature-based threshold voltage compensated sense amplifiers and methods for compensating same |
| CN114121073B (zh) * | 2020-08-27 | 2023-09-12 | 长鑫存储技术有限公司 | 存储器的调节方法、调节系统以及半导体器件 |
| CN119207511B (zh) * | 2023-06-20 | 2025-10-14 | 长鑫存储技术有限公司 | 存储器的控制方法、控制电路和存储器 |
| US20250124971A1 (en) * | 2023-12-28 | 2025-04-17 | Atomera Incorporated | Single-Ended Sense Amplifiers And Methods For Operating Same |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58168310A (ja) | 1982-03-30 | 1983-10-04 | Fujitsu Ltd | 出力回路 |
| EP0147968A3 (en) | 1983-12-23 | 1986-09-17 | General Motors Corporation | Temperature compensated magnetic bubble memory |
| US4727269A (en) | 1985-08-15 | 1988-02-23 | Fairchild Camera & Instrument Corporation | Temperature compensated sense amplifier |
| JPS63228496A (ja) * | 1987-03-17 | 1988-09-22 | Fujitsu Ltd | メモリ回路 |
| JPS6476495A (en) * | 1987-09-17 | 1989-03-22 | Matsushita Electric Industrial Co Ltd | Semiconductor memory device |
| JPH04153977A (ja) * | 1990-10-17 | 1992-05-27 | Hitachi Ltd | 半導体メモリ |
| JPH05242681A (ja) * | 1992-02-28 | 1993-09-21 | Toshiba Corp | 半導体集積回路装置 |
| JP3222235B2 (ja) | 1992-12-28 | 2001-10-22 | 沖電気工業株式会社 | センス回路 |
| JPH06243678A (ja) | 1993-02-19 | 1994-09-02 | Hitachi Ltd | ダイナミック型ramとそのプレート電圧設定方法及び情報処理システム |
| US5636170A (en) | 1995-11-13 | 1997-06-03 | Micron Technology, Inc. | Low voltage dynamic memory |
| JPH11297084A (ja) * | 1998-04-08 | 1999-10-29 | Hitachi Ltd | 半導体装置 |
| KR100326245B1 (ko) * | 1998-04-21 | 2002-04-17 | 박종섭 | 특정온도에서스탠바이모드로자동전환하기위한장치 |
| JP4043703B2 (ja) * | 2000-09-04 | 2008-02-06 | 株式会社ルネサステクノロジ | 半導体装置、マイクロコンピュータ、及びフラッシュメモリ |
| WO2004015867A1 (en) * | 2002-08-08 | 2004-02-19 | Koninklijke Philips Electronics N.V. | Circuit and method for controlling the threshold voltage of transistors |
| US6868025B2 (en) | 2003-03-10 | 2005-03-15 | Sharp Laboratories Of America, Inc. | Temperature compensated RRAM circuit |
| JP2005182873A (ja) | 2003-12-17 | 2005-07-07 | Seiko Epson Corp | 半導体記憶装置 |
| JP5400259B2 (ja) | 2004-11-19 | 2014-01-29 | ピーエスフォー ルクスコ エスエイアールエル | 半導体記憶装置 |
| JP2008059680A (ja) * | 2006-08-31 | 2008-03-13 | Hitachi Ltd | 半導体装置 |
| US7542343B1 (en) * | 2007-09-21 | 2009-06-02 | Juhan Kim | Planar NAND flash memory |
| US7443714B1 (en) * | 2007-10-23 | 2008-10-28 | Juhan Kim | DRAM including segment read circuit |
-
2009
- 2009-04-01 KR KR1020090028220A patent/KR101050699B1/ko not_active Expired - Fee Related
- 2009-04-01 US US12/416,432 patent/US7933141B2/en not_active Expired - Fee Related
- 2009-04-02 JP JP2009090443A patent/JP5566623B2/ja not_active Expired - Fee Related
-
2014
- 2014-06-18 JP JP2014125646A patent/JP2014197447A/ja not_active Withdrawn
Also Published As
| Publication number | Publication date |
|---|---|
| JP2009266364A (ja) | 2009-11-12 |
| KR20090106346A (ko) | 2009-10-08 |
| US20090251948A1 (en) | 2009-10-08 |
| US7933141B2 (en) | 2011-04-26 |
| KR101050699B1 (ko) | 2011-07-20 |
| JP2014197447A (ja) | 2014-10-16 |
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