JP5536901B2 - 半導体ダイの反りを制御する装置及び方法 - Google Patents

半導体ダイの反りを制御する装置及び方法 Download PDF

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Publication number
JP5536901B2
JP5536901B2 JP2012544923A JP2012544923A JP5536901B2 JP 5536901 B2 JP5536901 B2 JP 5536901B2 JP 2012544923 A JP2012544923 A JP 2012544923A JP 2012544923 A JP2012544923 A JP 2012544923A JP 5536901 B2 JP5536901 B2 JP 5536901B2
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semiconductor die
die
vias
arc
substrate
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JP2013526001A (ja
JP2013526001A5 (https=
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シュエ・バイ
ウルミ・レイ
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クアルコム，インコーポレイテッド
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W40/00—Arrangements for thermal protection or thermal control
    • H10W40/20—Arrangements for cooling
    • H10W40/22—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections
    • H10W40/226—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area
    • H10W40/228—Arrangements for cooling characterised by their shape, e.g. having conical or cylindrical projections characterised by projecting parts, e.g. fins to increase surface area the projecting parts being wire-shaped or pin-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2012544923A 2009-12-17 2010-12-17 半導体ダイの反りを制御する装置及び方法 Expired - Fee Related JP5536901B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/640,111 2009-12-17
US12/640,111 US8710629B2 (en) 2009-12-17 2009-12-17 Apparatus and method for controlling semiconductor die warpage
PCT/US2010/061143 WO2011084706A2 (en) 2009-12-17 2010-12-17 Apparatus and method for controlling semiconductor die warpage

Publications (3)

Publication Number Publication Date
JP2013526001A JP2013526001A (ja) 2013-06-20
JP2013526001A5 JP2013526001A5 (https=) 2014-04-10
JP5536901B2 true JP5536901B2 (ja) 2014-07-02

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JP2012544923A Expired - Fee Related JP5536901B2 (ja) 2009-12-17 2010-12-17 半導体ダイの反りを制御する装置及び方法

Country Status (7)

Country Link
US (1) US8710629B2 (https=)
EP (1) EP2513967A2 (https=)
JP (1) JP5536901B2 (https=)
KR (1) KR20120101136A (https=)
CN (1) CN103038877A (https=)
TW (1) TW201131717A (https=)
WO (1) WO2011084706A2 (https=)

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US9184144B2 (en) * 2011-07-21 2015-11-10 Qualcomm Incorporated Interconnect pillars with directed compliance geometry
US9059191B2 (en) * 2011-10-19 2015-06-16 International Business Machines Corporation Chamfered corner crackstop for an integrated circuit chip
US8464200B1 (en) 2012-02-15 2013-06-11 International Business Machines Corporation Thermal relief optimization
US8566773B2 (en) 2012-02-15 2013-10-22 International Business Machines Corporation Thermal relief automation
CN103378030B (zh) * 2012-04-18 2016-04-20 中芯国际集成电路制造(上海)有限公司 硅通孔结构
CN103377990B (zh) * 2012-04-18 2016-08-31 中芯国际集成电路制造(上海)有限公司 硅通孔结构
US9291578B2 (en) * 2012-08-03 2016-03-22 David L. Adler X-ray photoemission microscope for integrated devices
US9245826B2 (en) * 2013-03-11 2016-01-26 Newport Fab, Llc Anchor vias for improved backside metal adhesion to semiconductor substrate
US9247636B2 (en) 2013-03-12 2016-01-26 International Business Machines Corporation Area array device connection structures with complimentary warp characteristics
US9355967B2 (en) 2013-06-24 2016-05-31 Qualcomm Incorporated Stress compensation patterning
US9236301B2 (en) 2013-07-11 2016-01-12 Globalfoundries Inc. Customized alleviation of stresses generated by through-substrate via(S)
KR102122456B1 (ko) 2013-12-20 2020-06-12 삼성전자주식회사 실리콘 관통 비아 플러그들을 갖는 반도체 소자 및 이를 포함하는 반도체 패키지
US10006899B2 (en) 2014-03-25 2018-06-26 Genia Technologies, Inc. Nanopore-based sequencing chips using stacked wafer technology
US9728518B2 (en) 2014-04-01 2017-08-08 Ati Technologies Ulc Interconnect etch with polymer layer edge protection
US9560745B2 (en) * 2014-09-26 2017-01-31 Qualcomm Incorporated Devices and methods to reduce stress in an electronic device
US9772268B2 (en) * 2015-03-30 2017-09-26 International Business Machines Corporation Predicting semiconductor package warpage
US9721906B2 (en) * 2015-08-31 2017-08-01 Intel Corporation Electronic package with corner supports
US20170287873A1 (en) * 2016-03-29 2017-10-05 Santosh Sankarasubramanian Electronic assembly components with corner adhesive for warpage reduction during thermal processing
CN106531714A (zh) * 2017-01-24 2017-03-22 日月光封装测试(上海)有限公司 用于半导体封装的引线框架条及其制造方法
US11264337B2 (en) 2017-03-14 2022-03-01 Mediatek Inc. Semiconductor package structure
US11387176B2 (en) 2017-03-14 2022-07-12 Mediatek Inc. Semiconductor package structure
US12424531B2 (en) 2017-03-14 2025-09-23 Mediatek Inc. Semiconductor package structure
US11171113B2 (en) 2017-03-14 2021-11-09 Mediatek Inc. Semiconductor package structure having an annular frame with truncated corners
US10784211B2 (en) 2017-03-14 2020-09-22 Mediatek Inc. Semiconductor package structure
US11362044B2 (en) 2017-03-14 2022-06-14 Mediatek Inc. Semiconductor package structure
US10396003B2 (en) * 2017-10-18 2019-08-27 Micron Technology, Inc. Stress tuned stiffeners for micro electronics package warpage control
US10861797B2 (en) * 2018-07-16 2020-12-08 Micron Technology, Inc. Electrically or temperature activated shape-memory materials for warpage control
US11879170B2 (en) 2019-08-14 2024-01-23 Massachusetts Institute Of Technology Stress patterning systems and methods for manufacturing free-form deformations in thin substrates
US11308257B1 (en) 2020-12-15 2022-04-19 International Business Machines Corporation Stacked via rivets in chip hotspots
WO2026038490A1 (ja) * 2024-08-13 2026-02-19 Ａｇｃ株式会社 半導体用無機基板

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JP5361156B2 (ja) * 2007-08-06 2013-12-04 ラピスセミコンダクタ株式会社 半導体装置及びその製造方法

Also Published As

Publication number Publication date
EP2513967A2 (en) 2012-10-24
JP2013526001A (ja) 2013-06-20
WO2011084706A3 (en) 2013-03-28
WO2011084706A2 (en) 2011-07-14
US20110147895A1 (en) 2011-06-23
TW201131717A (en) 2011-09-16
CN103038877A (zh) 2013-04-10
US8710629B2 (en) 2014-04-29
KR20120101136A (ko) 2012-09-12

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