JP5988939B2 - 不連続な薄い半導体ウェハ表面のフィーチャ - Google Patents
不連続な薄い半導体ウェハ表面のフィーチャ Download PDFInfo
- Publication number
- JP5988939B2 JP5988939B2 JP2013190298A JP2013190298A JP5988939B2 JP 5988939 B2 JP5988939 B2 JP 5988939B2 JP 2013190298 A JP2013190298 A JP 2013190298A JP 2013190298 A JP2013190298 A JP 2013190298A JP 5988939 B2 JP5988939 B2 JP 5988939B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film layer
- etching
- semiconductor wafer
- die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 51
- 239000000758 substrate Substances 0.000 claims description 92
- 238000005530 etching Methods 0.000 claims description 34
- 238000004519 manufacturing process Methods 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 27
- 238000005498 polishing Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 59
- 229910052710 silicon Inorganic materials 0.000 description 28
- 239000010703 silicon Substances 0.000 description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 27
- 238000010586 diagram Methods 0.000 description 17
- 238000013461 design Methods 0.000 description 14
- 239000000463 material Substances 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 238000003860 storage Methods 0.000 description 8
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- 238000004891 communication Methods 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000010884 ion-beam technique Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000006399 behavior Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000000609 electron-beam lithography Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Weting (AREA)
Description
120 遠隔ユニット
125A、125B、125C ICデバイス
130 遠隔ユニット
140 基地局
150 遠隔ユニット
180 下りリンク信号
190 上りリンク信号
200 設計ワークステーション
201 ハードディスク
203 ドライブ装置
204 記憶媒体
210 回路、回路設計
212 半導体ウェハ
300 積層IC
310 パッケージ基板
320 ダイ
322 パッケージ接続部
324 シリコン貫通電極
330 ダイ
332 パッケージ接続部
400 ダイ
411 基板の裏側
412 基板
413 基板の表側
414 フィルム層
416 シリコン貫通電極
510 ウェハ
512 囲み
514 ダイ
516 エッチング線
518 ダイシング溝
700 ウェハ
710 基板
712 エッチング線
800 ウェハ
810 基板
830 フィルム層
832 エッチング線
834 絶縁プラグ
Claims (4)
- 半導体基板およびフィルム層を備える半導体ウェハを製造する方法であって、
前記半導体ウェハを薄化するステップと、
前記半導体ウェハ内の応力を緩和する不連続面を形成するために、前記半導体ウェハを薄化するステップの後で、前記半導体ウェハに少なくとも1つのエッチング線をエッチングするステップと、
前記不連続面の少なくとも一部分を非導電性絶縁プラグで充填するステップと、
前記非導電性絶縁プラグが前記半導体基板に隣接する前記フィルム層の面と反対である前記フィルム層の表面と同一平面であるように、前記非導電性絶縁プラグを裏面研磨するステップと、
を含む方法。 - 前記半導体ウェハに前記少なくとも1つのエッチング線をエッチングするステップが、前記半導体ウェハの前記半導体基板に少なくとも1つのエッチング線をエッチングするステップを含む、請求項1に記載の方法。
- 前記半導体ウェハに前記少なくとも1つのエッチング線をエッチングするステップが、前記半導体ウェハの前記フィルム層に少なくとも1つのエッチング線をエッチングするステップを含む、請求項1に記載の方法。
- 前記フィルム層が複数の層を含み、
前記半導体ウェハの前記フィルム層に前記少なくとも1つのエッチング線をエッチングするステップが、
前記フィルム層の第1の層に少なくとも1つのエッチング線をエッチングするステップと、
前記フィルム層の第2の層に少なくとも1つのエッチング線をエッチングするステップと、
を含む、請求項3に記載の方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/437,111 US8445994B2 (en) | 2009-05-07 | 2009-05-07 | Discontinuous thin semiconductor wafer surface features |
US12/437,111 | 2009-05-07 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012510024A Division JP2012526401A (ja) | 2009-05-07 | 2010-05-07 | 不連続な薄い半導体ウェハ表面のフィーチャ |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016114447A Division JP2016165015A (ja) | 2009-05-07 | 2016-06-08 | 不連続な薄い半導体ウェハ表面のフィーチャ |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2014013932A JP2014013932A (ja) | 2014-01-23 |
JP5988939B2 true JP5988939B2 (ja) | 2016-09-07 |
Family
ID=42288622
Family Applications (3)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012510024A Pending JP2012526401A (ja) | 2009-05-07 | 2010-05-07 | 不連続な薄い半導体ウェハ表面のフィーチャ |
JP2013190298A Expired - Fee Related JP5988939B2 (ja) | 2009-05-07 | 2013-09-13 | 不連続な薄い半導体ウェハ表面のフィーチャ |
JP2016114447A Pending JP2016165015A (ja) | 2009-05-07 | 2016-06-08 | 不連続な薄い半導体ウェハ表面のフィーチャ |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012510024A Pending JP2012526401A (ja) | 2009-05-07 | 2010-05-07 | 不連続な薄い半導体ウェハ表面のフィーチャ |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016114447A Pending JP2016165015A (ja) | 2009-05-07 | 2016-06-08 | 不連続な薄い半導体ウェハ表面のフィーチャ |
Country Status (7)
Country | Link |
---|---|
US (2) | US8445994B2 (ja) |
EP (1) | EP2427905B1 (ja) |
JP (3) | JP2012526401A (ja) |
KR (1) | KR101431890B1 (ja) |
CN (1) | CN102414802B (ja) |
TW (1) | TW201104741A (ja) |
WO (1) | WO2010129908A1 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8417922B2 (en) * | 2006-08-02 | 2013-04-09 | Qualcomm Incorporated | Method and system to combine multiple register units within a microprocessor |
US8445994B2 (en) | 2009-05-07 | 2013-05-21 | Qualcomm Incorporated | Discontinuous thin semiconductor wafer surface features |
US8083362B2 (en) | 2010-04-29 | 2011-12-27 | Skyline Solar, Inc. | Thin film reflective coating pinning arrangement |
CN103109350A (zh) * | 2010-09-30 | 2013-05-15 | 飞思卡尔半导体公司 | 处理半导体晶片的方法、半导体晶片以及半导体器件 |
US9355967B2 (en) | 2013-06-24 | 2016-05-31 | Qualcomm Incorporated | Stress compensation patterning |
US9397051B2 (en) | 2013-12-03 | 2016-07-19 | Invensas Corporation | Warpage reduction in structures with electrical circuitry |
US9761539B2 (en) | 2015-06-29 | 2017-09-12 | Globalfoundries Inc. | Wafer rigidity with reinforcement structure |
KR102634946B1 (ko) | 2016-11-14 | 2024-02-07 | 삼성전자주식회사 | 반도체 칩 |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0547684A3 (en) * | 1991-12-18 | 1996-11-06 | Koninkl Philips Electronics Nv | Method of manufacturing a semiconductor body comprising a carrier wafer and a monocrystalline semiconducting top layer |
JPH07130836A (ja) * | 1993-11-01 | 1995-05-19 | Matsushita Electric Ind Co Ltd | 素子分離の形成方法 |
JPH0917702A (ja) * | 1995-06-29 | 1997-01-17 | Hitachi Cable Ltd | Si基板及びその製造方法 |
KR100273704B1 (ko) * | 1997-12-20 | 2000-12-15 | 윤종용 | 반도체기판제조방법 |
US6103593A (en) * | 1998-02-13 | 2000-08-15 | Advanced Micro Devices, Inc. | Method and system for providing a contact on a semiconductor device |
US6339251B2 (en) * | 1998-11-10 | 2002-01-15 | Samsung Electronics Co., Ltd | Wafer grooves for reducing semiconductor wafer warping |
JP2003110017A (ja) * | 2001-09-28 | 2003-04-11 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2003115483A (ja) * | 2001-10-05 | 2003-04-18 | Seiko Instruments Inc | 基板の湾曲を低減させる薄膜積層素子の製造方法 |
JP2003332270A (ja) * | 2002-05-15 | 2003-11-21 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US7507638B2 (en) | 2004-06-30 | 2009-03-24 | Freescale Semiconductor, Inc. | Ultra-thin die and method of fabricating same |
US7223673B2 (en) * | 2004-07-15 | 2007-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing semiconductor device with crack prevention ring |
US7576013B2 (en) * | 2004-07-27 | 2009-08-18 | United Microelectronics Corp. | Method of relieving wafer stress |
CN101238570B (zh) * | 2005-08-17 | 2013-01-02 | 富士通株式会社 | 半导体器件及其制造方法 |
TWI416663B (zh) * | 2005-08-26 | 2013-11-21 | Hitachi Ltd | Semiconductor device manufacturing method and semiconductor device |
JP4984558B2 (ja) | 2006-02-08 | 2012-07-25 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
US7880278B2 (en) * | 2006-05-16 | 2011-02-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit having stress tuning layer |
US8445994B2 (en) | 2009-05-07 | 2013-05-21 | Qualcomm Incorporated | Discontinuous thin semiconductor wafer surface features |
-
2009
- 2009-05-07 US US12/437,111 patent/US8445994B2/en not_active Expired - Fee Related
-
2010
- 2010-05-07 EP EP10718017A patent/EP2427905B1/en not_active Not-in-force
- 2010-05-07 KR KR1020117029193A patent/KR101431890B1/ko not_active IP Right Cessation
- 2010-05-07 JP JP2012510024A patent/JP2012526401A/ja active Pending
- 2010-05-07 TW TW099114729A patent/TW201104741A/zh unknown
- 2010-05-07 WO PCT/US2010/034102 patent/WO2010129908A1/en active Application Filing
- 2010-05-07 CN CN201080019777.2A patent/CN102414802B/zh not_active Expired - Fee Related
-
2012
- 2012-11-19 US US13/681,412 patent/US8513089B2/en not_active Expired - Fee Related
-
2013
- 2013-09-13 JP JP2013190298A patent/JP5988939B2/ja not_active Expired - Fee Related
-
2016
- 2016-06-08 JP JP2016114447A patent/JP2016165015A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
CN102414802A (zh) | 2012-04-11 |
CN102414802B (zh) | 2015-02-18 |
EP2427905A1 (en) | 2012-03-14 |
EP2427905B1 (en) | 2013-03-20 |
JP2014013932A (ja) | 2014-01-23 |
US8513089B2 (en) | 2013-08-20 |
WO2010129908A1 (en) | 2010-11-11 |
JP2016165015A (ja) | 2016-09-08 |
US20130084686A1 (en) | 2013-04-04 |
KR20120014026A (ko) | 2012-02-15 |
JP2012526401A (ja) | 2012-10-25 |
KR101431890B1 (ko) | 2014-08-26 |
US20100283131A1 (en) | 2010-11-11 |
US8445994B2 (en) | 2013-05-21 |
TW201104741A (en) | 2011-02-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5988939B2 (ja) | 不連続な薄い半導体ウェハ表面のフィーチャ | |
JP5605958B2 (ja) | 薄い半導体のためのパネル化裏面処理を用いた半導体製造方法及び半導体デバイス | |
US8298906B2 (en) | Trench decoupling capacitor formed by RIE lag of through silicon via (TSV) etch | |
TWI389277B (zh) | 藉由一附有凹槽之環狀孔的晶粒堆疊 | |
JP5859514B2 (ja) | 積層集積回路のための二面の相互接続されたcmos | |
US7691748B2 (en) | Through-silicon via and method for forming the same | |
US7507637B2 (en) | Method of manufacturing wafer level stack package | |
US20100314725A1 (en) | Stress Balance Layer on Semiconductor Wafer Backside | |
US8933540B2 (en) | Thermal via for 3D integrated circuits structures | |
KR20240056662A (ko) | 리소그래픽으로 정의된 비아들 내의 스케일러블 임베디드 실리콘 브리지 비아 필러들 및 그 제조 방법들 | |
US20110012239A1 (en) | Barrier Layer On Polymer Passivation For Integrated Circuit Packaging | |
US20150332966A1 (en) | Wafer frontside-backside through silicon via | |
US11710636B2 (en) | Metal and spacer patterning for pitch division with multiple line widths and spaces | |
US20120007213A1 (en) | Semiconductor chip and method for fabricating the same | |
US20140035134A1 (en) | Dense interconnect with solder cap (disc) formation with laser ablation and resulting semiconductor structures and packages |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20131010 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20131010 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20141027 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20141110 |
|
A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20150210 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20150508 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20160208 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160608 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20160621 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160711 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20160809 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5988939 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |