JP2016165015A - 不連続な薄い半導体ウェハ表面のフィーチャ - Google Patents
不連続な薄い半導体ウェハ表面のフィーチャ Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 78
- 239000000758 substrate Substances 0.000 claims abstract description 99
- 238000005530 etching Methods 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 30
- 238000004519 manufacturing process Methods 0.000 claims description 27
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 238000004891 communication Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 59
- 229910052710 silicon Inorganic materials 0.000 description 28
- 239000010703 silicon Substances 0.000 description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 27
- 238000010586 diagram Methods 0.000 description 17
- 238000013461 design Methods 0.000 description 14
- 239000000463 material Substances 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 14
- 238000003860 storage Methods 0.000 description 8
- 238000010884 ion-beam technique Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 230000006399 behavior Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000000609 electron-beam lithography Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000032798 delamination Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000004926 polymethyl methacrylate Substances 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
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Abstract
【解決手段】半導体ウェハは、表側および裏側を有する半導体基板、並びに半導体基板の表側上に形成されたフィルムを有する。基板および/またはフィルムは、ウェハ内の残留応力を低減する不連続面を生成する、少なくとも1つのエッチング線を有する。半導体ウェハ内の残留応力を低減することにより、ウェハが薄いときの、ウェハの反りが低減される。さらに、絶縁プラグが、層の短絡を防止するために、エッチング線の一部分を充填するために使用され得る。
【選択図】図5
Description
120 遠隔ユニット
125A、125B、125C ICデバイス
130 遠隔ユニット
140 基地局
150 遠隔ユニット
180 下りリンク信号
190 上りリンク信号
200 設計ワークステーション
201 ハードディスク
203 ドライブ装置
204 記憶媒体
210 回路、回路設計
212 半導体ウェハ
300 積層IC
310 パッケージ基板
320 ダイ
322 パッケージ接続部
324 シリコン貫通電極
330 ダイ
332 パッケージ接続部
400 ダイ
411 基板の裏側
412 基板
413 基板の表側
414 フィルム層
416 シリコン貫通電極
510 ウェハ
512 囲み
514 ダイ
516 エッチング線
518 ダイシング溝
700 ウェハ
710 基板
712 エッチング線
800 ウェハ
810 基板
830 フィルム層
832 エッチング線
834 絶縁プラグ
Claims (20)
- 半導体ウェハであって、
表側および裏側を有する半導体基板と、
前記半導体基板の前記表側上のフィルム層と、を備え、
前記フィルム層および前記半導体基板の少なくとも1つは、少なくとも1つのエッチング線を備える第1の不連続面を有し、前記第1の不連続面は、前記半導体ウェハ内の残留応力を低減する、半導体ウェハ。 - 前記少なくとも1つのエッチング線が、前記半導体ウェハの反りを低減する、請求項1に記載の半導体ウェハ。
- 少なくとも1つのエッチング線を備える第2の不連続面を前記フィルム層内にさらに備え、前記第1の不連続面もまた、前記フィルム層内にある、請求項1に記載の半導体ウェハ。
- 前記第1の不連続面が、前記第2の不連続面と実質的に直交する、請求項3に記載の半導体ウェハ。
- 前記第1の不連続面の少なくとも一部分を充填する絶縁プラグをさらに備える、請求項1に記載の半導体ウェハ。
- 前記絶縁プラグは、酸化ケイ素フィルムを備える、請求項5に記載の半導体ウェハ。
- 前記フィルム層が、窒化ケイ素層を備え、前記第1の不連続面が、前記窒化ケイ素層内にある、請求項1に記載の半導体ウェハ。
- 前記第1の不連続面が、相互に実質的に直交する少なくとも2つのエッチング線を備える、請求項1に記載の半導体ウェハ。
- 音楽プレーヤ、ビデオプレーヤ、娯楽装置、ナビゲーション装置、通信装置、携帯情報端末(PDA)、固定位置データユニット、およびコンピュータから成る群から選択されるデバイスに組み込まれる、請求項1に記載の半導体ウェハ。
- 半導体ウェハを製造する方法であって、
前記半導体ウェハを薄化するステップと、
前記半導体ウェハ内の応力を緩和する不連続面を形成するために、前記半導体ウェハを薄化するステップの後で、前記半導体ウェハに少なくとも1つのエッチング線をエッチングするステップと、
を含む方法。 - 前記半導体ウェハ内に前記少なくとも1つのエッチング線をエッチングするステップが、前記半導体ウェハの半導体基板に少なくとも1つのエッチング線をエッチングするステップを含む、請求項10に記載の方法。
- 前記半導体ウェハに前記少なくとも1つのエッチング線をエッチングするステップが、前記半導体ウェハのフィルム層に少なくとも1つのエッチング線をエッチングするステップを含む、請求項10に記載の方法。
- 前記半導体ウェハのフィルム層に前記少なくとも1つのエッチング線をエッチングするステップが、
前記フィルム層の第1の層に少なくとも1つのエッチング線をエッチングするステップと、
前記フィルム層の第2の層に少なくとも1つのエッチング線をエッチングするステップと、
を含む、請求項12に記載の方法。 - 前記不連続面の少なくとも一部分を絶縁プラグで充填するステップをさらに含む、請求項10に記載の方法。
- 前記絶縁プラグを前記半導体ウェハの表面の高さまで裏面研磨するステップをさらに含む、請求項14に記載の方法。
- 半導体基板と、
フィルム層と、
前記半導体基板および前記フィルム層の少なくとも1つにおける応力を緩和するための手段と、
を備える半導体ウェハ。 - 前記応力を緩和する手段の少なくとも一部分を充填する、絶縁するための手段をさらに備える、請求項16に記載の半導体ウェハ。
- 前記絶縁する手段が、前記応力を緩和する手段の全域で、信号の短絡を防止する、請求項17に記載の半導体ウェハ。
- 前記応力を緩和する手段が、前記フィルム層内に配設される、請求項17に記載の半導体ウェハ。
- 前記応力を緩和する手段が、前記半導体基板内に配設される、請求項16に記載の半導体ウェハ。
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Application Number | Priority Date | Filing Date | Title |
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US12/437,111 | 2009-05-07 | ||
US12/437,111 US8445994B2 (en) | 2009-05-07 | 2009-05-07 | Discontinuous thin semiconductor wafer surface features |
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JP2013190298A Division JP5988939B2 (ja) | 2009-05-07 | 2013-09-13 | 不連続な薄い半導体ウェハ表面のフィーチャ |
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JP2012510024A Pending JP2012526401A (ja) | 2009-05-07 | 2010-05-07 | 不連続な薄い半導体ウェハ表面のフィーチャ |
JP2013190298A Expired - Fee Related JP5988939B2 (ja) | 2009-05-07 | 2013-09-13 | 不連続な薄い半導体ウェハ表面のフィーチャ |
JP2016114447A Pending JP2016165015A (ja) | 2009-05-07 | 2016-06-08 | 不連続な薄い半導体ウェハ表面のフィーチャ |
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JP2012510024A Pending JP2012526401A (ja) | 2009-05-07 | 2010-05-07 | 不連続な薄い半導体ウェハ表面のフィーチャ |
JP2013190298A Expired - Fee Related JP5988939B2 (ja) | 2009-05-07 | 2013-09-13 | 不連続な薄い半導体ウェハ表面のフィーチャ |
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US (2) | US8445994B2 (ja) |
EP (1) | EP2427905B1 (ja) |
JP (3) | JP2012526401A (ja) |
KR (1) | KR101431890B1 (ja) |
CN (1) | CN102414802B (ja) |
TW (1) | TW201104741A (ja) |
WO (1) | WO2010129908A1 (ja) |
Families Citing this family (8)
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US8417922B2 (en) * | 2006-08-02 | 2013-04-09 | Qualcomm Incorporated | Method and system to combine multiple register units within a microprocessor |
US8445994B2 (en) | 2009-05-07 | 2013-05-21 | Qualcomm Incorporated | Discontinuous thin semiconductor wafer surface features |
US20110265869A1 (en) | 2010-04-29 | 2011-11-03 | Skyline Solar, Inc. | Thin film coating pinning arrangement |
JP2013542599A (ja) * | 2010-09-30 | 2013-11-21 | フリースケール セミコンダクター インコーポレイテッド | 半導体ウェハを処理するための方法、半導体ウェハおよび半導体デバイス |
US9355967B2 (en) * | 2013-06-24 | 2016-05-31 | Qualcomm Incorporated | Stress compensation patterning |
US9397051B2 (en) | 2013-12-03 | 2016-07-19 | Invensas Corporation | Warpage reduction in structures with electrical circuitry |
US9761539B2 (en) | 2015-06-29 | 2017-09-12 | Globalfoundries Inc. | Wafer rigidity with reinforcement structure |
KR102634946B1 (ko) | 2016-11-14 | 2024-02-07 | 삼성전자주식회사 | 반도체 칩 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05253835A (ja) * | 1991-12-18 | 1993-10-05 | Philips Gloeilampenfab:Nv | 半導体本体の製造方法 |
JPH0917702A (ja) * | 1995-06-29 | 1997-01-17 | Hitachi Cable Ltd | Si基板及びその製造方法 |
JPH11186119A (ja) * | 1997-12-20 | 1999-07-09 | Samsung Electron Co Ltd | 半導体基板の製造方法 |
US6103593A (en) * | 1998-02-13 | 2000-08-15 | Advanced Micro Devices, Inc. | Method and system for providing a contact on a semiconductor device |
JP2003110017A (ja) * | 2001-09-28 | 2003-04-11 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2003332270A (ja) * | 2002-05-15 | 2003-11-21 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US20070267724A1 (en) * | 2006-05-16 | 2007-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit having stress tuning layer and methods of manufacturing same |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07130836A (ja) * | 1993-11-01 | 1995-05-19 | Matsushita Electric Ind Co Ltd | 素子分離の形成方法 |
US6339251B2 (en) | 1998-11-10 | 2002-01-15 | Samsung Electronics Co., Ltd | Wafer grooves for reducing semiconductor wafer warping |
JP2003115483A (ja) * | 2001-10-05 | 2003-04-18 | Seiko Instruments Inc | 基板の湾曲を低減させる薄膜積層素子の製造方法 |
US7507638B2 (en) | 2004-06-30 | 2009-03-24 | Freescale Semiconductor, Inc. | Ultra-thin die and method of fabricating same |
US7223673B2 (en) * | 2004-07-15 | 2007-05-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of manufacturing semiconductor device with crack prevention ring |
US7576013B2 (en) | 2004-07-27 | 2009-08-18 | United Microelectronics Corp. | Method of relieving wafer stress |
KR101015444B1 (ko) * | 2005-08-17 | 2011-02-18 | 후지쯔 가부시끼가이샤 | 반도체 장치 및 그 제조 방법 |
WO2007023947A1 (ja) * | 2005-08-26 | 2007-03-01 | Hitachi, Ltd. | 半導体装置の製造方法および半導体装置 |
JP4984558B2 (ja) | 2006-02-08 | 2012-07-25 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
US8445994B2 (en) | 2009-05-07 | 2013-05-21 | Qualcomm Incorporated | Discontinuous thin semiconductor wafer surface features |
-
2009
- 2009-05-07 US US12/437,111 patent/US8445994B2/en not_active Expired - Fee Related
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2010
- 2010-05-07 KR KR1020117029193A patent/KR101431890B1/ko not_active IP Right Cessation
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- 2016-06-08 JP JP2016114447A patent/JP2016165015A/ja active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05253835A (ja) * | 1991-12-18 | 1993-10-05 | Philips Gloeilampenfab:Nv | 半導体本体の製造方法 |
JPH0917702A (ja) * | 1995-06-29 | 1997-01-17 | Hitachi Cable Ltd | Si基板及びその製造方法 |
JPH11186119A (ja) * | 1997-12-20 | 1999-07-09 | Samsung Electron Co Ltd | 半導体基板の製造方法 |
US6103593A (en) * | 1998-02-13 | 2000-08-15 | Advanced Micro Devices, Inc. | Method and system for providing a contact on a semiconductor device |
JP2003110017A (ja) * | 2001-09-28 | 2003-04-11 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2003332270A (ja) * | 2002-05-15 | 2003-11-21 | Renesas Technology Corp | 半導体装置およびその製造方法 |
US20070267724A1 (en) * | 2006-05-16 | 2007-11-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Integrated circuit having stress tuning layer and methods of manufacturing same |
Also Published As
Publication number | Publication date |
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CN102414802A (zh) | 2012-04-11 |
JP2014013932A (ja) | 2014-01-23 |
EP2427905A1 (en) | 2012-03-14 |
JP2012526401A (ja) | 2012-10-25 |
KR101431890B1 (ko) | 2014-08-26 |
US20100283131A1 (en) | 2010-11-11 |
US8445994B2 (en) | 2013-05-21 |
EP2427905B1 (en) | 2013-03-20 |
KR20120014026A (ko) | 2012-02-15 |
US8513089B2 (en) | 2013-08-20 |
WO2010129908A1 (en) | 2010-11-11 |
CN102414802B (zh) | 2015-02-18 |
US20130084686A1 (en) | 2013-04-04 |
TW201104741A (en) | 2011-02-01 |
JP5988939B2 (ja) | 2016-09-07 |
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